Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Amendment, filed January 29, 2026, has been fully considered and entered. Accordingly, Claims 1-20 are pending in this application. Claims 1, 8, and 15 are independent claims and have been amended.
It is the position of the Examiner that while Claims 1-20 may contain an abstract mental process, the claims are integrated into a practical application as they provide a technological solution to a technological problem (i.e., memory cache management) and are thus not directed to an abstract idea without significantly more.
In view of paragraph [0093] of the Applicant’s Specification, limiting the claimed computer-readable storage medium to non-transitory embodiments, the rejection of Claims 15-20 under 35 U.S.C. 101 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shah (PG Pub. No. 2016/0117241 A1) and further in view of Dwarkadas (US Patent No. RE41958E1) and Syamala (PG Pub. No. 2020/0349067 A1).
Regarding Claim 1, Shah discloses a method comprising:
determining a work statistic associated with a cache, the work statistic determined based on an execution of a database workload during a first period of time (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining a cache reclamation amount based at least on the acceptable amount of extra work and a current cache size of the database cache (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
providing, to a cache manager, the cache reclamation amount to enable reduction of the current cache size of the database cache by the cache reclamation amount (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Shah does not disclose:
the cache is a database cache;
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time; and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time.
Shah in view of Dwarkadas discloses:
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that increasing the cache size in response to cache miss handling exceeding 3% of total execution time is not patentably distinguishable from the claimed Work Reclamation Ratio); and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that Dwarkadas discloses a selectable amount of acceptable extra work time]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Dwarkadas for the benefit of providing dynamic low-cost configurability trading off size and speed on a per application phase basis (see Dwarkadas, Abstract).
Shah in view of Dwarkadas does not disclose the cache is a database cache. Syamala discloses the cache is a database cache (see Syamala, paragraph [0005], where aspects disclosed herein are directed to a solution for memory management of serverless databases).
Shah, Dwarkadas, and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah and Dwarkadas with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 2, Shah in view of Dwarkadas and Syamala discloses the method of Claim 1, wherein said determining a work statistic comprises at least one of:
determining an amount of time spent populating the database cache from storage (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining an amount of time spent generating a query plan for the database workload and storing the generated query plan in the database cache; or
determining an amount of time spent populating the database cache with security tokens.
Regarding Claim 3, Shah in view of Dwarkadas and Syamala discloses the method of Claim 1, wherein said determining a cache reclamation amount comprises:
determining, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling);
determining, based on the current cache size of the database cache and the determined relationship, a target cache size of the database cache (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling) associated with an amount of extra work that satisfies a predetermined relationship with the acceptable amount of extra work (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
determining the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache (see Shah, paragraph [0058], where technology in this experiment starts with a size for the cache resources that meet the target set for the service level objective [SLO] … the latency shows a corresponding increase or decrease … eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Regarding Claim 4, Shah in view of Dwarkadas and Syamala discloses the method of Claim 3, said determining, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size comprises at least one of:
determining a regression function based on the historical simulated buffer information (see Shah, paragraph [0036], where the storage management computing apparatus produces an estimated cache size vs. cache hit rate curve based on the monitored sampling data gathered back in step 100 [it is the position of the Examiner that an estimated curve is not patentably distinguishable from a regression function]); or
determining a machine learning model trained based on the historical simulated buffer information to predict the target cache size of the database cache based on the current cache size of the database cache and the acceptable amount of extra work.
Regarding Claim 5, Shah in view of Dwarkadas and Syamala discloses the method of Claim 3, wherein said determining the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache comprises:
Shah does not disclose:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit; and
determining the cache reclamation amount based on the cache reclamation limit.
Syamala discloses:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size); and
determining the cache reclamation amount based on the cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 6, Shah in view of Dwarkadas and Syamala discloses the method of Claim 1, wherein said determining a WRR comprises:
determining, based on historical simulated buffer information associated the database cache, a utility cost indicative of an increase in an execution time associated with the execution of the database workload resulting from a cache eviction during the execution of the database workload (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling); and
determining, based on the work statistic, an amount of work associated with the database workload during a predetermined time interval (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]).
Shah does not disclose determining the WRR based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval, and a predetermined WRR limit. Shah in view of Syamala discloses determining the WRR (see Syamala, paragraph [0019], where disclosed solutions are flexible, enabling customization of the aggressiveness and manner of memory reclamation [it is the position of the Examiner that the work reclamation ratio is not patentably distinguishable from a reclamation aggressiveness parameter]) based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval (see Shah, paragraph [0040], where Cost_warming = Latency_miss*(Size_solnN – Size_solnN1), and a predetermined WRR limit (see Syamala, paragraph [0024], where trimming parameters are tailored by the user to adjust to the user’s preference for aggressiveness, such as … the maximum allowable amount of memory to trim per cycle).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 7, Shah in view of Dwarkadas and Syamala discloses the method of Claim 1, further comprising:
Shah does not disclose:
determining that a time elapsed since generation of a recent simulated buffer information associated with the database satisfies a predetermined recency condition; and
periodically providing, to the cache manager, a predetermined cache reclamation amount to enable reduction of the current cache size of the database cache by the predetermined cache reclamation amount, wherein said periodic providing continues until new simulated buffer information is generated for the database cache.
Syamala discloses:
determining that a time elapsed since generation of a recent simulated buffer information associated with the database satisfies a predetermined recency condition (see Syamala, Claim 1, where operations comprise detecting a trigger event for reclaiming memory from a serverless database instance, wherein the trigger event comprises … a timer event); and
periodically providing, to the cache manager, a predetermined cache reclamation amount to enable reduction of the current cache size of the database cache by the predetermined cache reclamation amount, wherein said periodic providing continues until new simulated buffer information is generated for the database cache (see Syamala, paragraph [0046], where in each subsequent iteration, the memory reduces as follows: 100, 75, 56, 42, 43, 24, 18, 13, 10, 10, 10 … see Fig. 2, noting that minimum 204 corresponds to 10 in this example).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 8, Shah discloses a system comprising:
a processor (see Shah, Fig. 2, for processor 24); and
a memory device comprising program code (see Shah, Fig. 2, for memory 26) structured to cause the processor to:
determining a work statistic associated with a cache, the work statistic determined based on an execution of a database workload during a first period of time (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining a cache reclamation amount based at least on the acceptable amount of extra work and a current cache size of the database cache (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
providing, to a cache manager, the cache reclamation amount to enable reduction of the current cache size of the database cache by the cache reclamation amount (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Shah does not disclose:
the cache is a database cache;
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time; and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time.
Shah in view of Dwarkadas discloses:
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that increasing the cache size in response to cache miss handling exceeding 3% of total execution time is not patentably distinguishable from the claimed Work Reclamation Ratio); and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that Dwarkadas discloses a selectable amount of acceptable extra work time]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Dwarkadas for the benefit of providing dynamic low-cost configurability trading off size and speed on a per application phase basis (see Dwarkadas, Abstract).
Shah in view of Dwarkadas does not disclose the cache is a database cache. Syamala discloses the cache is a database cache (see Syamala, paragraph [0005], where aspects disclosed herein are directed to a solution for memory management of serverless databases).
Shah, Dwarkadas, and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah and Dwarkadas with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 9, Shah in view of Dwarkadas and Syamala discloses the system of Claim 8, wherein, to determine a work statistic, the program code is structured to cause the processor to at least one of:
determining an amount of time spent populating the database cache from storage (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining an amount of time spent generating a query plan for the database workload and storing the generated query plan in the database cache; or
determining an amount of time spent populating the database cache with security tokens.
Regarding Claim 10, Shah in view of Dwarkadas and Syamala discloses the system of Claim 8, wherein, to determine a cache reclamation amount, the program code is structured to cause the processor to:
determining, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling);
determining, based on the current cache size of the database cache and the determined relationship, a target cache size of the database cache (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling) associated with an amount of extra work that satisfies a predetermined relationship with the acceptable amount of extra work (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
determining the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache (see Shah, paragraph [0058], where technology in this experiment starts with a size for the cache resources that meet the target set for the service level objective [SLO] … the latency shows a corresponding increase or decrease … eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Regarding Claim 11, Shah in view of Dwarkadas and Syamala discloses the system of Claim 10, wherein, to determine, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size, the program code is structured to cause the processor to at least one of:
determining a regression function based on the historical simulated buffer information (see Shah, paragraph [0036], where the storage management computing apparatus produces an estimated cache size vs. cache hit rate curve based on the monitored sampling data gathered back in step 100 [it is the position of the Examiner that an estimated curve is not patentably distinguishable from a regression function]); or
determining a machine learning model trained based on the historical simulated buffer information to predict the target cache size of the database cache based on the current cache size of the database cache and the acceptable amount of extra work.
Regarding Claim 12, Shah in view of Dwarkadas and Syamala discloses the system of Claim 10, wherein, to determine the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache, the program code is structured to cause the processor to::
Shah does not disclose:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit; and
determining the cache reclamation amount based on the cache reclamation limit.
Syamala discloses:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size); and
determining the cache reclamation amount based on the cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 13, Shah in view of Dwarkadas and Syamala discloses the system of Claim 8, wherein, to determine a WRR, the program code is structured to cause the processor to:
determining, based on historical simulated buffer information associated the database cache, a utility cost indicative of an increase in an execution time associated with the execution of the database workload resulting from a cache eviction during the execution of the database workload (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling); and
determining, based on the work statistic, an amount of work associated with the database workload during a predetermined time interval (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]).
Shah does not disclose determining the WRR based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval, and a predetermined WRR limit. Shah in view of Syamala discloses determining the WRR (see Syamala, paragraph [0019], where disclosed solutions are flexible, enabling customization of the aggressiveness and manner of memory reclamation [it is the position of the Examiner that the work reclamation ratio is not patentably distinguishable from a reclamation aggressiveness parameter]) based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval (see Shah, paragraph [0040], where Cost_warming = Latency_miss*(Size_solnN – Size_solnN1), and a predetermined WRR limit (see Syamala, paragraph [0024], where trimming parameters are tailored by the user to adjust to the user’s preference for aggressiveness, such as … the maximum allowable amount of memory to trim per cycle).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 14, Shah in view of Dwarkadas and Syamala discloses the system of Claim 8, wherein the program code is structured to further cause the processor to:
Shah does not disclose:
determining that a time elapsed since generation of a recent simulated buffer information associated with the database satisfies a predetermined recency condition; and
periodically providing, to the cache manager, a predetermined cache reclamation amount to enable reduction of the current cache size of the database cache by the predetermined cache reclamation amount, wherein said periodic providing continues until new simulated buffer information is generated for the database cache.
Syamala discloses:
determining that a time elapsed since generation of a recent simulated buffer information associated with the database satisfies a predetermined recency condition (see Syamala, Claim 1, where operations comprise detecting a trigger event for reclaiming memory from a serverless database instance, wherein the trigger event comprises … a timer event); and
periodically providing, to the cache manager, a predetermined cache reclamation amount to enable reduction of the current cache size of the database cache by the predetermined cache reclamation amount, wherein said periodic providing continues until new simulated buffer information is generated for the database cache (see Syamala, paragraph [0046], where in each subsequent iteration, the memory reduces as follows: 100, 75, 56, 42, 43, 24, 18, 13, 10, 10, 10 … see Fig. 2, noting that minimum 204 corresponds to 10 in this example).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 15, Shah discloses a computer-readable storage medium comprising executable instructions that, when executed by a processor, cause the processor to:
determining a work statistic associated with a cache, the work statistic determined based on an execution of a database workload during a first period of time (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining a cache reclamation amount based at least on the acceptable amount of extra work and a current cache size of the database cache (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
providing, to a cache manager, the cache reclamation amount to enable reduction of the current cache size of the database cache by the cache reclamation amount (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Shah does not disclose:
the cache is a database cache;
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time; and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time.
Shah in view of Dwarkadas discloses:
determining a work reclamation ratio (WRR) as a ratio of an acceptable increase in the work statistic during a second period of time subsequent to cache reclamation to an amount of work associated with the database workload during the first period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that increasing the cache size in response to cache miss handling exceeding 3% of total execution time is not patentably distinguishable from the claimed Work Reclamation Ratio); and
determining, based on the work statistic and the WRR, an acceptable amount of extra work during the second period of time (see Dwarkadas, column 11, lines 34 – 46, where the TLB configuration is also progressively changed as shown in the flow chart of Fig. 12; the change is performed on an interval-by-interval basis, as indicated in steps 1201 and 1215; a counter tracks TLB miss handler cycles in step 1203; in step 1205, a single bit is added to each TLB entry which is set to indicate whether it has been used in an interval (and is cleared at start of an interval); if the counter exceeds a threshold (which is contemplated to be 3%, although those skilled in the art will be able to select the threshold needed) of the total execution time counter for an interval, as determined in step 1207, the L1 TLB cache size is increased in step 1209 [it is the position of the Examiner that Dwarkadas discloses a selectable amount of acceptable extra work time]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Dwarkadas for the benefit of providing dynamic low-cost configurability trading off size and speed on a per application phase basis (see Dwarkadas, Abstract).
Shah in view of Dwarkadas does not disclose the cache is a database cache. Syamala discloses the cache is a database cache (see Syamala, paragraph [0005], where aspects disclosed herein are directed to a solution for memory management of serverless databases).
Shah, Dwarkadas, and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah and Dwarkadas with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 16, Shah in view of Dwarkadas and Syamala discloses the computer-readable storage medium of Claim 15, wherein, to determine a work statistic, the executable instructions, when executed by the processor, cause the processor to at least one of:
determining an amount of time spent populating the database cache from storage (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]);
determining an amount of time spent generating a query plan for the database workload and storing the generated query plan in the database cache; or
determining an amount of time spent populating the database cache with security tokens.
Regarding Claim 17, Shah in view of Dwarkadas and Syamala discloses the computer-readable storage medium of Claim 15, wherein, to determine a cache reclamation amount, the executable instructions, when executed by the processor, cause the processor to:
determining, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling);
determining, based on the current cache size of the database cache and the determined relationship, a target cache size of the database cache (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling) associated with an amount of extra work that satisfies a predetermined relationship with the acceptable amount of extra work (see Shah, paragraph [0056], where the performance target of the service level objective is an average latency of 6 ms; see also paragraph [0058], where eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective); and
determining the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache (see Shah, paragraph [0058], where technology in this experiment starts with a size for the cache resources that meet the target set for the service level objective [SLO] … the latency shows a corresponding increase or decrease … eventually the performance moves outside the target range of 5.7-6.3 ms; at this point, this technology in this experiment resizes the cache resources to move performance back to the performance target for the service level objective).
Regarding Claim 18, Shah in view of Dwarkadas and Syamala discloses the computer-readable storage medium of Claim 17, wherein, to determine, based on historical simulated buffer information associated the database cache at a plurality of cache sizes, a relationship between a particular cache size of the database cache and a cache utility cost at the particular cache size, the executable instructions, when executed by the processor, cause the processor to at least one of:
determining a regression function based on the historical simulated buffer information (see Shah, paragraph [0036], where the storage management computing apparatus produces an estimated cache size vs. cache hit rate curve based on the monitored sampling data gathered back in step 100 [it is the position of the Examiner that an estimated curve is not patentably distinguishable from a regression function]); or
determining a machine learning model trained based on the historical simulated buffer information to predict the target cache size of the database cache based on the current cache size of the database cache and the acceptable amount of extra work.
Regarding Claim 19, Shah in view of Dwarkadas and Syamala discloses the computer-readable storage medium of Claim 17, wherein, to determine the cache reclamation amount based at least on a difference between the current cache size of the database cache and the target cache size of the database cache, the executable instructions, when executed by the processor, cause the processor to:
Shah does not disclose:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit; and
determining the cache reclamation amount based on the cache reclamation limit.
Syamala discloses:
determining that the difference between the current cache size of the database cache and the target cache size of the database cache satisfies a predetermined relationship with a cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size); and
determining the cache reclamation amount based on the cache reclamation limit (see Syamala, paragraph [0021], where if database activity is low for a configurable time period, then cache reclamation occurs in steps over time (typically gradually) to a predefined minimum cache size).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Regarding Claim 20, Shah in view of Dwarkadas and Syamala discloses the computer-readable storage medium of Claim 15, wherein, to determine a WRR, the executable instructions, when executed by the processor, cause the processor to:
determining, based on historical simulated buffer information associated the database cache, a utility cost indicative of an increase in an execution time associated with the execution of the database workload resulting from a cache eviction during the execution of the database workload (see Shah, Claim 3, further comprising modeling, by the storage controller computing apparatus, the hit or miss rate for each of the plurality of prior workloads over a range of sizes of the cache storage resources, wherein the determining the at least one configuration for the cache storage resources for the one or more current workloads is further based on the modeling); and
determining, based on the work statistic, an amount of work associated with the database workload during a predetermined time interval (see Shah, paragraph [0040], where storage management computing apparatus 12 evaluates the length of time to warm the cache resources allocated to a workload and assigns a cost based on a latency penalty paid while warming those cache resources [it is the position of the Examiner that cache warming time is not patentably distinguishable from time spent populating a cache from storage]).
Shah does not disclose determining the WRR based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval, and a predetermined WRR limit. Shah in view of Syamala discloses determining the WRR (see Syamala, paragraph [0019], where disclosed solutions are flexible, enabling customization of the aggressiveness and manner of memory reclamation [it is the position of the Examiner that the work reclamation ratio is not patentably distinguishable from a reclamation aggressiveness parameter]) based at least on the current utility cost, the current cache size of the database cache, the amount of work associated with the database workload during the predetermined time interval (see Shah, paragraph [0040], where Cost_warming = Latency_miss*(Size_solnN – Size_solnN1), and a predetermined WRR limit (see Syamala, paragraph [0024], where trimming parameters are tailored by the user to adjust to the user’s preference for aggressiveness, such as … the maximum allowable amount of memory to trim per cycle).
Both Shah and Syamala are directed to cache size management. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Shah with Syamala as it amounts to combining known prior art elements to achieve predictable results (see MPEP 2143(I)(A)).
Response to Arguments
Applicant’s Arguments, filed January 29, 2026, have been fully considered, but they are not persuasive in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FARHAD AGHARAHIMI/Examiner, Art Unit 2161
/APU M MOFIZ/Supervisory Patent Examiner, Art Unit 2161