Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
1. This office action is responsive to communication(s) filed on 12/17/2025.
2. Claims 1-20 are presented for examination.
Response to Double Patenting Arguments
3. Claim 1 has been amended and new claims 2-20 added. In view of the present amendment, the outstanding rejection under 35 U.S.C. § 101 has been withdrawal.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-2, 4, 6-7, 11, 13, 15-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 9524786. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims of the examined application are anticipated and the same scope of invention by claims of the reference such as a memory system comprising: a nonvolatile semiconductor memory device including a plurality of memory cells, and a control circuit configured to: send a first command, to cause the nonvolatile semiconductor memory device, read data stored in the memory cells using a first voltage, and send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is lower than the first voltage, after a first time has elapsed (a time for an error detection) from a previous access is executed to the memory cells.
Claims 3 and 12 with a limitation of a refresh operation in a is obvious to a claim 6 of the reference 10916312.
Claims 5 and 14 with a limitation of a value of the second voltage vary according to a temperature in the memory system is obvious to a claim 3 of the reference 10916312.
Claims 8 and 18 with a limitation of wherein the nonvolatile semiconductor memory includes a NAND flash memory is obvious to a claim 17 of the reference 11984167.
Claims 9 and 19 with a limitation of a memory configured to store a firmware for an operation of the control circuit is inherent in the memory system.
Claims 10 and 20 with a limitation of wherein the memory includes a DRAM is inherent in the memory system.
6. Claims 1, 3-5, 7, 11-14 and 17, are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 10916312. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims of the examined application are anticipated and the same scope of invention by claims of the reference such as a nonvolatile semiconductor memory device including a plurality of memory cells, and a control circuit configured to: send a first command, to cause the nonvolatile semiconductor memory device, read data stored in the memory cells using a first voltage, and send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is lower than the first voltage, after a first time has elapsed from a previous access is executed to the memory cells.
Claims 2 and 15 with a limitation of wherein the control circuit is configured to send a third command, to the nonvolatile semiconductor memory device, to read the data using a third voltage that is higher than the first voltage, after a second time has elapsed from the previous access to the memory cells, the second time being shorter than the first time is obvious to a claim 6 of the reference 9524786.
Claims 6 and 16 with a limitation of wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage that is lower than the first voltage is obvious to a claim 8 of the reference 9524786.
Claims 8 and 18 with a limitation of wherein the nonvolatile semiconductor memory includes a NAND flash memory is obvious to a claim 17 of the reference 11984167.
Claims 9 and 19 with a limitation of a memory configured to store a firmware for an operation of the control circuit is inherent in the memory system.
Claims 10 and 20 with a limitation of wherein the memory includes a DRAM is inherent in the memory system.
7. Claims 1-2, 4, 7, 11, 13, 15 and 17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 11475962. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims of the examined application are anticipated and the same scope of invention by claims of the reference such as a nonvolatile semiconductor memory device including a plurality of memory cells, and a control circuit configured to: send a first command, to cause the nonvolatile semiconductor memory device, read data stored in the memory cells using a first voltage, and send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is lower than the first voltage, after a first time has elapsed (a time for an error detection) from a previous access is executed to the memory cells.
Claims 3 and 12 with a limitation of a refresh operation in a is obvious to a claim 6 of the reference 10916312.
Claims 5 and 14 with a limitation of a value of the second voltage vary according to a temperature in the memory system is obvious to a claim 3 of the reference 10916312.
Claims 6 and 16 with a limitation of wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage that is lower than the first voltage is obvious to a claim 8 of the reference 9524786.
Claims 8 and 18 with a limitation of wherein the nonvolatile semiconductor memory includes a NAND flash memory is obvious to a claim 17 of the reference 11984167.
Claims 9 and 19 with a limitation of a memory configured to store a firmware for an operation of the control circuit is inherent in the memory system.
Claims 10 and 20 with a limitation of wherein the memory includes a DRAM is inherent in the memory system.
8. Claims 1-2, 4, 7, 13, 15 and 17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-5 of U.S. Patent No. 11984167. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims of the examined application are anticipated and the same scope of invention by claims of the reference such as a nonvolatile semiconductor memory device including a plurality of memory cells, and a control circuit configured to: send a first command, to cause the nonvolatile semiconductor memory device, read data stored in the memory cells using a first voltage, and send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is lower than the first voltage, after a first time has elapsed (a time for an error detection) 2222from a previous access is executed to the memory cells.
Claims 3 and 12 with a limitation of a refresh operation in a is obvious to a claim 6 of the reference 10916312.
Claims 5 and 14 with a limitation of a value of the second voltage vary according to a temperature in the memory system is obvious to a claim 3 of the reference 10916312.
Claims 6 and 16 with a limitation of wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage that is lower than the first voltage is obvious to a claim 8 of the reference 9524786.
Claims 8 and 18 with a limitation of wherein the nonvolatile semiconductor memory includes a NAND flash memory is obvious to a claim 17 of the reference 11984167.
Claims 9 and 19 with a limitation of a memory configured to store a firmware for an operation of the control circuit is inherent in the memory system.
Claims 10 and 20 with a limitation of wherein the memory includes a DRAM is inherent in the memory system.
Claim Rejections - 35 U.S.C. § 102
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
10. Claims 1-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Cohen et al. US Pub. No. 20090228739 (IDS).
As per claims 1, 4, 11, 13 and , Figs. 1C and 2B of Cohen is directed to a memory systema nonvolatile semiconductor memory device including a plurality of memory cells (Fig. 1A), and a control circuit (170) configured to: send a first command (by RV00, par. 45), to cause the nonvolatile semiconductor memory device, read data stored in the memory cells using a first voltage (RV00), and send a second command (by RV01), to the nonvolatile semiconductor memory device, to read the data using a second voltage (RV01) that is lower than the first voltage, after a first time has elapsed (a time for an error detection, par. 256) from a previous access is executed to the memory cells
As per Claim 2 and 15, Fig. 2B of Cohen discloses wherein the control circuit is configured to send a third command, to the nonvolatile semiconductor memory device, to read the data using a third voltage (RV10) hat is higher than the first voltage, after a second time has elapsed elapsed (a time for an error detection, par. 256) from the previous access to the memory cells, the second time being shorter than the first time.
As per Claim 3 and 12, a paragraph 193 of Cohen discloses wherein in a case where an error is detected on data read in a read operation according to the second command, the control circuit is configured to execute a refresh operation on the data read in the read operation according to the second command.
As per Claim 5 and 14, a paragraph 32 of Cohen discloses wherein a value of the second voltage vary according to a temperature in the memory system.
As per Claims 6-7 and 16-17, a paragraph 76 of Cohen discloses wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage (four or more program levels, par. 76) that is lower than the first voltage.
As per Claims 8 and 18, a paragraph 53 of Cohen discloses wherein the nonvolatile semiconductor memory includes a NAND flash memory.
As per Claims 9 and 19, Figs. 1B and 1C and paragraphs 167 and 178 of Cohen disclose further comprising a memory configured to store a firmware (inherency under a software ROM, par. 167) for an operation of the control circuit. This limitation would be rejected under 103 rejection in view of a paragraph 84 of Yano et al. US Pub. No. 20090222636.
As per Claims 10 and 20, a paragraph 204 of Cohen discloses wherein the memory includes a DRAM.
Response to Arguments
11. Applicant's arguments with respect to the newly added claims have been considered but are moot in view of the new ground(s) of rejections as set forth in the rejection above.
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). See MPEP 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
13. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827