Prosecution Insights
Last updated: July 17, 2026
Application No. 18/654,577

METHOD FOR SEPARATING AND MODELING N-UI JITTER BASED ON SPECTRUM

Non-Final OA §101§102§103§112
Filed
May 03, 2024
Priority
May 05, 2023 — provisional 63/464,517
Examiner
BECKER, BRANDON J
Art Unit
Tech Center
Assignee
Tektronix Inc.
OA Round
1 (Non-Final)
55%
Grant Probability
Moderate
1-2
OA Rounds
1y 5m
Est. Remaining
63%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
119 granted / 218 resolved
-5.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
33 currently pending
Career history
270
Total Applications
across all art units

Statute-Specific Performance

§101
15.6%
-24.4% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 218 resolved cases

Office Action

§101 §102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 14-20 are objected to because of the following informalities: Claim 14 recites “the test and measurement instrument an N-UI jitter analyzer configured to” missing a word i.e. comprising, is, contains etc. Claims 15-20 are objected to based on their inherited deficiencies Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites “a signal under test” and again “a signal under test” it is unclear if these are the same or different signals and further unclear which signal “the signal under test” refers to. For the purposes of examining, they are considered to be the same. Claims 12-13 are rejected based on their inherited deficiencies. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Under step 1, claim 1-20 belongs to a statutory category. Under Step 2A prong 1, the claims as a whole are identified as being directed to a judicial exception as claim 1 recite(s) “a method, comprising: determining a time interval error (TIE) spectrum for a signal under test, the TIE spectrum including a plurality of frequency bins; identifying frequency bins in the TIE spectrum containing deterministic jitter; and determining components of total jitter for the signal under test based on frequency bins in an N-UI spectrum for the signal under test corresponding to the identified frequency bins in the TIE spectrum” which are directed to mathematical concepts and/or mental processes per applicants specification for examples see Par. 21-31, 51, 72 etc. Under Step 2A prong 2, evaluating whether the claim as a whole integrates the exception into a practical application of that exception, the judicial exception is not integrated into a practical application because there are none. Under Step 2B, evaluating additional elements to determine whether they amount to an inventive concept both individually and in combination, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because there are none. Under Step 2A prong 1, the claims as a whole are identified as being directed to a judicial exception as claim 11 and similarly 14 recite(s) “determine a time interval error (TIE) spectrum of a signal under test, the TIE spectrum including a plurality of frequency bins; identify frequency bins in the TIE spectrum containing deterministic jitter in the signal under test; and determine components of total jitter for the signal under test based on frequency bins in an N-UI spectrum for the signal under test corresponding to the identified frequency bins in the TIE spectrum.” which are directed to mathematical concepts and/or mental processes per applicants specification for examples see Par. 21-31, 51, 72 etc. Under Step 2A prong 2, evaluating whether the claim as a whole integrates the exception into a practical application of that exception, the judicial exception is not integrated into a practical application because “a test and measurement instrument, comprising: an N-UI jitter analyzer configured to receive an acquired waveform of a signal under test, the N-UI jitter analyzer configured to:”, “A test and measurement system”, “a device under test” and “a test and measurement instrument” are considered to be data gathering steps required to use the correlation do not add a meaningful limitation to the method as they are insignificant extra-solution activity. Under Step 2B, evaluating additional elements to determine whether they amount to an inventive concept both individually and in combination, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because “a test and measurement instrument, comprising: an N-UI jitter analyzer configured to receive an acquired waveform of a signal under test, the N-UI jitter analyzer configured to:”, “A test and measurement system”, “a device under test” and “a test and measurement instrument” are considered to be adding insignificant extra-solution activity to the judicial exception per MPEP 2106.05(g) (ii) and are well-understood, routine, conventional activities/elements previously known to the industry per MPEP 2106.05(d)(i). Claims 2-10, 12-13, 15-17, and 20 further describe the abstract ideas cited above. In claim 18, “wherein the test and measurement instrument comprises an oscilloscope” is not integrated into a practical application and does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are considered to be data gathering steps required to use the correlation do not add a meaningful limitation to the method as they are insignificant extra-solution activity and are considered to be adding insignificant extra-solution activity to the judicial exception per MPEP 2106.05(g) (ii) and are well-understood, routine, conventional activities/elements previously known to the industry per MPEP 2106.05(d)(i). In claim 19, “wherein the device under test comprises a Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM) memory device” is not integrated into a practical application and does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are considered to be generically recited computer elements do not add a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer and are well-understood, routine, conventional activities/elements previously known to the industry per MPEP 2106.05(d). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 5-12, 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guist (US 8891602 B1). In claim 1, Guist discloses a method, comprising: determining a time interval error (TIE) spectrum (Column 4 Line 61-Column 5 Line “TIE”) for a signal under test (Column 5 Lines 49-67 “SUT”), the TIE spectrum including a plurality of frequency bins (Column 9 Lines 28-39 “frequency bins”); identifying frequency bins in the TIE spectrum containing deterministic jitter (Column 10 Lines 21-33 “TIE deterministic jitter waveform”); and determining components of total jitter for the signal under test (Column 5 Lines 17-45 “statistical components of jitter”) based on frequency bins in an N-UI spectrum (Column 5 Lines 17-45 “periodic jitter” Column 7 Lines 35-47 “jitter spectrum”) for the signal under test corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 28-39). In claim 2, Guist further discloses determining, from the TIE spectrum, the N-UI spectrum for the signal under test (Column 9 Lines 9-40 “TIE jitter spectrums” Column 12 Lines 23-35). In claim 5, Guist further discloses wherein the signal under test comprises a clock signal (Column 11 Lines 1-2 “SUT 110 is a clock timing signal”). In claim 6, Guist further discloses wherein determining components of total jitter for the signal under test based on frequency bins in the N-UI spectrum for the signal under test corresponding to the identified frequency bins in the TIE spectrum further comprises performing adaptive spectral separation of the N-UI spectrum by generating an N-UI deterministic jitter spectrum (Column 5 Lines 17-45 “deterministic jitter”) and generating an N-UI random jitter spectrum for the signal under test based on the identified frequency bins and the N-UI spectrum (Column 5 Lines 17-45 “random jitter”). In claim 7, Guist discloses all of claim 6. Guist further discloses wherein generating the N-UI deterministic jitter spectrum comprises setting to zero all frequency bins in the N-UI spectrum except for frequency bins in the N-UI spectrum corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 27-51 “eliminate the spur” “magnitude of the spur may be set to zero”). In claim 8, Guist discloses all of claim 7. Guist further discloses performing an inverse Fourier transform on the N-UI deterministic jitter spectrum to generate an N-UI deterministic jitter time train (Column 10 Lines 21-33 “inverse discrete Fourier transform”). In claim 9, Guist discloses all of claim 6. Guist further discloses wherein generating the N-UI random jitter spectrum comprises setting to zero all frequency bins in the N-UI spectrum corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 27-51 “eliminate the spur” “magnitude of the spur may be set to zero”). In claim 10, Guist discloses all of claim 9. Guist further discloses characterizing the N-UI random jitter spectrum by determining a root-mean-square (RMS) value and standard deviation value for the N-UI random jitter spectrum (Column 10 Lines 21-33 “root-mean-square”). In claim 11, Guist discloses a test and measurement instrument (Fig. 8), comprising: an N-UI jitter analyzer (Fig. 8, 830/840/340/350) configured to receive an acquired waveform of a signal under test (Column 5 Lines 49-67 “SUT”), the N-UI jitter analyzer configured to: determine a time interval error (TIE) spectrum (Column 4 Line 61-Column 5 Line “TIE”) of a signal under test (Column 5 Lines 49-67 “SUT”), the TIE spectrum including a plurality of frequency bins (Column 9 Lines 28-39 “frequency bins”); identify frequency bins in the TIE spectrum containing deterministic jitter in the signal under test (Column 10 Lines 21-33 “TIE deterministic jitter waveform”); and determine components of total jitter for the signal under test based on frequency bins in an N-UI spectrum (Column 5 Lines 17-45 “periodic jitter” Column 7 Lines 35-47 “jitter spectrum”) for the signal under test corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 28-39). In claim 12, Guist further discloses wherein the N-UI jitter analyzer is further configured to determine, from the TIE spectrum, the N-UI spectrum of the signal under test (Column 9 Lines 9-40 “TIE jitter spectrums” Column 12 Lines 23-35). In claim 14, Guist discloses a test and measurement system (Fig. 8), comprising: a device under test (Fig. 8, 100) configured to provide a signal under test (Fig. 8, 110); and a test and measurement instrument (Fig. 8, 800) coupled to the device under test to receive the signal under test (Fig. 8, 810), the test and measurement instrument an N-UI jitter analyzer “(Fig. 8, 830/840/340/350)” configured to: determine a time interval error (TIE) spectrum for the signal under test (Column 4 Line 61-Column 5 Line “TIE”), the TIE spectrum including a plurality of frequency bins (Column 9 Lines 28-39 “frequency bins”); derive, directly from the TIE spectrum, an N-UI spectrum for the signal under test (Column 5 Lines 17-45 “periodic jitter” Column 7 Lines 35-47 “jitter spectrum”); and perform adaptive spectral separation on the N-UI spectrum to determine components of total jitter for the signal under test (Column 5 Lines 17-45 “deterministic jitter”). In claim 15, Guist further discloses wherein to perform adaptive spectral separation the N-UI jitter analyzer is further configured to: identify frequency bins in the TIE spectrum containing deterministic jitter for the signal under test (Column 10 Lines 21-33 “TIE deterministic jitter waveform”); and generate an N-UI deterministic jitter spectrum (Column 5 Lines 17-45 “deterministic jitter”) and an N-UI random jitter spectrum for the signal under test based on the identified frequency bins and the N-UI spectrum (Column 5 Lines 17-45 “random jitter”). In claim 16, Guist discloses all of claim 15. Guist further discloses wherein to generate the N-UI deterministic jitter spectrum the N-UI jitter analyzer is further configured to set to zero all frequency bins in the N-UI spectrum except for frequency bins in the N-UI spectrum corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 27-51 “eliminate the spur” “magnitude of the spur may be set to zero”). In claim 17, Guist discloses all of claim 16. Guist further discloses wherein to generate the N-UI random jitter spectrum the N-UI jitter analyzer is further configured to set to zero all frequency bins in the N-UI spectrum corresponding to the identified frequency bins in the TIE spectrum (Column 9 Lines 27-51 “eliminate the spur” “magnitude of the spur may be set to zero”). In claim 18, Guist discloses all of claim 15. Guist further discloses wherein the test and measurement instrument comprises an oscilloscope (Fig. 1, 120). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Guist in view of Zhao (US 20200333396 A1). In claim 19, Guist discloses wherein the device under test comprises any type of memory used to store digital data, including but not limited to random access memory (RAM), magnetic, optical, hard drive, SRAM, DRAM, EPROM, EEPROM, flash or other volatile or non-volatile memory (Column 11 Lines 36-48). Guist does not explicitly disclose wherein the device under test comprises a Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM) memory device. Zhao teaches using a Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM) memory device (Par. 3). It would have been obvious to one of ordinary skill in the art before the invention was filed to have wherein the device under test comprises a Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM) memory device based on the teaching of Zhao to the memory of Guist for the understood benefit of the increased speed (Zhao Par. 3). Examiner Note with regards to Prior Art of Record Claims 3-4, 13 and 20 are distinguished over the prior art of record based on the reasons below. In claim 3, 13 and 20, the claim differs from the closest prior arts of record cited above in that it fails to anticipate or render obvious: PNG media_image1.png 160 798 media_image1.png Greyscale in combination with all the other limitations in the claim as claimed and defined by the applicant. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 7590170 B2; US 20090219395 A1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON J BECKER whose telephone number is (571)431-0689. The examiner can normally be reached M-F 9:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby Turner can be reached at (571) 272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.J.B/ Examiner, Art Unit 2857 /SHELBY A TURNER/ Supervisory Patent Examiner, Art Unit 2857
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Prosecution Timeline

May 03, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
55%
Grant Probability
63%
With Interview (+8.2%)
3y 7m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 218 resolved cases by this examiner. Grant probability derived from career allowance rate.

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