DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' response filed on 03/09/26. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments, filed 03/09/26, with respect to non-final rejection dated 12/18/25 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang et al. (US 20190252896 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 15 rejected under 35 U.S.C. 103 as being unpatentable over Sautto et al. (US 20180284826 A1 and hereinafter as Sau) in view of Huang et al. (US 20190252896 A1)
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Regarding claim 1. Sau teaches a low-dropout (LDO) regulator circuit [fig 3, coupled is interpreted as connected between intervening elements] comprising: a first input [1st input of A]; a second input [2nd input of A]; an output [vout];
a first pass transistor [B] including a switch [M1], a source coupled to the first input of the LDO regulator circuit, and a drain coupled to the output of the LDO regulator circuit;
and a second pass transistor [C] including a switch [M2], a source coupled to the second input of the LDO regulator circuit, and a drain coupled to the output of the LDO regulator circuit.
However, Sau does not explicitly mention the first and second pass transistors includes a switchable well. Huang teaches a circuit comprising: switchable well transistor [¶40].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Huang in order to provide a transistor in which by adjusting the well potential, leakage paths through the body diode and parasitic junctions can be minimize which is useful for linear regulators; also it should be noted that while Huang shows 1 switchable well transistor duplication of the essential working components of a device involves only routine skill in the art because if one transistor in a circuit benefits from independent well control, any other transistor performing a similar function would predictably an effect in the same way.
Regarding method claim 15, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Sautto et al. (US 20180284826 A1 and hereinafter as Sau) in view of Huagn et al. (US 20190252896 A1) further in view of Shaw (US 20100060078 A1)
Regarding claim 2. Sau teaches the LDO regulator circuit of claim 1. However, Sau does not explicitly mention a circuit further comprising a logic circuit including: a first output coupled to a gate of the first pass transistor; and a second output coupled to a gate of the second pass transistor, wherein the logic circuit is configured to selectively couple the first output to a power supply rail or to a gate driver node and to selectively couple the second output to the gate driver node or to the power supply rail.
Shaw teaches a logic circuit [fig 2, 170] including: a first output [output of 170 to p12] coupled to a gate of the first pass transistor [p12];
and a second output [output of 170 to p11] coupled to a gate of the second pass transistor, wherein the logic circuit is configured to selectively couple the first output to a power supply rail [function of 170, ¶25] or to a gate driver node and to selectively couple the second output to the gate driver node or to the power supply rail [function of 170, ¶25].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Shaw in order to provide a circuitry that addresses the power source change-over between LDO to the more efficient regulator circuit.
Allowable Subject Matter
Claims 3-14 and 16-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Monica Lewis, can be reached on (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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