DETAILED ACTION
This is in response to the application filed on 5/3/2024 in which claims 1 – 33 are presented for examination.
Status of Claims
Claims 1 – 33 are pending, of which claims 1, 10, 15, 23, and 27 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/8/2024 (3 IDS), 5/31/2024, 7/12/2024, 8/28/2024, 12/9/2024, 4/7/2025, and 8/13/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29 – 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 29 and 30 refer to “a tile register including the one or more registers” and “each of the plurality of tile registers to store one of a plurality of matrices,” respectively.
It is unclear how a register can include one or more registers. It is also unclear how a register can store a matrix.
Claims 1 – 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, 15, 23 refer to the vector registers having a single-instruction multiple-data (SIMD) dimension based on the configuration value for the tiles. An SIMD dimension of registers is not a common phrase in the art. All the dependent claims of these independent claims inherit this rejection based on their dependencies.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 10, 15, and 23 refer to the vector registers having a single-instruction multiple-data (SIMD) dimension. [0051] of Applicant’s PGPub 2025/0004716 mentions parameters including a maximum SIMD dimension. [0067] of Applicant’s PGPub 2025/0004716 “the SIMD (packed data element) dimension M (row height of matrix A).” However, an SIMD dimension of vector registers is not commonly understood in the art. All the dependent claims of these independent claims inherit this rejection based on their dependencies.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 – 10, 13, 15, 16, 23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Haber et al., U.S. Patent Application 2019/0004801 (hereinafter referred to as Haber) in view of Clemons et al., U.S. Patent Application 2017/0004089 (hereinafter referred to as Clemons) (from Applicant’s IDS).
The applied reference has common inventors and a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Referring to claim 1, Haber discloses “A processor” (Fig. 1) “comprising: a register” (Fig. 1 registers 110) ; “decode circuitry to decode an instruction” (Fig. 1 decode circuit 106), “the instruction having a field to identify a plurality of non-consecutive vector registers” ([0131] – [0132] “encodings of the instruction include a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations in memory” and “an SIB type memory operand of the form vm32{x, y, z} may identify a vector array of memory operands specified using SIB type memory addressing”), “a field to identify a register to store a base, and a field to identify a register to store an index” ([0131] base address register and an index register, [0132] “In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements”), “wherein the plurality of non-consecutive vector registers are to have a single-instruction, multiple-data (SIMD) dimension based on the configuration value for the tiles” ([0131] – [0132] “encodings of the instruction include a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations in memory” and “an SIB type memory operand of the form vm32{x, y, z} may identify a vector array of memory operands specified using SIB type memory addressing.” [0060] - [0061] teaches the configuration of the tiles); “and execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction” (Fig. 1 execution circuit 108), “including to:” process “64-bit data elements” as well as “memory locations generated using the base and the index in the plurality of non-consecutive vector registers” ([0132] SIB type memory operand identifies a vector array of memory operands using SIB type memory addressing. [0302] 64-bit registers, [0303] 64-bit packed integer data).
Haber further teaches a load unit ([0311] may include a 'load unit'), but Haber does not appear to explicitly disclose “a register to store a configuration value for tiles” nor “load 64-bit data elements from memory locations.”
However, Clemons discloses “a register to store a configuration value for tiles” ([0095] patch shift with horizontal and vertical step amounts programmable via a special register) and to “load” “data elements from memory locations” ([0034] instruction is a patch load request, [0060] load tile instruction).
Clemons further discloses “the plurality of non-consecutive vector registers are to have a single-instruction, multiple-data (SIMD) dimension based on the configuration value for the tiles” (Fig. 7 striped register file, base, offset, address and [0097] each VPU with data processed in parallel).
Haber and Clemons are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber and Clemons before him or her, to modify the teachings of Haber to include the teachings of Clemons so that tile configuration is stored in a register and an instruction loads tile data elements.
The motivation for doing so would have been to provide a means for a more efficient means for accessing data from different rows that are not stored in a contiguous portion of memory (as taught by Clemons at [0003]).
Therefore, it would have been obvious to combine Clemons with Haber to obtain the invention as specified in the instant claim.
As per claim 6, Haber discloses “the instruction is to indicate a stride” ([0077] At 208, the execution circuit uses the second immediate to set a stride value).
As per claim 7, Haber discloses “the non-consecutive vector registers correspond to different rows delineated based on the stride” (Figs. 13, 16).
As per claim 8, Haber discloses “the processor has a reduced instruction set computing (RISC) architecture” ([0308] RISC).
As per claim 9, Haber discloses “the processor is a central processing unit (CPU), and wherein the CPU further comprises a reorder buffer and register renaming circuitry” ([0305] CPU, [0123] register renaming, [0310] register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s)).
Referring to claim 10, claim 1 recites the corresponding limitations as that of claim 10. Therefore, the rejection of claim 1 applies to claim 10.
Further, Haber discloses “generating addresses of memory locations using the base and the index” ([0131] compute an address using base and index).
Note, claim 13 recites the corresponding limitations of claim 9. Therefore, the rejection of claim 9 applies to claim 13.
Referring to claim 15, claim 1 recites the corresponding limitations as that of claim 15. Therefore, the rejection of claim 1 applies to claim 15.
Further, Clemons discloses “A system on a chip (SoC) comprising: a memory controller; and a processor coupled with the memory controller” (Fig. 10 SoC 1000 with memory interface 1005 and CPU/GPU 1010/1020, [0039] memory controller).
Note, claim 16 recites the corresponding limitations of claim 9. Therefore, the rejection of claim 9 applies to claim 16.
Further, Clemons discloses “the SoC further comprises a bus controller unit” (Fig. 10, CPU, GPU, memory interface, etc can be considered equivalent to a bus controller unit).
Referring to claim 23, claim 10 recites the corresponding limitations as that of claim 23. Therefore, the rejection of claim 10 applies to claim 23.
Further, Haber discloses A non-transitory machine-readable storage medium storing instructions that, when executed by a machine, are to cause the machine to perform operations” ([0344]-[0345]).
Note, claim 26 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 26.
Claims 2, 3, 12, 17, 19, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Agarwal et al., U.S. Patent 5,513,366 (hereinafter referred to as Agarwal) (from Applicant’s IDS).
As per claim 2, Haber discloses “the plurality of non-consecutive vector registers” ([0131] – [0132] “encodings of the instruction include a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations in memory” and “an SIB type memory operand of the form vm32{x, y, z} may identify a vector array of memory operands specified using SIB type memory addressing”)
Neither Haber nor Clemons appears to explicitly disclose “the plurality of non-consecutive vector registers is a configured number of non-consecutive vector registers.”
However, Agarwal discloses “the plurality of non-consecutive vector registers is a configured number of non-consecutive vector registers” (Abstract “vector register lengths, and the number of vector registers, may be dynamically configured by setting the vector size parameter and the offset parameter in the controller” and column 4 lines 30 – 48 “columns in the register array are selected and concatenated to form a vector register”).
Haber, Clemons, and Agarwal are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, and Agarwal before him or her, to modify the teachings of Haber and Clemons to include the teachings of Agarwal so that the plurality of non-consecutive vector registers is a configured number of non-consecutive vector registers.
The motivation for doing so would have been to provide a means for a dynamically reconfiguring a register file to meet the current needs (as described by Agarwal at column 3 line 42 – column 4 line 3).
Therefore, it would have been obvious to combine Agarwal with Haber and Clemons to obtain the invention as specified in the instant claim.
As per claim 3, Agarwal discloses dynamically setting the optimum register configuration for a particular vector calculation (column 3 line 42 – column 4 line 3. Abstract “vector register lengths, and the number of vector registers, may be dynamically configured by setting the vector size parameter and the offset parameter in the controller” and column 4 lines 30 – 48 “columns in the register array are selected and concatenated to form a vector register”).
As such, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to modify Agarwal so that “the plurality of non-consecutive vector registers is four non-consecutive vector registers.”
Note, claim 12 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 12.
Further, as above, Haber discloses “determining a stride indicated by the instruction” ([0077] At 208, the execution circuit uses the second immediate to set a stride value).
Note, claim 17 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 17.
Note, claim 19 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 19.
Note, claim 21 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 21.
Further, Clemons discloses “the SoC further comprises a display unit” (Fig. 10 video interface 1030, Fig. 12 display 1208).
Note, claim 22 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 22.
Further, Haber/Clemons discloses “the SoC further comprises direct memory access (DMA) unit” (Clemons Fig. 10 SoC and Haber Fig. 37 DMA unit 3732).
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Yan et al., U.S. Patent Application 2021/0126641 (hereinafter referred to as Yan).
As per claim 4, neither Haber nor Clemons appears to explicitly disclose “a register to indicate whether the tiles are configured for use.”
However, Yan discloses “a register to indicate whether the tiles are configured for use” ([0092] a tile finite state machine (FSM) register 1222, a tile configuration register 1224).
Haber, Clemons, and Yan are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, and Yan before him or her, to modify the teachings of Haber and Clemons to include the teachings of Yan so that a register indicates whether tiles are configured for use.
The motivation for doing so would have been to provide a means for conveying readiness to an application.
Therefore, it would have been obvious to combine Yan with Haber and Clemons to obtain the invention as specified in the instant claim.
Claims 5, 14, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Nair et al., U.S. Patent Application 2004/0111587 (hereinafter referred to as Nair) (from Applicant’s IDS).
As per claim 5, neither Haber nor Clemons appears to explicitly disclose “the decode circuitry is to decode a second instruction, and further comprising execution circuitry to perform operations corresponding to the second instruction, including to configure the tiles for use.”
However, Nair discloses “the decode circuitry is to decode a second instruction, and further comprising execution circuitry to perform operations corresponding to the second instruction, including to configure the tiles for use” (Figs. 4 – 6 and [0050] - [0055] instruction information to generate desired matrix parameters (i.e., number of rows and columns, element resolution)).
Haber, Clemons, and Nair are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, and Nair before him or her, to modify the teachings of Haber and Clemons to include the teachings of Nair so that a second instruction is used to configure the tiles for use.
The motivation for doing so would have been to configure the matrices/tiles for more efficient computing (as described by Nair at [0006]).
Therefore, it would have been obvious to combine Nair with Haber and Clemons to obtain the invention as specified in the instant claim.
Note, claim 14 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 14.
Note, claim 25 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 25.
Claims 11, 18, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Agarwal, and further in view of Yan.
Note, claim 11 recites the corresponding limitations of claims 2 and 4. Therefore, the rejection of claims 2 and 4 apply to claim 11.
As above, Haber, Clemons, and Agarwal are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, and Agarwal before him or her, to modify the teachings of Haber and Clemons to include the teachings of Agarwal so that the plurality of non-consecutive vector registers is a configured number of non-consecutive vector registers.
The motivation for doing so would have been to provide a means for a dynamically reconfiguring a register file to meet the current needs (as described by Agarwal at column 3 line 42 – column 4 line 3).
Also, Haber, Clemons, Agarwal, and Yan are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, Agarwal, and Yan before him or her, to modify the teachings of Haber, Clemons, and Agarwal to include the teachings of Yan so that a register indicates whether tiles are configured for use.
The motivation for doing so would have been to provide a means for conveying readiness to an application.
Therefore, it would have been obvious to combine Yan with Haber, Clemons, and Agarwal to obtain the invention as specified in the instant claim.
Note, claim 18 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 18.
However, due to dependency on claim 17, claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Agarwal, and further in view of Yan.
Haber, Clemons, Agarwal, and Yan are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, Agarwal, and Yan before him or her, to modify the teachings of Haber, Clemons, and Agarwal to include the teachings of Yan so that a register indicates whether tiles are configured for use.
The motivation for doing so would have been to provide a means for conveying readiness to an application.
Therefore, it would have been obvious to combine Yan with Haber, Clemons, and Agarwal to obtain the invention as specified in the instant claim.
Note, claim 24 recites the corresponding limitations of claim 11. Therefore, the rejection of claim 11 applies to claim 24.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, as applied to claims above, further in view of Agarwal, and further in view of Nair.
Note, claim 20 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 20.
However, due to dependency on claim 17, claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Haber in view of Clemons, further in view of Agarwal, and further in view of Nair.
Haber, Clemons, Agarwal, and Nair are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Haber, Clemons, Agarwal, and Nair before him or her, to modify the teachings of Haber, Clemons, and Agarwal to include the teachings of Nair so that a second instruction is used to configure the tiles for use.
The motivation for doing so would have been to configure the matrices/tiles for more efficient computing (as described by Nair at [0006]).
Therefore, it would have been obvious to combine Nair with Haber, Clemons, and Agarwal to obtain the invention as specified in the instant claim.
Claims 27, 29, 30, 32, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Clemons in view of Haber.
Referring to claim 27, Clemons discloses “An apparatus comprising: programmable configuration storage to store configuration information for a matrix” ([0095] patch shift with horizontal and vertical step amounts programmable via a special register), “the configuration information including a first value corresponding to a number of rows for the matrix, and a second value corresponding to a number of columns for the matrix” ([0048] The patch data structure may also include a second field and a third field that identifies a height and width of the patch, respectively. In one embodiment, the height and width fields may specify a number of rows and columns in the patch, respectively); “decode circuitry to decode a matrix load instruction” ([0034] instruction is a patch load request, [0060] load tile instruction, Fig. 4C and [0070] patch load/store unit 422 decodes commands received), “the matrix load instruction having one or more fields to specify one or more registers” ([0070] load patch command includes an index into the patch table), “an index” ([0070] load patch command includes an index into the patch table), “execution circuitry, coupled to the programmable configuration storage and coupled to the decode circuitry, the execution circuitry to perform operations corresponding to the matrix load instruction, including to load the matrix from memory” ([0034] instruction is a patch load request, [0060] load tile instruction, Fig. 4C and [0070] patch load/store unit 422 decodes commands received), “based on the initial memory address and the” index, “to the one or more registers specified by the one or more fields” ([0049] – [0050]).
Clemons also discloses utilizing “a base” to reference a matrix/tile/patch ([0049] – [0050]).
Clemons does not appear to explicitly disclose “the matrix load instruction having scale-index-base (SIB) addressing information, the SIB addressing information to indicate a scale, an index, a base, and a displacement, the base plus the displacement to reference an initial memory address of the matrix, the index shifted by the scale to represent a stride of the matrix” and “based on the initial memory address and the stride, to the one or more registers specified by the one or more fields.”
However, Haber teaches instruction having scale-index-base (SIB) addressing information, the SIB addressing information to indicate a scale, an index, a base, and a displacement, the base plus the displacement to reference an initial memory address of the matrix, the index shifted by the scale to represent a stride of the matrix” ([0131] instruction includes SIB type memory addressing operand that identifies multiple memory destination locations, index, base, scale. [0131] if a scaling factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to compute a destination address. [0132] SIB type memory operand identifies a vector array of memory operands using SIB type memory addressing, [0299] Scale, Index, Base (SIB), [0300] displacement field).
Clemons and Haber are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clemons and Haber before him or her, to modify the teachings of Clemons to include the teachings of Haber so that scale-index-base (SIB) addressing is utilized.
The motivation for doing so would have been to improve efficiency of array access as well as to add flexibility via the scaling factor for accessing different data types.
Therefore, it would have been obvious to combine Haber with Clemons to obtain the invention as specified in the instant claim.
As per claim 29, Clemons discloses “a tile register including the one or more registers” (Clemons Fig. 7 and [0095] patch shift with horizontal and vertical step amounts programmable via a special register).
As per claim 30, Clemons discloses “the tile register is one of a plurality of tile registers, each of the plurality of tile registers to store one of a plurality of matrices, and the configuration information is to include a plurality of pairs of values, each of the plurality of pairs of values corresponding to a number of rows and a number of columns for one of the plurality of matrices” ([0048] The patch data structure may also include a second field and a third field that identifies a height and width of the patch, respectively. In one embodiment, the height and width fields may specify a number of rows and columns in the patch, respectively).
As per claim 32, Clemons discloses “the apparatus comprises a core coupled to at least one accelerator, the core including the decode circuitry and the at least one accelerator including the execution circuitry” (Fig. 10 CPU cluster 1010 and GPU 1020).
As per claim 33, Haber discloses “the apparatus is a core comprising the decode circuitry and the execution circuitry” ([0046] – [0050] core, Fig. 1 decode circuit 106, execution circuit 108).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Clemons in view of Haber, as applied to claims above, further in view of Nair.
As per claim 31, neither Clemons nor Haber appears to explicitly disclose “the decode circuitry is to decode a second instruction to load the configuration information from one or more memory locations referenced by one or more operands of the second instruction to the programmable configuration storage.”
However, Nair discloses “the decode circuitry is to decode a second instruction to load the configuration information from one or more memory locations referenced by one or more operands of the second instruction to the programmable configuration storage” (Figs. 4 – 6 and [0050] - [0055] instruction information to generate desired matrix parameters (i.e., number of rows and columns, element resolution)).
Clemons, Haber, and Nair are analogous art because they are from the same field of endeavor, which is matrix/tile processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clemons, Haber, and Nair before him or her, to modify the teachings of Clemons and Haber to include the teachings of Nair so that a second instruction is used to configure the tiles for use.
The motivation for doing so would have been to configure the matrices/tiles for more efficient computing (as described by Nair at [0006]).
Therefore, it would have been obvious to combine Nair with Clemons and Haber to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 11418196 is the granted patent to Yan.
U.S. Patent 9934153 is the granted patent to Clemons.
U.S. Patent Application 20240103858 teaches instructions for matrix manipulations and configuring tiles.
‘Dynamic Selection of Tile Sizes’ by Sanket Tavarageri et al. teaches dynamic sizing of tiles.
'Addressing Modes' by S. Dandamudi teaches many addressing modes including based-index, which uses base, index, scale, and displacement.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184