DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) were submitted on 05/03/2024 and 09/05/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0003],” the inductor is in series with a drain channel of the MOSFET” should be --the inductor is in series with a source channel of the MOSFET--.
Paragraph [0025], “VBAT, VBAT_PRO1” are not shown in the drawing.
Paragraph [0025], “the inductor is in series with a drain channel of the MOSFET” should be --the inductor is in series with a source channel of the MOSFET--.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
A battery line of claims 1, 7 and 15,
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 5 are objected to because of the following informalities:
Claim 1 lines 4-5, “a metal-oxide-semiconductor field effect transistor (MOSFET) located within the circuit;” should be -- a metal-oxide-semiconductor field effect transistor (MOSFET);--
Claim 5 line 1, “the response time” should be -- the additional response time--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 lines 6-7 recites “series with a drain channel”. Fig.2 shows inductor L2 connected to source of MOSFET M2. For the purpose of examination, the above limitation is interpreted as -- series with a source channel--.
Claim 1 lines 9-10 recites “a ground channel of the MOSFET”. It is unclear if source, drain, gate or body is considered as ground channel. Specification paragraph [0025] does not provide further clarification. For examination purposes, the above limitation is interpreted as –a ground channel--.
Claims 2-6 are rejected for the same reasons as stated above for claim 1.
Claim 2 lines 1-2 recites “one or more resistors is connected to both the drain channel”. Fig.2 shows resistor R7 connected to source of MOSFET M2. For the purpose of examination, the above limitation is interpreted as -- one or more resistors is connected to both the source channel--.
Claim 4 lines 1-2 recites “the capacitor is located between the transistor and the drain channel”. In fig.2, capacitor C2 is not located between transistor Q4 and drain of MOSFET M2. For the purposes of examination, the above limitation is interpreted as -- the inductor is located between the transistor and the source channel--.
Claim 7 lines 11-12 recites “a diode connected to a third channel of the MOSFET and the base of the transistor”. From fig.2, it is understood that the first channel is source of MOSFET M2, second channel is drain of MOSFET M2 and third channel is gate of MOSFET M2. Also seen in fig.2, diode D4 is connected between drain of M2 and base of Q4. For the purposes of examination, the above limitation is interpreted as -- a diode connected to the second channel of the MOSFET and the base of the transistor--.
Claims 8-14 are rejected for the same reasons as stated above for claim 7.
Claim 10 lines 1-2 recites “the third channel is a source channel of the MOSFET”. Based on fig.2 and limitations in claim 7, the source of transistor M2 is understood to be the first channel. For the purposes of examination, the above limitation is interpreted as -- the first channel is a source channel of the MOSFET--.
Claim 15 is rejected for the same reason as stated above for claim 7.
Claims 16-20 are rejected for the same reasons as stated above for claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dias (A. V. Dias, J. A. Pomilio and S. Finco, "Limitation of Initial Surge in Latching Current Limiters (LCL)," 2023 IEEE 8th Southern Power Electronics Conference and 17th Brazilian Power Electronics Conference (SPEC/COBEP), Florianopolis, Brazil, 2023, pp. 1-7).
Regarding claim 1, Dias teaches a circuit in a vehicle electronic control unit (ECU) (abstract, DC power systems are widely used in the automotive), comprising:
a battery (page 5, protect a 28V DC bus) (it is necessarily true that a battery is present) that includes a battery line (e.g. DC power bus Vbus, figs.1, 5, 7-8, 10) configured to supply voltage to the circuit that is connected to a load side (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged) including at least a capacitor (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged);
a metal-oxide-semiconductor field effect transistor (MOSFET) (e.g. MOSFET M1, fig.10);
an inductor (e.g. inductor Ls, fig.10) in series with the MOSFET (e.g. Ls and M1 are connected in series, fig.10), wherein the inductor is in series with a source channel of the MOSFET (e.g. source of M1 is connected to Ls, fig.10);
a transistor (e.g. transistor Q1, fig.10) in series with the inductor (e.g. emitter of Q1 is in series with transistor M1, fig.10), wherein an emitter channel of the transistor is connected with the inductor (e.g. emitter of Q1 is connected to Ls, fig.10) and a base of the transistor is connected to a ground channel (e.g. base of Q1 is connected to ground via M1, fig.10); and
a diode (e.g. diodes D1 and D2, fig.10) connected to a source channel of the MOSFET (e.g. anode of D1 is connected to source of M1 via Ls and anode of D2 is directly connected to source of M1, fig.10) and the base of the transistor (e.g. anode of D1 is connected to base of Q1 via Ls and Rs, and anode of D2 is connected to base of Q1 via Rs, fig.10);
wherein in response to the transistor and the diode detecting a difference in voltage, the transistor is configured to turn off the MOSFET utilizing a gate terminal of the MOSFET (page 3, During the transient, when the voltage over the inductor tends to be greater than the sum of the diode forward voltage (VD1) and the transistor Q1 emitter-base voltage) (page 1, control unit triggers the deactivation of the MOSFET); and
wherein in response to the MOSFET turning off, the inductor is configured to generate an additional response time to the circuit (page 3, This circuit is an impedance multiplier that increases the effect of the source inductor) (page 1, the control unit triggers the deactivation of the MOSFET) and the capacitor on the load side is configured to supply current to the load side during the additional response time (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged, resulting in a subsequent decline and stabilization of the current at the load's specified level (ILOAD)).
Regarding claim 2, Dias teaches the circuit of claim 1, wherein one or more resistors is connected to both the source channel and gate terminal of the MOSFET (e.g. resistor Rs and RG are connected to source and gate of MOSFET M1, fig.10).
Regarding claim 3, Dias teaches the circuit of claim 1, wherein the transistor is connected to the drain channel of the MOSFET (e.g. collector of Q1 is connected to drain of M1, fig.10).
Regarding claim 4, Dias teaches the circuit of claim 1, wherein the inductor is located between the transistor and the source channel (e.g. inductor Ls is between transistor Q1 and source of M1, fig.10).
Regarding claim 5, Dias teaches the circuit of claim 1, wherein the additional response time is a time constant associated with the inductor (page 3, This circuit is an impedance multiplier that increases the effect of the source inductor).
Regarding claim 6, Dias teaches the circuit of claim 1, wherein the inductor is directly connected to the source channel of the MOSFET (e.g. inductor Ls is directly connected to source of M1, fig.10).
Regarding claim 7, Dias substantially teaches the claim limitations as stated above in claim 1. Dias further teaches a first channel of MOSFET (e.g. source of MOSFET M1, fig.10); a base of the transistor is connected to a second channel of the MOSFET (e.g. base of transistor Q1 is connected to drain of MOSFET M1 via D2 and VBUS, fig.10); a diode connected to the second channel of the MOSFET and the base of the transistor (e.g. anode of D1 and cathode of D2 are connected to drain of M1 via VBUS, fig.10).
Regarding claim 8, Dias teaches the circuit of claim 7, wherein the transistor is configured to turn off the MOSFET utilizing a gate terminal of the MOSFET (page 4, the voltage applied to the gate terminal is controlled by the bipolar transistor during the transient).
Regarding claim 9, Dias teaches the circuit of claim 7, wherein the MOSFET is not located at the load side of the circuit (e.g. MOSFET is in LCL switch between input and output, fig.1).
Regarding claim 10, Dias teaches the circuit of claim 7, wherein the first channel is a source channel of the MOSFET (e.g. source of MOSFET M1, fig.10).
Regarding claim 11, Dias teaches the circuit of claim 10, wherein the source channel is directly connected to the inductor via the battery line (e.g. source of M1 is directly connected to Ls, where battery line is line comprising VBUS, LS and M1, fig.10).
Regarding claim 12, Dias teaches the circuit of claim 10, wherein the source channel is connected to the inductor with no electrical components there between the source channel and the inductor (e.g. there are no components between source of M1 and inductor Ls, fig.10).
Regarding claim 13, Dias teaches the circuit of claim 7, wherein the MOSFET is located on a line side of the circuit (e.g. MOSFET is connected to VBUS on the input side, fig.1), and wherein the line side does not include the capacitor (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged).
Regarding claim 14, Dias teaches the circuit of claim 7, wherein the capacitor on the load side is a bulk capacitor (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged).
Regarding claim 15, the method is rejected for the same reasons as stated above for claim 7.
Regarding claim 16, Dias teaches the method of claim 15, wherein the capacitor is configured to supply current to the load side of the circuit when the MOSFET is turned off (page 1, This constant current persists until the input capacitance of the load (instant C) becomes fully charged, resulting in a subsequent decline and stabilization of the current at the load's specified level (ILOAD)) and the circuit is in a negative transient duration (page 1, In a malfunction situation (instant D), a rapid surge current occurs, surpassing the predefined threshold (instant E). The magnitude of this surge current).
Regarding claim 17, Dias teaches the method of claim 15, wherein the circuit includes one or more resistors in parallel with the MOSFET (e.g. resistors Rs and RG are parallel to MOSFET M1, fig.10).
Regarding claim 20, Dias teaches the method of claim 15, wherein the additional response time is corresponded to a negative transient duration of the circuit (page 1, In a malfunction situation (instant D), a rapid surge current occurs, surpassing the predefined threshold (instant E). The magnitude of this surge current).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Dias (A. V. Dias, J. A. Pomilio and S. Finco, "Limitation of Initial Surge in Latching Current Limiters (LCL)," 2023 IEEE 8th Southern Power Electronics Conference and 17th Brazilian Power Electronics Conference (SPEC/COBEP), Florianopolis, Brazil, 2023, pp. 1-7).
Regarding claim 18, Dias teaches the method of claim 15, wherein the circuit includes a resistor in parallel with both the MOSFET and the inductor (e.g. resistors Rs and RG, fig.10).
Dias does not teach, a resistor greater than or equal to 100k ohms.
It would have been an obvious matter of design choice to a resistor greater than or equal to 100k ohms , since the applicant has not disclosed that a resistor greater than or equal to 100k ohms solves any problem or is for a particular reason. It appears that the claimed invention would perform equally well with a resistor greater than or equal to 100k ohms, as it provides advantage of optimal design.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Dias (A. V. Dias, J. A. Pomilio and S. Finco, "Limitation of Initial Surge in Latching Current Limiters (LCL)," 2023 IEEE 8th Southern Power Electronics Conference and 17th Brazilian Power Electronics Conference (SPEC/COBEP), Florianopolis, Brazil, 2023, pp. 1-7), and further in view of Warnes (US 20220006374 A1).
Regarding claim 19, Dias teaches the method of claim 15.
Dias does not teach, wherein the method includes providing a resistor in parallel to the capacitor on the load side.
Warnes teaches in a similar field of endeavor of preventing transient voltage spikes, a resistor (i.e. resistor 627, fig.6) in parallel to the capacitor on the load side (e.g. resistor 627 is parallel to capacitor 603, fig.6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the resistor in parallel to the capacitor on the load side in Dias, as taught by Warnes, as it provides the advantage of protecting the main circuit from further transient voltage spikes in the form of Resistor, Capacitor, Diode (RCD) snubber.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gagnon (US 20190027945 A1) figs.2-3.
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/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 01/15/2026