Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III, in the reply filed on July 6, 2026, is acknowledged.
Claim Objections
Claims 1 and 8 are objected to because of the following informalities:
In claim 1, lines 10-11, “the lateral dimension” should be “and the lateral dimension”.
In claim 1, line 11, “…the metal layer less than…” should be “the metal layer is less than…”.
In claim 8, line 2, “…positioned over metal layer…” should be “…positioned over the metal layer…”.
In claim 14, line 1, “The method claim 13” should be “The method of claim 13”.
In claim 15, line 1, “The method claim 14” should be “The method of claim 14”.
In claim 16, line 1, “The method claim 15” should be “The method of claim 15”.
In claim 17, line 1, “The method claim 16” should be “The method of claim 16”.
In claim 18, line 1, “The method claim 16” should be “The method of claim 16”.
In claim 19, line 1, “The method claim 18” should be “The method of claim 18”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation, “associated with the opening of the second patterned passivation layer”, in lines 3-4 and lines 5-6. Since the device of claim 16 has this opening in the second patterned passivation layer filled in with a metal structure, the opening recited in this claim no longer exists.
Claim 19 is dependent on claim 18 and thus inherits the deficiencies of the parent claim.
This rejection may be overcome by removing the limitation, “associated with the opening of the second patterned passivation layer”, from lines 3-4 and lines 5-6 in claim 18.
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Figs. 1 and 2 of Shah, reproduced with annotations added by the examiner.
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Figs. 3 and 4 of Shah, reproduced with annotations added by the examiner.
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Figs. 5 and 6 of Shah, reproduced with annotations added by the examiner.
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Figs. 7 and 8 of Shah, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-10, and 13 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Shah et. al., Pub. No. US 2021/0193604, hereafter referred to as Shah.
Regarding claim 1, Shah teaches all of the limitations of the claim in Figs. 1 and 2, reproduced above with annotations added by the examiner: “A bumping assembly for a semiconductor die” (Figs. 1 and 2), “comprising: one or more substrate layers” ([0034]: “Turning now to the drawings, and in particular to FIG. 1, therein is shown a pictorial view of an exemplary embodiment of a semiconductor chip device 10 that includes a semiconductor chip 15 that can be mounted on a circuit board 20, which can be a system board, circuit card, a semiconductor chip package substrate or otherwise.”; Figs. 1 and 2, semiconductor chip 15); “a metal layer formed over the one or more substrate layers” ([0035]: “The conductor pad 32 can be composed of aluminum, copper, gold, platinum, silver, palladium or the like.”; Fig. 2, conductor pad 32), “the metal layer configured for routing of a signal” ([0035]: “The skilled artisan will appreciate that the pad 32 may be part of a topmost layer of interconnect metallization and may be connected to various other electrical structures both laterally and vertically that form up an interconnect system for the semiconductor chip 15.”) “and having a lateral dimension” (Fig. 2; note that the conductor pad 32 has a horizontal extent); “a conductive pad formed over the metal layer and having a lateral dimension” ([0036] and [0039]; Fig. 2, pillar base portion 45 and lateral dimension D1; also see [0037]: “The pillar base portion 45 can consist of copper, silver, gold, platinum, palladium, laminates of these or the like…”); “and an under bump metallization layer formed over the conductive pad and having a lateral dimension” ([0036]: “In this illustrative arrangement, the pillar barrier layer 50 consists of two components, a central portion 60 upon which the solder cap 44 is bonded and a peripheral ring portion 65 that surrounds the central portion 60 and is separated therefrom by a narrow gap 70, which has some dimension x1.” and [0039]; Fig. 2, central portion 60 and lateral dimension D3; also see [0037]: “The pillar barrier layer 50 can consist of nickel, nickel-vanadium or like materials suitable for diffusion and electromigration barriers.”), “such that the metal layer is electrically connected to a bump through the conductive pad and the under bump metallization layer when the bump is implemented over the under bump metallization layer” ([0036]; Fig. 2, note that the solder cap 44 is connected to the central portion 60, which is itself connected to the pillar base portion 45, which in turn is connected to the conductor pad 32), “the lateral dimension of the metal layer less than the lateral dimension of the conductive pad” (Fig. 2, note that the conductor pad 32 has a smaller diameter than the pillar base portion 45).
Regarding claim 2, Shah further teaches “The bumping assembly of claim 1 wherein the lateral dimension of the conductive pad is greater than or equal to the lateral dimension of the under bump metallization layer” ([0039]: “Referring again to FIG. 2, in this illustrative arrangement, the pillar base portion 45 can be constructed with some lateral dimension D1 and the ring portion 65 can be constructed with some lateral dimension D2, which is slightly smaller than the lateral dimension D1 of the underlying pillar base portion 45. … The central portion 60 of the pillar barrier layer 50 can be constructed with some lateral dimension D3 that is smaller than D2…”).
Regarding claim 3, Shah further teaches “The bumping assembly of claim 2 wherein the lateral dimension of the conductive pad is greater than the lateral dimension of the under bump metallization layer” ([0039]: “Referring again to FIG. 2, in this illustrative arrangement, the pillar base portion 45 can be constructed with some lateral dimension D1 and the ring portion 65 can be constructed with some lateral dimension D2, which is slightly smaller than the lateral dimension D1 of the underlying pillar base portion 45. … The central portion 60 of the pillar barrier layer 50 can be constructed with some lateral dimension D3 that is smaller than D2…”).
Regarding claim 4, Shah further teaches “The bumping assembly of claim 1 wherein the lateral dimension of the metal layer being less than the lateral dimension of the conductive pad provides a reduction in congestion of metal layers in a die associated with the bumping assembly, the reduction in congestion of metal layers providing a reduction in size of the die” (Fig. 2, note that the fact that the conductor pad 32 has a smaller diameter than the pillar base portion 45 necessarily reduces the density per unit area of the conductor pads for a given number of bumping assemblies on a device).
Regarding claim 5, Shah further teaches “The bumping assembly of claim 4 wherein the reduction in congestion of metal layers provide a reduction in size of the die when compared to another die without the bumping assembly” (Fig. 2, note that the fact that the conductor pad 32 has a smaller diameter than the pillar base portion 45 necessarily allows for a greater number of bumping assemblies per unit area, thus allowing for smaller die sizes for a given number of bumping assemblies).
Regarding claim 7, Shah further teaches “The bumping assembly of claim 1 wherein the bumping assembly is configured to provide flip-chip mounting functionality for the semiconductor die” ([0034]: “When mounted, the side 22 of the chip 15 faces the circuit board 20. In this illustrative embodiment, and to illustrate certain features, the semiconductor chip 15 is shown detached and flipped over from its mounting position on the circuit board 20.”; Fig. 1, semiconductor chip 15 and circuit board 20).
Regarding claim 8, Shah further teaches “The bumping assembly of claim 1 wherein the conductive pad is positioned over metal layer through a neck portion having a lateral dimension” (Fig. 2, neck portion; note that the neck portion has a horizontal extent).
Regarding claim 9, Shah further teaches “The bumping assembly of claim 8 wherein the lateral dimension of the neck portion is less than the lateral dimension of the metal layer” (Fig. 2, note that the neck portion has a smaller horizontal extent than the conductor pad 32).
Regarding claim 10, Shah further teaches “The bumping assembly of claim 8 wherein the neck portion is formed from same material as the conductive pad” ([0036]; Fig. 2, note that the pillar base portion 45 includes the neck portion, and is thus made of the same material as the rest of it).
Regarding claim 13, Shah teaches all of the limitations of the claim in Figs. 1 and 2: “A method for processing a semiconductor die” (Figs. 1 and 2), “the method comprising: providing or forming one or more substrate layers” ([0034]; Figs. 1 and 2, semiconductor chip 15); “forming a metal layer over the one or more substrate layers” ([0035]: “The conductor pad 32 can be composed of aluminum, copper, gold, platinum, silver, palladium or the like.”; Fig. 2, conductor pad 32), “the metal layer configured for routing of a signal” ([0035]: “The skilled artisan will appreciate that the pad 32 may be part of a topmost layer of interconnect metallization and may be connected to various other electrical structures both laterally and vertically that form up an interconnect system for the semiconductor chip 15.”) “and having a lateral dimension” (Fig. 2; note that the conductor pad 32 has a horizontal extent); “forming a conductive pad over the metal layer and having a lateral dimension” ([0036] and [0039]; Fig. 2, pillar base portion 45 and lateral dimension D1; also see [0037]); “and forming an under bump metallization layer over the conductive pad and having a lateral dimension” ([0036] and [0039]; Fig. 2, central portion 60 and lateral dimension D3; also see [0037]), “such that the metal layer is electrically connected to a bump through the conductive pad and the under bump metallization layer when the bump is implemented over the under bump metallization layer” ([0036]; Fig. 2, note that the solder cap 44 is connected to the central portion 60, which is itself connected to the pillar base portion 45, which in turn is connected to the conductor pad 32), “the lateral dimension of the metal layer less than the lateral dimension of the conductive pad” (Fig. 2, note that the conductor pad 32 has a smaller diameter than the pillar base portion 45).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shah.
Regarding claim 6, Shah teaches “The bumping assembly of claim 1” but does not teach “wherein the ratio of the lateral dimension of the metal layer over the lateral dimension of the conductive pad is less than 0.95, less than 0.90, less than 0.85, less than 0.80, less than 0.75, less than 0.70, less than 0.65, or less than 0.60.”
Shah, however, does teach that the lateral dimension of the metal layer is smaller than that of the conductive pad (Fig. 2, note that the conductor pad 32 has a smaller diameter than the pillar base portion 45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the ratio of the lateral dimension of the metal layer to that of the conductive pad less than 0.95 (which overlaps the other recited ranges) because doing so would allow for the bumping assemblies to be placed closer together, reducing the overall die size, and current case law holds that, in cases wherein the general conditions of a claim are disclosed in the prior art, discovering optimal or working ranges involves only routine skill in the art (see MPEP 2144.05 II A: ““[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”).
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Fig. 1H of Chen, reproduced with annotations added by the examiner.
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Reproduction of Figs. 2A-G of Chen.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Chen et. al., Pub. No. US 2019/0189577, hereafter referred to as Chen.
Regarding claim 11, Shah teaches “The bumping assembly of claim 1” but does not teach “wherein a footprint of each of the under bump metallization layer, the conductive pad and the metal layer has a respective shape, the footprint of the conductive pad and the footprint of the metal layer having a similar shape.” Shah, however, does teach that the pillar base portion and the pillar barrier layer can both have a circular footprint (Shah Fig. 3; note the circular shapes of the pillar base portion 45 and the pillar barrier layer 65), and that these may have other shapes as well, including polygons (Shah [0038]: “It should be understood that while the conductive pillar 25 depicted in FIGS. 1 and 2 is generally circular in footprint, other shapes such as oval, square, rectangular or some other polygon shape could be used as well.”).
Chen, on the other hand, teaches a similar bumping assembly (Chen Fig. 1H) with multiple metallic layers (Chen [0024], [0027], and [0031]; Fig. 1H, conductive pad 122, under bump metallurgy (UBM) 130, first pillar layer 142, and first barrier layer 144) and a solder bump disposed on top (Chen [0031]; Fig. 1H, first solder layer 148). Furthermore, Chen teaches that the lowest of these layers (Chen [0024]; Fig. 1H, conductive pad 122) can have various shapes, including circular (Chen Fig. 2A), elliptical (Chen Fig. 2B), square (Chen Fig. 2C), rectangular (Chen Fig. 2D), diamond (Chen Fig. 2E), hexagonal (Chen Fig. 2F), and octagonal (Chen Fig. 2G).
The different shapes of the conductive layer of Chen can be incorporated into the device of Shah by making the conductor pad of Shah with the same shape as the pillar base portion and pillar barrier layer. The combined device teaches “wherein a footprint of each of the under bump metallization layer, the conductive pad and the metal layer has a respective shape, the footprint of the conductive pad and the footprint of the metal layer having a similar shape”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the conductor pad of Shah have the same shape as the pillar base portion and the pillar barrier layer because doing so would make it easier to form the various elements of the conductive pillar and it would be a simple substitution of one element for another.
Regarding claim 12, the combination of Shah and Chen described in the discussion of claim 11 teaches “The bumping assembly of claim 11 wherein the similar shape of the footprints of the conductive pad and metal layer includes a polygonal shape” (Shah [0038]; Chen Figs. 2F and 2G), “such that the polygonal shape of the footprint of the metal layer is within the polygonal shape of the footprint of the conductive pad” (Shah Fig. 2; note that the fact that the conductor pad 32 has a smaller lateral dimension than the pillar base portion 45 implies that the footprint of the conductor pad 32 is contained within that of the pillar base portion 45).
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Fig. 1C of Jeon, reproduced with annotations added by the examiner.
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Fig. 1E of Jeon, reproduced with annotations added by the examiner.
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Jeon et. al., Pub. No. US 2021/0028137, hereafter referred to as Jeon.
Regarding claim 14, Shah further teaches “The method claim 13” but does not teach “wherein the forming of the metal layer includes forming a patterned layer having an opening, and forming a metal structure within the opening, the opening having a lateral dimension approximately the same as the lateral dimension of the metal layer.” Shah, however, does teach a metal layer ([0035]; Fig. 2, conductor pad 32) with an insulating layer formed around it ([0035]; Fig. 2 passivation layer 36).
Jeon, on the other hand, does teach “wherein the forming of the metal layer includes forming a patterned layer having an opening” (Jeon [0037]: “…the first dielectric layer 101 may undergo a curing process to form a first opening 119.”; Fig. 1C, first dielectric layer 101 and first opening 119), “and forming a metal structure within the opening” (Jeon [0038]: “an under-bump pattern 150 may be formed in the first opening 119.”; Fig. 1E, under-bump pattern 150; also see [0040]: “The under-bump pattern 150 may include metal.”), “the opening having a lateral dimension approximately the same as the lateral dimension of the metal layer” (Jeon Fig. 1E, note that the under-bump pattern 150 has about the same width as the opening 119).
The step of forming a dielectric with an opening and filling the opening with a metal structure taught by Jeon can be incorporated into the process of Shah as a step of forming the passivation layer with an opening and then forming the conductor pad inside the opening.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the process of Shah to form the passivation layer with an opening and then form the conductor pad inside the opening as suggested by Jeon because doing so would allow for better control of the final shape of the conductor pad and it would be a simple substitution of one step for another.
Regarding claim 15, the combination of Shah and Jeon described in the discussion of claim 14 further teaches “The method claim 14 wherein the forming of the conductive pad includes forming a first patterned passivation layer” ([0035]; Fig. 2, polymer layer 38) “having an opening with a lateral dimension less than the lateral dimension of the metal layer” (Fig. 4; note that the polymer layer 38 has an opening 80 with a lateral dimension less than that of the conductor pad 32), “and forming a second patterned passivation layer having an opening over the first patterned passivation layer” ([0041]; Fig. 5, photoresist mask 85; note that the second patterned passivation layer is being interpreted as any insulating layer), “the opening of the second patterned passivation layer having a lateral dimension greater than the lateral dimension of the metal layer” (Fig. 5; note that the photoresist mask 85 has an opening 90 with a lateral dimension larger than that of the conductor pad 32).
Regarding claim 16, the combination of Shah and Jeon as applied to claim 14 above further teaches “The method claim 15 wherein the forming of the conductive pad further includes forming a metal structure within each of the openings of the first and second patterned passivation layers” ([0042]; Fig. 6, note that the pillar base portion 45 is formed within the openings 80 and 90 of both the polymer layer 38 and the photoresist mask 85, respectively).
Regarding claim 17, the combination of Shah and Jeon as applied to claim 14 above further teaches “The method claim 16 wherein the metal structure within the opening of the first patterned passivation layer and the metal structure within the opening of the second patterned passivation layer are formed from same material” ([0042]; Fig. 6, note that, since the pillar base portion 45 is formed as a single unit within both of the openings, both portions are necessarily made of the same material).
Regarding claim 18, the combination of Shah and Jeon as applied to claim 14 above further teaches “The method claim 16, wherein the forming of the under bump metallization layer includes removing the second patterned passivation layer at least about the metal structure associated with the opening of the second patterned passivation layer” (Shah [0043]: “…the photoresist mask 85 depicted in FIG. 6 is stripped from the semiconductor chip 15 using well-known ashing, solvent stripping or combinations of the two…”), “and forming a passivation layer to expose a portion of an upper surface of the metal structure associated with the opening of the second patterned passivation layer” (Shah [0043]: “…another photoresist mask 95 is applied over the UBM seed layer 40 and the pillar base portion 45. The photoresist mask 95 is applied using the same techniques described above in conjunction with the photomask 85 and is appropriately patterned with a central opening 100 over the pillar base portion 45…”; Fig. 7, note that the opening 100 in the photoresist mask 95 exposes the pillar base portion 45).
Regarding claim 19, the combination of Shah and Jeon as applied to claim 14 above further teaches “The method claim 18 wherein the forming of the under bump metallization layer further includes forming the under bump metallization layer over the exposed portion of the upper surface of the metal structure associated with the opening of the second patterned passivation layer to provide a bump space for receiving a bump” (Shah [0036] and [0044]: “Next and as shown in FIG. 8, the semiconductor chip 15 is subjected to a suitable plating process to apply the pillar barrier layer 50, which includes the aforementioned central portion 60 plated in the central opening 100 of the photoresist mask 95…”; Figs. 2 and 8, note that the central portion 60 is formed over an exposed surface of the pillar base portion 45 and has a solder cap 44 disposed over it).
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Figs. 34A-C of Shealy, reproduced with annotations added by the examiner.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Shealy, Pub. No. US 2022/0293455, hereafter referred to as Shealy.
Regarding claim 20, Shah teaches “A semiconductor die” (Shah Fig. 1) “comprising: one or more substrate layers” (Shah [0034]; Fig. 1, semiconductor chip 15); “and an array of bumping assemblies” (Shah [0034]: “While only a few conductive pillars 23 and 25 are depicted, it should be understood that the conductive pillars 23 and 25 can numbers in the hundreds or thousands. … The conductor structures can be solder bumps, pre-solders or others.”; Fig. 1, conductive pillars 23 and 25), “each bumping assembly including a metal layer formed over the one or more substrate layers” (Shah [0035]; Fig. 2, conductor pad 32), “the metal layer configured for routing of a signal” (Shah [0035]: “The skilled artisan will appreciate that the pad 32 may be part of a topmost layer of interconnect metallization and may be connected to various other electrical structures both laterally and vertically that form up an interconnect system for the semiconductor chip 15.”) “and having a lateral dimension” (Shah Fig. 2; note that the conductor pad 32 has a horizontal extent), “the bumping assembly further including a conductive pad formed over the metal layer and having a lateral dimension” (Shah [0036] and [0039]; Fig. 2, pillar base portion 45 and lateral dimension D1; also see [0037]), “and an under bump metallization layer formed over the conductive pad and having a lateral dimension” (Shah [0036] and [0039]; Fig. 2, central portion 60 and lateral dimension D3; also see [0037]), “such that the metal layer is electrically connected to a bump through the conductive pad and the under bump metallization layer when the bump is implemented over the under bump metallization layer” (Shah [0036]; Fig. 2, note that the solder cap 44 is connected to the central portion 60, which is itself connected to the pillar base portion 45, which in turn is connected to the conductor pad 32), “the lateral dimension of the metal layer less than the lateral dimension of the conductive pad” (Shah Fig. 2, note that the conductor pad 32 has a smaller diameter than the pillar base portion 45).
Shah, however, does not teach “an integrated circuit and/or a device implemented on one side of the one or more substrate layers configured to provide radio-frequency functionality” and “(an array of bumping assemblies) implemented on the other side of the one or more substrate layers”.
Shealy, on the other hand, teaches a resonator device (Shealy [0155]; Figs. 34A-C) intended for use in receiving radio signals in a smartphone (Shealy [0042]) that consists of hardware used in receiving said signals (Shealy [0155]; Figs. 34A-C, backside electrode member 3443) on one side of a substrate (Shealy [0155]; epitaxial layer 3420) and bump structures on the other side (Shealy [0155]; Figs. 34A-C, copper pillar structures 3474).
The resonator device of Shealy can be incorporated into the device of Shah by using a similar resonator device as the semiconductor chip. The combined device teaches “an integrated circuit and/or a device implemented on one side of the one or more substrate layers configured to provide radio-frequency functionality” (Shealy [0155]; Figs. 34A-C, backside electrode member 3443) and “(an array of bumping assemblies) implemented on the other side of the one or more substrate layers” (Shealy [0155]; Figs. 34A-C, note that the copper pillar structures 3474 are on an opposite side of the epitaxial layer 3420 from the backside electrode member 3443).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used a resonator device as taught by Shealy as the semiconductor chip of Shah because doing so would provide the device with the ability to pick up RF signals and it would be a simple substitution of one element for another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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