DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 05/06/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 05/06/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 & 11 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Jao et al (US20080068910).
Regarding claim 1, Jao discloses a semiconductor integrated circuit(FIG 5; 100), comprising: a power supply pin configured to receive an external power supply voltage(at node of 120); a fuse memory circuit including a fuse element(FIG 5; 110 comprising fuse elements RF0-Rfn); and a power supply circuit having an output connected to the fuse memory circuit(FIG 5; 120, LS16 & 116 output connected to 110), and configured to receive the external power supply voltage(FIG 5; [0038-0040] discloses VDD_IO, VDD_CORE wherein 116 receiving EPS), the power supply circuit being switchable in response to a control signal between (i) a first state in which an internal power supply voltage of a first voltage level(FIG 5; [0040] discloses 116 based on signal EPS_EN from level shifter, disconnecting and connecting the external programming voltage to programmable unit 110 e.g., programming or preventing from false programming two different states off and on) , which is capable of cutting the fuse element(when programming voltage EPS is connected to 110), is supplied to a power supply line of the fuse memory circuit and (ii) a second state in which the internal power supply voltage of a second voltage level lower than the first voltage level(EPS connected on state, EPS disconnected off state), which is incapable of cutting the fuse element, is supplied to the power supply line of the fuse memory circuit(When programming voltage EPS is disconnected to 110).
Regarding claim 2, Jao discloses a wherein the first voltage level is substantially equal to the external power supply voltage (FIG 5; [0040] when the external programming volage enabling signal EPS_EN to an I/O power domain signal from a core power domain signal that allows for programming 110 e.g., VDD_IO and VDD_CORE is ready during power up operation e.g., substantially equal power to ESP).
Regarding claim 3, Jao discloses wherein the power supply circuit includes: a constant voltage circuit configured to be in a disable state in the first state(FIG 5; [0040] discloses LS16 disconnecting programming voltage EPS), and be in an enable state in the second state and generate the internal power supply voltage of the second voltage level in the power supply line of the fuse memory circuit(connecting EPS programming voltage), and a switch installed between the power supply pin and the power supply line of the fuse memory circuit and configured to be turned on in the first state and turned off in the second state(FIG 5; 116 is between power supply and supply line to 110, configured to be turned on and off e.g., open and close state).
Regarding claim 11, Jao discloses wherein the power supply circuit includes a variable voltage circuit configured to generate the internal power supply voltage of the first voltage level in the power supply line of the fuse memory circuit in the first state and generate the internal power supply voltage of the second voltage level in the power supply line of the fuse memory circuit in the second state (FIG 5-6; [0040-0041] (FIG 5; [0040] discloses LS16 connecting programming voltage EPS(on state) and disconnecting programming voltage EPS (off state) to in the power supply connected 110 e.g., using switching element 116).
Allowable Subject Matter
Claims 4-10 & 12-13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hidaka et al (US6426908 FIG 10; Abstract; col 15, lines 1-19; discloses power supply control circuit to be put in different power supply voltage supplying states in during a delf refresh mode, wherein power supply voltage is equal in voltage level to external power supply voltage EV2).
Nakamura et al (US8791749 FIG 8; discloses power supply control block 110 comprising voltage level sensor circuity 114 and constant current source 112, wherein power generator is connected to memory core 103 and 110).
Okamoto et al (US20020191472 FIG 1; discloses memory 1000 comprising power supply circuit 100 having supply line connected to Vdd, and output connected to memory array 20).
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827