Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4,8-12,14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210012118 A1 (Bohacik) in view of US 20170272740 A1 (Clark).
Regarding claim 1, Bohacik teaches
A device comprising:
memory configured to store image frame data of an image frame;(par 84 “a receiver subsystem coupled to the vision processor, the receiver subsystem including a controller including a plurality of buffers coupled to a plurality of imaging subsystems, the plurality of buffers being configured to receive and store image data from the plurality of imaging subsystems via a plurality of data lanes, a finite state machine that receives synchronization signal pulses via a plurality of synchronization inputs, and a lane merging demultiplexer coupled to the finite state machine and to the plurality of buffers, the lane merging demultiplexer being configured to organize the image data stored on the plurality of buffers to produce image data packets.”) and
one or more processors configured to: (fig 1:110; par 18 “…the vision/radar processor 110 is communicatively coupled to the plurality of imaging/radar subsystems 150…”)
initiate a timing event based on receiving a frame start indication of the image frame, (fig 11:1102,1106; par 59, par 61 “At step 1106, the timing event generator identifies timing events (e.g., frame start, frame end, etc.) embedded in the received image/radar data, including frame start boundaries and frame end boundaries”) the timing event configured to match with a frame end indication;(fig 11:1106,1108; par 61,62 “At step 1108, the timing event generator determines whether a timing event error has occurred. For example, the timing event generator may identify the presence of two consecutive frame start boundaries (i.e., consecutive in that they are not separated by a frame end boundary) … as corresponding to a timing event error.”)
receive, via a communication link, the image frame data subsequent to receiving the frame start indication;(fig 11:1102; par 59 “At step 1102, the MIPI CSI-2 subsystem receives image/radar data from one or more imaging/radar subsystems”) and
responsive to a detected timing event error, initiate a reset operation corresponding to an error in receipt of the frame end indication.(fig 11:1108,1110,1112; par 62 “At step 1108, the timing event generator determines whether a timing event error has occurred.”; par 63, 64 “At step 1112, the timing event generator recovers the timing events that were lost or corrupted as a result of the timing event error.” Par 45 “For example, the timing event generator of the system may generate relevant triggers even in the scenario of loss of a timing event (e.g., frame start/end boundary) in an image/radar data frame. This allows the system to recover from the lost timing event without requiring the full reset/reconfiguration of the link between the system and the imaging/radar subsystems,”; par 43 “The system processor may reset the system in response to the sync alignment error. If the sync alignment error persists after reset, the system processor may provide an indication of a permanent fault of the link and/or sensor associated with the sync alignment error.”; par 54 Although Bohacik focuses on other ways of handling errors besides a full reset, Bohacik does acknowledge that a reset is also an option to handle an error.)
However, although Bohacik detects timing events and expects frame starts and corresponding frame ends, Bohacik does not specifically teach initiating a timer based on receiving a frame start indication of the image frame, the timer configured to expire after an expected receipt time of a frame end indication.
On the other hand, Clark teaches,
A device comprising: (fig 1; par 18)
memory configured to store image frame data of an image frame;(par 27 “In various embodiments, the image signal processor may comprise a memory device (not shown), for example, a frame buffer or line buffers, to temporarily store image data.”) and
one or more processors configured to:
initiate a timer based on receiving a frame start indication of the image frame,(par 31 “The counter 305 may be enabled with a vertical sync signal VSYNC and may also receive a clock signal CLK to begin the period for counting the number of pixels that are read out on a per frame basis.” The VSYNC signal is active during the readout of the entire frame and is explained in par 51 “The vertical sync signal VSYNC remains high during the readout of the entire frame.” and par 52 “After the last row of the frame is read out, the vertical sync signal VSYNC is low and goes high again when read out of a subsequent frame begins.”) the timer configured to expire after an expected receipt time of a frame end indication;(par 31 “The configuration register 300 may be programmed with a timeout value A which may be greater than or equal to the number of clock cycles needed to transmit the pixel data for all pixels 205 in the pixel array 200.” Pixel array is equivalent to image frame.)
receive, via a communication link, the image frame data subsequent to receiving the frame start indication;(fig 7:700; par 53 “When the vertical sync signal VSYNC goes high, the pixels begin to readout (700) and the counter 305 starts counting down (705).”) and
responsive to expiration of the timer, (fig 7:710,715; par 53 “If the counter 305 counts down to zero (710), the output Q … . In this case, if the output Q equals zero, then the number of pixels 205 read out is greater than the timeout value A, which suggests an error condition (715), since the expected number of readout pixels 205 should be less than the timeout value A. As such, if more pixels 205 are read out than expected, the logic gate 310 transmits an error condition (720).”) initiate a corrective operation corresponding to an error in receipt of the frame end indication.(par 53 “The error condition may then be transmitted to the image signal processor 125 to instruct the image signal processor 125 to disregard the pixel data and/or retrieve new pixel data.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Bohacik to incorporate the timer of Clark. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Bohacik -- a need for how to detect and handle errors in image data(Clark par 3 “When the image data is incomplete or contains errors, the embedded system may make decisions based on the incomplete or incorrect data, which may result in the vehicle performing functions and/or actions that are inconsistent with the actual environment.”) -- with Clark providing a known method to solve a similar problem. Clark provides “Various embodiments of the present technology may comprise methods and apparatus for error detection in an imaging system. The method and apparatus may comprise pixels arranged in rows and columns and an error detection circuit receiving pixel data generated by the pixels. The error detection circuit may detect errors and generate an error condition and/or signal, for example if one or more image frames are the same and/or a readout error has occurred”(Clark par 15)
Regarding claim 2, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the one or more processors are configured to disable the timer responsive to receiving the frame end indication.(par 54 “If the counter does not count down to zero (710), this suggests that an error has not occurred (725). In this case, the counter 305 is reset (730) prior to read out of the next line or frame of pixels 205 (710).”)
Regarding claim 3, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the image frame corresponds to an output of a camera coupled to the one or more processors via the communication link.(par 22 “In various embodiments, the image sensor 120 may capture image data. For example, light may enter the imaging system through a lens and strike the image sensor 120. The image sensor 120 may detect and convey the information that constitutes an image, such as by converting the variable attenuation of waves ( as they pass through or reflect off objects) into electronic signals.”)
Regarding claim 4, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the image frame data includes a stream of row data interspersed with blanking intervals.(par 51-52 “The period when the horizontal sync signal HSYNC is low may be referred to as a horizontal blanking period HBLANK. The vertical sync signal VSYNC remains high during the readout of the entire frame. Readout between image frames may comprise a vertical blanking period VBLANK. After the last row of the frame is read out, the vertical sync signal VSYNC is low and goes high again when read out of a subsequent frame begins.”)
However, Clark does not specifically teach packets.
On the other hand, Bohacik teaches,
wherein the image frame data includes a stream of packets of line data(par 47 “The data stream 810 may include a sequence of timing events and data packets (shown here as sequential, labeled blocks).”) interspersed with blanking intervals. (par 47 "SoT" represents a Start of Transmission identifier, "FS" represents a frame start boundary, "EoT represents an End of Transmission identifier, "LPS" represents a low power state ( e.g., occurring between EoT and SoT identifiers”)
Regarding claim 8, Bohacik and Clark teaches
The device of claim 1,
Bohacik further teaches,
wherein the reset operation corresponds to reset of one or more hardware blocks associated with receiving the image frame data via the communication link.(par 44 “When such timing event corruption occurs, conventional receiver systems may merely be capable of indicating a generic error and, in response, stalling further image/radar data reception and potentially resetting/reinitializing the entire link between the imaging/radar subsystems and the conventional receiver.”)
Regarding claim 9, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the timer is configured to expire before an expected receipt time of a next frame start indication.(par 52 “Readout between image frames may comprise a vertical blanking period VBLANK. After the last row of the frame is read out, the vertical sync signal VSYNC is low and goes high again when read out of a subsequent frame begins.”; par 53 “In operation and referring to FIGS. 3 and 7, the configuration register 300 may be programmed with the timeout value A prior to pixel readout. The timeout value A is greater than the number of clock cycles required to read out all of the pixels 205 in one frame. Generally, one pixel is read out per clock cycle, so the time out value A will be greater than the number of pixels 205 in one frame. While the vertical sync signal VSYNC is low, the timeout value A may be loaded into the counter 305.”; par 31 “The configuration register 300 may be programmed with a timeout value A which may be greater than or equal to the number of clock cycles needed to transmit the pixel data for all pixels 205 in the pixel array 200.”)
Regarding claim 10, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the timer is configured to expire during an expected vertical blanking interval after the expected receipt time of the frame end indication.(par 52 “Readout between image frames may comprise a vertical blanking period VBLANK. After the last row of the frame is read out, the vertical sync signal VSYNC is low and goes high again when read out of a subsequent frame begins.”; par 53 “In operation and referring to FIGS. 3 and 7, the configuration register 300 may be programmed with the timeout value A prior to pixel readout. The timeout value A is greater than the number of clock cycles required to read out all of the pixels 205 in one frame. Generally, one pixel is read out per clock cycle, so the time out value A will be greater than the number of pixels 205 in one frame. While the vertical sync signal VSYNC is low, the timeout value A may be loaded into the counter 305.”; par 31 “The configuration register 300 may be programmed with a timeout value A which may be greater than or equal to the number of clock cycles needed to transmit the pixel data for all pixels 205 in the pixel array 200.”)
Regarding claim 11, Bohacik and Clark teaches
The device of claim 1,
Bohacik further teaches,
wherein the reset operation is completed prior to an expected receipt time of a next frame start indication.(par 25 “The system processor 345 may then take appropriate action in response to the interrupt received from the interrupt controller 342 ( e.g., resetting a link between the system 305 and the imaging/radar systems 350, resetting the system 305 itself, or carrying out other safety measures as may be required).” ; par 45 “This allows the system to recover from the lost timing event without requiring the full reset/reconfiguration of the link between the system and the imaging/radar subsystems, and normal operation may subsequently resume.” Normal operation would require that a next frame start would occur after the reset operation is finished. )
Regarding claim 12, Bohacik and Clark teaches
The device of claim 1,
Bohacik further teaches,
wherein the error corresponds to an unbounded frame error.(par 45 “embodiments of the present system may be capable of both identifying and recovering from timing event boundary corruption errors. For example, the occurrence of a timing event boundary corruption error may be identified and reported by a timing event generator of the system, and the system may correct the error so that data reception operations may continue uninterrupted. For example, the timing event generator of the system may generate relevant triggers even in the scenario of loss of a timing event (e.g., frame start/end boundary) in an image/ radar data frame.”)
Regarding claim 14, it is a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to execute instructions that the device of claim 1 implements. Claim 14 is rejected for the same reasons as claim 1.
Regarding claim 15, it is the method that the device of claim 1 implements. Claim 15 is rejected for the same reasons as claim 1.
Regarding claims 16-17, they are the method that the device of claims 3,4 implement and are rejected for the same reasons as claim 3,4.
Claim(s) 5-7,13,18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210012118 A1 (Bohacik) and US 20170272740 A1 (Clark) as applied to claims 1,15 above, and further in view of US 20050212932 A1 (Steimie).
Regarding claim 5, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the one or more processors are configured to update a pixel counter based on receiving a packet of pixel data, wherein the image frame data includes the packet of pixel data.(par 30 “the error detection circuit 130 detects when the number of pixels 205 read out is greater than the number of pixels 205 in the pixel array 200. In real-time operations, it is desirable to utilize "live" image data, so if imaging system 105 reads out a number of pixels 205 that is greater than the number of pixels 205 in the pixel array 200, then this suggests that some of the pixel data has been repeated, and therefore not "live." In an exemplary embodiment, the error detection circuit may count the number of pixels that are read out and generate an error condition if the number of pixels 205 read out is greater than the total number of pixels 205 in the pixel array 200.”. In pixel arrays, pixel count is directly proportional to line count. Par 23 “the image sensor 120 may comprise a pixel array 200 comprising a plurality of pixels 205 arranged in rows and columns.”)
Bohacik further teaches,
wherein the one or more processors are configured to identify a line based on receiving a packet of line data, wherein the image frame data includes the packet of line data.(par 28 “A line done boundary may be inserted at the end of each line or at the end of a predetermined number of lines of image/radar data, and may be interpreted by the vision/radar processor as an indication that data received between two line done boundaries corresponds to a line of the image/radar data or to a predetermined number of lines of the image/radar data, depending on the embodiment.”); par 65 “At step 1114, the timing event generator generates line done and frame boundaries ( e.g., corresponding to timing events).” Bohacik expressly teaches identifying line done boundaries and timing events, and Bohacik generally expects each frame start to have a corresponding frame end.(par 79,87))
However, although Clark teaches updating a pixel counter, and Bohacik teaches identifying lines, Bohacik and Clark do not specifically teach updating a line counter.
On the other hand, Steimie teaches,
An image processing system that receives start of frame signals, start of line, end of line signals, and detects missing lines if the elapsed time between lines exceeds a time out value indicating a missing line,(par 11 “According to the present invention there is first described an improved image sensing device interface unit to interface an image sensing device and a color & format converter (20) that is capable to process the lines and pixels of an image comprising”; par 16-18 “a time interval counter for counting the time interval between the start of line 1 and the start of line 2 of a frame; a time out counter for counting the time interval for any other pair of two consecutive lines and being reset at each start of a new line; a first comparator for comparing the contents of time interval and time out counting means to generate a first interrupt signal, referred to as the 'missing line' interrupt if the time out value is greater than the time interval value and configured to apply said interrupt signal to the data processing and synchronization circuit which in turn generates a clock control signal;” )
wherein the one or more processors are configured to update a line counter based on receiving a packet of line data, wherein the image frame data includes the packet of line data.(par 44 “Error comparator 41 compares the content of line counter 45 (which holds the number of lines per frame) and line register 46 (in block 16') to identify a first type of errors (Error 1).”; par 63 “if at the end of a frame, the content of the line counter 45 is not equal to the value stored in the line register 46, the interrupt signal corresponding to a missing line is set to '1' or the interrupt signal corresponding to a line in excess is set to '1'.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Bohacik and Clark to incorporate the line counter of Steimie. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Bohacik and Clark -- a need for how to deal with missing data, such as missing lines(Steimie par 1 “The present invention also concerns a method for the power management self-optimization of an image sensing device interface unit that is based on complete missing line detection.” par7,18) -- with Steimie providing a known method to solve a similar problem. Steimie provides (Steimie par 11 “According to the present invention there is first described an improved image sensing device interface unit to interface an image sensing device and a color & format converter (20) that is capable to process the lines and pixels of an image comprising”; Steimie par 7 “It is another object of the present invention to provide a method and system for self-optimizing the power management of a sensor interface unit that is based on complete missing line detection.)
Regarding claim 6, Bohacik, Clark, and Steimie teaches
The device of claim 5,
Steimie further teaches,
wherein the one or more processors are configured to, responsive to and based on determining that a value of the line counter does not match an expected line count, designate the image frame data as invalid. (par 44 “Error comparator 41 compares the content of line counter 45 (which holds the number of lines per frame) and line register 46 (in block 16') to identify a first type of errors (Error 1).”; par 63 “if at the end of a frame, the content of the line counter 45 is not equal to the value stored in the line register 46, the interrupt signal corresponding to a missing line is set to '1' or the interrupt signal corresponding to a line in excess is set to '1'.”)
Although Steimie also teaches a timer, Steimie teaches a line timer instead of a frame timer(par 16).
Clark further teaches,
wherein the one or more processors are configured to, responsive to expiration of the timer(fig 7:710,715; par 53 “If the counter 305 counts down to zero (710), the output Q … . In this case, if the output Q equals zero, then the number of pixels 205 read out is greater than the timeout value A, which suggests an error condition (715), since the expected number of readout pixels 205 should be less than the timeout value A. As such, if more pixels 205 are read out than expected, the logic gate 310 transmits an error condition (720).”) and based on determining that a value of the pixel counter does not match an expected pixel count,( par 30 “the error detection circuit 130 detects when the number of pixels 205 read out is greater than the number of pixels 205 in the pixel array 200. In real-time operations, it is desirable to utilize "live" image data, so if imaging system 105 reads out a number of pixels 205 that is greater than the number of pixels 205 in the pixel array 200, then this suggests that some of the pixel data has been repeated, and therefore not "live." In an exemplary embodiment, the error detection circuit may count the number of pixels that are read out and generate an error condition if the number of pixels 205 read out is greater than the total number of pixels 205 in the pixel array 200.”. In pixel arrays, pixel count is directly proportional to line count.) designate the image frame data as invalid. (par 53 “The error condition may then be transmitted to the image signal processor 125 to instruct the image signal processor 125 to disregard the pixel data and/or retrieve new pixel data.”)
Regarding claim 7, Bohacik, Clark, and Steimie teaches
The device of claim 5,
Clark further teaches,
wherein the one or more processors are configured to, responsive to expiration of the timer and based on determining that a value of the line counter matches an expected line count, do not designate the image frame data as invalid. (fig 7:710,715; par 53 “If the counter 305 counts down to zero (710), the output Q … . In this case, if the output Q equals zero, then the number of pixels 205 read out is greater than the timeout value A, which suggests an error condition (715), since the expected number of readout pixels 205 should be less than the timeout value A. As such, if more pixels 205 are read out than expected, the logic gate 310 transmits an error condition (720).”)
However, Clark does not explicitly designate the image frame data as valid either, it just does not mark it as invalid.
On the other hand, Bohacik teaches,
wherein the one or more processors are configured to, responsive to determining a missing frame end, designate the image frame data as valid.(par 45 “… embodiments of the present system may be capable of both identifying and recovering from timing event boundary corruption errors. For example, the occurrence of a timing event boundary corruption error may be identified and reported by a timing event generator of the system, and the system may correct the error so that data reception operations may continue uninterrupted. For example, the timing event generator of the system may generate relevant triggers even in the scenario of loss of a timing event (e.g., frame start/end boundary) in an image/radar data frame. This allows the system to recover from the lost timing event without requiring the full reset/reconfiguration of the link between the system and the imaging/radar subsystems, and normal operation may subsequently resume.” Bohacik teaches generating missing frame end boundaries and continuing operation. )
Regarding claim 13, Bohacik and Clark teaches
The device of claim 1,
Clark further teaches,
wherein the one or more processors are configured to, responsive to receipt of the frame end indication prior to expiration of the timer(par 31 “The configuration register 300 may be programmed with a timeout value A which may be greater than or equal to the number of clock cycles needed to transmit the pixel data for all pixels 205 in the pixel array 200.” Pixel array is equivalent to image frame.)
Bohacik further teaches,
wherein the one or more processors are configured to, responsive to detecting an error, initiate a reset operation.( par 43 “The system processor may reset the system in response to the sync alignment error. If the sync alignment error persists after reset, the system processor may provide an indication of a permanent fault of the link and/or sensor associated with the sync alignment error.” Although Bohacik focuses on other ways of handling errors besides a full reset, Bohacik does acknowledge that a reset is also an option to handle an error.)
However, although Clark teaches an expected frame end timer, and Bohacik teaches reset operations, Bohacik and Clark do not specifically teach responsive to receipt of the frame end indication prior to expiration of the timer, initiate a reset operation corresponding to receipt of the frame end indication.
On the other hand, Steimie teaches,
An image processing system that receives start of frame signals, start of line, end of line signals, and detects missing lines if the elapsed time between lines exceeds a time out value indicating a missing line,(par 11 “According to the present invention there is first described an improved image sensing device interface unit to interface an image sensing device and a color & format converter (20) that is capable to process the lines and pixels of an image comprising”; par 16-18 “a time interval counter for counting the time interval between the start of line 1 and the start of line 2 of a frame; a time out counter for counting the time interval for any other pair of two consecutive lines and being reset at each start of a new line; a first comparator for comparing the contents of time interval and time out counting means to generate a first interrupt signal, referred to as the 'missing line' interrupt if the time out value is greater than the time interval value and configured to apply said interrupt signal to the data processing and synchronization circuit which in turn generates a clock control signal;” )
wherein the one or more processors are configured to, responsive to receipt of the frame end indication prior to expiration of the timer, initiate a reset operation corresponding to receipt of the frame end indication.(par 63 “if at the end of a frame, the content of the line counter 45 is not equal to the value stored in the line register 46, the interrupt signal corresponding to a missing line is set to '1' or the interrupt signal corresponding
to a line in excess is set to '1'.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Bohacik and Clark to incorporate the line counter of Steimie. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Bohacik and Clark -- a need for how to deal with missing data, such as missing lines(Steimie par 1 “The present invention also concerns a method for the power management self-optimization of an image sensing device interface unit that is based on complete missing line detection.” par7,18) -- with Steimie providing a known method to solve a similar problem. Steimie provides (Steimie par 11 “According to the present invention there is first described an improved image sensing device interface unit to interface an image sensing device and a color & format converter (20) that is capable to process the lines and pixels of an image comprising”; Steimie par 7 “It is another object of the present invention to provide a method and system for self-optimizing the power management of a sensor interface unit that is based on complete missing line detection.)
Regarding claims 18-20, they are the method that the device of claims 5-7 implement and are rejected for the same reasons as claims 5-7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20060104367 A1 - Bruls - calculates when synchronization signals should happen and inserts them when they are missing in a video feed. Doesn't explicitly say frame start for the timer start, and doesn't explicitly say reset either.
US 20170075777 A1 - Dunn - checks if the video player is communicating. If not then recovery process starts.
US 20160112159 A1 - Banthia - mitigating effects of unresponsive devices.
US 6115054 A - Giles - uses a frame timeout counter, which forces a frame end if a frame end has not been received yet.
US 20130242749 A1 - Herz - timeout monitoring for commands
US 20240007286 A1 - Miyamoto - uses Camera Serial Interface (CSI) which has frame start for streaming video frames.
US 20200335062 A1 - Huard - deals with multiple displays and tries to synchronize start frames.
US 20180276720 A1 - Yang - par 126 talks about session end frame and times out if the end frame is not received in time.
US 20040085894 A1- Wang - about internet frames, but does have a timeout for frame end.
US5912752A - Mollett - end of frame timeout counter puts in in an end of frame if none is received in time.
US 20140325274 A1 - Mueller - watchdog resets graphics processing unit when timeout.
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