DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1–10 are presented for examination in a non-provisional application filed on 05/06/2024.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority based on an application filed in CHINA (CN) on Jun. 29, 2023 (202310791909.2). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
4. The drawings were received on 09/27/2023 (in the filings). These drawings are acceptable.
Claim Objections
Claims 1–9 use claim phrases of:
“a first memory, receiving a first command corresponding to a first task ...”
“a decoder circuit, decoding the first command ...”
“an event monitor circuit, determining according to the event identifier ...” and
“a filter control circuit, recording second data previously stored ....” each of which explicitly lacks a “linking” or transition word, linking the claimed structure, such as “memory” and “decoder circuit,” with its corresponding functional limitation(s).
For purposes of examination, these limitations will be construed as including a “for” transitioning word, e.g. “a first memory, FOR receiving a first command corresponding to a first task ...” “a decoder circuit, FOR decoding the first command ....”
Dependent claims 2–9 are similarly objected to for either incorporating the aforementioned limitations by dependency or for reciting similar claim expressions, functional limitations or features.
Appropriate corrections are required.
Examiner’s Remarks
5. Examiner refers to and explicitly cites particular pages, sections, figures, paragraphs or columns and lines in the references as applied to Applicant’s claims to the extent practicable to streamline prosecution.
Although the cited portions of the references are representative of the best teachings in the art and are applied to meet the specific limitations of the claims, other uncited but related teachings of the references may be equally applicable as well. It is respectfully requested that, in preparing responses to the rejections, the Applicant fully considers not only the cited portions of the references, but also the references in their entirety, as potentially teaching, suggesting or rendering obvious all or one or more aspects of the claimed invention.
Abbreviations
6. Where appropriate, the following abbreviations will be used when referencing Applicant’s submissions and specific teachings of the reference(s):
i. figure / figures: Fig. / Figs.
ii. column / columns: Col. / Cols.
iii. page / pages: p. / pp.
References Cited
7. (A) Chang et al., US 2022/0138121 A1 (“Chang”).
(B) Bshara et al., US 11,416,749 B2 (“Bshara”).
(C) Jiang et al., US 2019/0073133 A1 (“Jiang”).
Notice re prior art available under both pre-AIA and AIA
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
9. Claims 1–10 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Chang in view of (B) Bshara and (C) Jiang.
See “References Cited” section, above, for full citations of references.
10. Regarding claim 1, (A) Chang teaches/suggests the invention substantially as claimed, including:
“An image processing accelerator device, comprising:
a first memory, receiving a first command corresponding to a first task, ...
(Fig. 1 and ¶ 30: the image sensor 200 may comprise a register bank 210, a command receiver 220, a multiplexer 250, a sensor array 260, a memory 270 and an image signal processor 280, where the sensor array 260, the memory 270 and the image signal processor 280 can be used to accomplish image frame/sequence capturing. The command receiver 220 of the image sensor 200 is arranged to receive commands via the serial bus 150;
¶ 25: the command transmitter 130 delivers multiple register write command with a virtual burst write command is illustrated in FIG. 3);
a decoder circuit, decoding the first command to determine a register to be accessed in an image processing circuit and first data to be written to the register by the first command, ...
(Fig. 4 and ¶¶ 35–36: decoding an address and data in the virtual burst write command to obtain decoded data to be written and decoded addresses; and ... allowing the decoded data to be written to a plurality of registers identified by the decoded addresses);
... execute a second command corresponding to a second task”
(¶ 44: deliver multiple write commands through burst-mode transmission).
Chang do not teach “a wait event command which follows the first command;
... decoding the wait event command to generate an event identifier;
an event monitor circuit, determining according to the event identifier whether the image processing circuit has finished executing the first task, and controlling, after determining that the image processing circuit has finished executing the first task, the image processing circuit to execute a second command corresponding to a second task”
(B) Bshara, in the context of Chang’s teachings, however teaches or suggests implementing:
“a wait event command which follows the first command;
... decoding the wait event command to generate an event identifier;
(Col. 18, lines 30–35: decodes and executes an instruction to wait on the first event. In various examples, processor 510 can distinguish the second event from the first event based on the identifiers associated with the events, an address for each event, or some other encoding for the events;
Col. 18, lines 52–59: to send a write transaction to accelerator 502, which may set an event (e.g., writing “1” to an event register) at accelerator 502. Processor 510 may then proceed to execute a wait for event instruction);
an event monitor circuit, determining according to the event identifier whether the image processing circuit has finished executing the first task, and controlling, after determining that the image processing circuit has finished executing the first task, the image processing circuit to execute a second command corresponding to a second task
(Col. 19, lines 1–5: Processor 510, upon detecting that the event it is waiting for has been set, may then proceed to execute the subsequent instructions;
Col. 3, lines 1–15: an “event” may refer to an indicator of an execution status of an operation associated with one or more instructions .... Events may be used to synchronize or coordinate the operations of different functional blocks of a circuit or a system. For example, one functional block may need to wait for another functional block to complete an operation (which may be indicated by a change of status of the event or a change of value in an event register) before starting an operation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (B) Bshara with those of (A) Chang to decode and execute a wait event instruction before executing subsequent write commands. The motivation or advantage to do so is to coordinate and synchronize (the ordering) of different write operations.
Chang and Bshara do not teach “a filter control circuit, recording second data previously stored in the register, and writing the first data to the register when the first data is different from the second data.”
(C) Jiang however teaches or suggests implementing:
“a filter control circuit, recording second data previously stored in the register, and writing the first data to the register when the first data is different from the second data”
(¶ 71: Deduplication engine manager 410 is responsible for handling the specific reading and writing of data and eliminating data duplication. To that end, deduplication engine manager 410 may include various deduplication engines 420-1 through 420-3. Each deduplication engine 420-1 through 420-3 may determine whether any received user data has been stored before and if so, may prevent storing the same data a second time in memory 115).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (C) Jiang with those of (A) Chang and (B) Bshara to deduplicate data written into the register. The motivation or advantage to do so to optimize memory resources by preventing repetitious storage of data.
11. Regarding claim 2, Bshara teaches or suggests:
“wherein the event monitor circuit compares the event identifier with an identifier returned by the image processing circuit so as to determine whether the image processing circuit has finished executing the first task”
(Col. 18, lines 30–35: decodes and executes an instruction to wait on the first event. In various examples, processor 510 can distinguish the second event from the first event based on the identifiers associated with the events, an address for each event, or some other encoding for the events;
Col. 13, lines 3–22: a change in the value of any event register in event table 422 can cause processing unit 400 to send a notification message. The notification message may be generated by a notification queue management 428 in event management and notification generation circuit 420. For example, when an event register is set, notification queue management 428 may determine to send a notification message 412 that identifies the event and indicates that the event has been set. In various embodiments, notification queue management 428 can also send a notification message when the event register is cleared;
Col. 21, lines 52–56: a corresponding notification message may be generated when an event register is set or cleared during the execution. The notification message may include an identification of the corresponding event and a 55 timestamp associated with the event as described above).
12. Regarding claim 3, Bshara teaches or suggests:
“wherein the event monitor circuit further starts to time a predetermined time upon receiving the event identifier, and compares the event identifier with the identifier returned by the image processing circuit within the predetermined time”
(Col. 12, lines 56–62: by reading the age bit register at a certain time after setting the bits corresponding to the events for synchronizing and controlling the execution of certain instructions or operations, the host driver may determine whether an event that is expected to have occurred has indeed occurred).
13. Regarding claim 4, Jiang teaches or suggests:
“wherein the filter control circuit does not write the first data to the register if the first data is same as the second data”
(¶ 71: Deduplication engine manager 410 is responsible for handling the specific reading and writing of data and eliminating data duplication. To that end, deduplication engine manager 410 may include various deduplication engines 420-1 through 420-3. Each deduplication engine 420-1 through 420-3 may determine whether any received user data has been stored before and if so, may prevent storing the same data a second time in memory 115).
14. Regarding claim 5, Chang and Bshara teach or suggest:
“a command controller, receiving the first command and the wait event command from a second memory, decoding the first command to obtain an address of the register and the first data, and decoding the wait event command to obtain the event identifier; and
(Chang, Fig. 1 and ¶ 30: the image sensor 200 may comprise a register bank 210, a command receiver 220, a multiplexer 250, a sensor array 260, a memory 270 and an image signal processor 280, where the sensor array 260, the memory 270 and the image signal processor 280 can be used to accomplish image frame/sequence capturing. The command receiver 220 of the image sensor 200 is arranged to receive commands via the serial bus 150;
¶ 25: the command transmitter 130 delivers multiple register write command with a virtual burst write command is illustrated in FIG. 3);
Fig. 4 and ¶¶ 35–36: decoding an address and data in the virtual burst write command to obtain decoded data to be written and decoded addresses; and ... allowing the decoded data to be written to a plurality of registers identified by the decoded addresses;
Bshara, Col. 18, lines 30–35: decodes and executes an instruction to wait on the first event. In various examples, processor 510 can distinguish the second event from the first event based on the identifiers associated with the events, an address for each event, or some other encoding for the events);
an event notifier, transmitting the event identifier to the event monitor circuit, and selectively controlling the command controller to start decoding the second command according to a response of the event monitor circuit”
(Chang, ¶ 44: deliver multiple write commands through burst-mode transmission;
Bshara, Col. 18, lines 30–35: decodes and executes an instruction to wait on the first event. In various examples, processor 510 can distinguish the second event from the first event based on the identifiers associated with the events, an address for each event, or some other encoding for the events;
Col. 13, lines 3–22: a change in the value of any event register in event table 422 can cause processing unit 400 to send a notification message. The notification message may be generated by a notification queue management 428 in event management and notification generation circuit 420. For example, when an event register is set, notification queue management 428 may determine to send a notification message 412 that identifies the event and indicates that the event has been set. In various embodiments, notification queue management 428 can also send a notification message when the event register is cleared;
Col. 21, lines 52–56: a corresponding notification message may be generated when an event register is set or cleared during the execution. The notification message may include an identification of the corresponding event and a timestamp associated with the event as described above).
15. Regarding claim 6, Bshara teaches or suggests:
“a multiplexer, receiving an identifier from the image processing circuit; and
an event controller, comparing the identifier from the image processing circuit with the event identifier so as to determine whether the image processing circuit has finished the first task”
(Bshara, Col. 3, lines 1–15: an “event” may refer to an indicator of an execution status of an operation associated with one or more instructions .... Events may be used to synchronize or coordinate the operations of different functional blocks of a circuit or a system. For example, one functional block may need to wait for another functional block to complete an operation (which may be indicated by a change of status of the event or a change of value in an event register) before starting an operation;
Col. 18, lines 30–35: decodes and executes an instruction to wait on the first event. In various examples, processor 510 can distinguish the second event from the first event based on the identifiers associated with the events, an address for each event, or some other encoding for the events;
Col. 13, lines 3–22: a change in the value of any event register in event table 422 can cause processing unit 400 to send a notification message. The notification message may be generated by a notification queue management 428 in event management and notification generation circuit 420. For example, when an event register is set, notification queue management 428 may determine to send a notification message 412 that identifies the event and indicates that the event has been set. In various embodiments, notification queue management 428 can also send a notification message when the event register is cleared;
Col. 21, lines 52–56: a corresponding notification message may be generated when an event register is set or cleared during the execution. The notification message may include an identification of the corresponding event and a timestamp associated with the event as described above).
16. Regarding claim 7, Bshara teaches or suggests:
“wherein the event controller further starts to time a predetermined time upon receiving the event identifier, and compares the event identifier with the identifier returned by the image processing circuit within the predetermined time so as to selectively output a prompt message”
(Col. 21, lines 52–56: a corresponding notification message may be generated when an event register is set or cleared during the execution. The notification message may include an identification of the corresponding event and a 55 timestamp associated with the event as described above;
Col. 12, lines 56–62: by reading the age bit register at a certain time after setting the bits corresponding to the events for synchronizing and controlling the execution of certain instructions or operations, the host driver may determine whether an event that is expected to have occurred has indeed occurred).
Col. 16, lines 14–20: poll the age bit registers through CSRs 416 to determine if events that are expected to occur have occurred and whether events that are not expected to occur have occurred. If an event that is expected to occur has not occurred or if an event that is not expected to occur has occurred, an error ( e.g., a stall) may have occurred during the execution of the instructions;
Col. 21, line 60–61: if an error, a halt, or an interrupt has occurred, a notification message may also be generated).
17. Regarding claim 8, Jiang teaches or suggests:
“a second memory, storing the address of the register and the second data;
a command matcher, reading the second data from the second memory according to the address of the register, and determining whether the second data is same as the first data; and
a command executor, writing the first data to the register when the command matcher determines that the second data is different from the first data”
(¶ 71: Deduplication engine manager 410 is responsible for handling the specific reading and writing of data and eliminating data duplication. To that end, deduplication engine manager 410 may include various deduplication engines 420-1 through 420-3. Each deduplication engine 420-1 through 420-3 may determine whether any received user data has been stored before and if so, may prevent storing the same data a second time in memory 115).
18. Regarding claim 9, Jiang teaches or suggests:
“wherein the command matcher further writes the first data to the second memory when it is determined that the second data is different from the first data, so as to update the second memory by replacing the second data with the first data”
(¶ 71: Deduplication engine manager 410 is responsible for handling the specific reading and writing of data and eliminating data duplication. To that end, deduplication engine manager 410 may include various deduplication engines 420-1 through 420-3. Each deduplication engine 420-1 through 420-3 may determine whether any received user data has been stored before and if so, may prevent storing the same data a second time in memory 115).
19. Regarding claim 10, it is the corresponding method claim reciting similar limitations of commensurate scope as the system (device) of claim 1. Therefore, it is rejected on the same basis as claim 1 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Volpe et al., US 11,281,967 B1, teaching generating a notification message when an indicator of an event used to synchronize the execution of different functional blocks of the integrated circuit changes status.
(b) Barrell et al., US 11,429,587 B1, teaching perform data deduplication operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN C WU whose telephone number is (571)270-5906. The examiner can normally be reached Monday through Friday, 8:30 A.M. to 5:00 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J. Li can be reached on (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN C WU/Primary Examiner, Art Unit 2195
June 10, 2026
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