DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections — 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows (Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966)): determining the scope and contents of the prior art; ascertaining the differences between the prior art and the claims at issue; resolving the level of ordinary skill in the pertinent art; and evaluating evidence of secondary considerations.
4. Claims 1–8, 12, 14–17, 20–22, 28, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679).
In regard to Claim 1:
Lee discloses a class-D amplifier (class-D power amplifier 300, Fig. 2, ¶[0020]), comprising: carrier generation circuitry configured to generate a carrier wave having a variable period but a constant peak-to-peak voltage (triangular wave generator 3024 generating triangular wave VFT with a variable frequency, ¶[0021], ¶[0031], ¶[0038], the storage voltage VS of energy storage module 404 swinging between the high reference voltage VREFH and the low reference voltage VREFL such that the peak-to-peak amplitude remains fixed between the two reference voltages while the period varies, ¶[0030]–[0031], Fig. 4, Fig. 7A); control signal generation circuitry configured to generate at least one control signal (control module 408 comprising flip-flop module 30256 and counter module 30258 generating first control signals FCS1–FCS3 and second control signals SCS1–SCS3, ¶[0025]–[0026], ¶[0029]); a counter configured to iterate a count (counter module 30258 counting the switch signal to generate the plurality of control signals, ¶[0029], ¶[0031]); integration circuitry configured to generate the carrier wave based upon the at least one control signal (first variable current source module 30242 and second variable current source module 30248 charging and discharging energy storage module 404 under control of the control signals to produce the triangular wave VFT, ¶[0025], ¶[0030]–[0031], Figs. 4–6); a PWM signal generator configured to generate a PWM signal by comparing an input voltage to the carrier wave (comparator 3026 comparing the first voltage V1 with the triangular wave VFT to generate the pulse-width modulation signal VPWM, ¶[0021], ¶[0023]); and a bridge circuit configured to generate an output signal from the PWM signal (gate driver 3028 and output stage circuit 3030 composed of P-type transistor 30302 and N-type transistor 30304 generating output voltage DOUT, ¶[0021], ¶[0024]).
Lee does not disclose modulation circuitry configured to generate a modulating wave; noise shaping circuitry configured to perform noise shaping on the modulating wave to produce a noise shaping output; carrier generation circuitry configured to generate a programmable constant representing a fundamental period of a carrier wave; an adder configured to add the programmable constant to the noise shaping output to produce an updated counting top signal representative of a new top count value; or activation of the noise shaping circuitry upon reset of the count.
Park discloses, in Figure 1, noise shaping circuitry of a digital amplifier PWM modulator (noise shaper comprising requantizer 10, clipping unit 20, clipping error compensator 30, and requantization error compensator 40, ¶[0018]) configured to perform noise shaping on an input signal to produce a noise shaping output, wherein the input of the requantizer is the sum of the fed-back error signal and the noise shaper input signal (¶[0021]), the requantization error compensator 40 compares the signal input to the requantizer 10 with the signal output from the requantizer 10 to calculate a requantization error and feeds the calculated error back to the requantizer input through transfer function HNS(z) so that the power of the requantization error is minimized in the audible frequency band (¶[0020]), and the processing is performed digitally on quantized digital values (¶[0019]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the variable-period carrier generation of Lee with the noise shaping taught by Park in order to shape the spectral content of the period-control values so that the resulting quantization artifacts are pushed out of the frequency band of interest, thereby obtaining the predictable benefit of reduced in-band noise and distortion while retaining the electromagnetic interference reduction of the variable-frequency carrier (Lee ¶[0008], ¶[0039]–[0040]; Park ¶[0020], ¶[0025]).
In regard to Claim 2:
Lee further discloses wherein the control signal generation circuitry comprises: polarity generation circuitry configured to invert a polarity signal to produce an updated polarity signal (flip-flop module 30256 having output terminal Q outputting the first switch signal SW1 and inverse output terminal Q̅ outputting the second switch signal SW2, the flip-flop being alternately reset and set by comparison signals CS1 and CS2 so that the switch signals invert once per carrier ramp, ¶[0029]–[0031]); and magnitude generation circuitry configured to generate an updated magnitude signal (counter module 30258 outputting the first control signals FCS1–FCS3 and second control signals SCS1–SCS3 to adjust the variable currents Ic1 and Ic2 based upon the count, ¶[0029], ¶[0031]); wherein the integration circuitry generates the carrier wave based upon the updated polarity signal and the updated magnitude signal (charging by variable current Ic1 when SW1 is asserted and discharging by variable current Ic2 when SW2 is asserted, with the current magnitudes set by the control signals, ¶[0030]–[0031]).
In regard to Claim 3:
Lee further discloses a programmable current source configured: when the polarity signal has a first logic value, to source a current having a magnitude set based upon the updated magnitude signal to an integration input to produce an output integration voltage (first variable current source module 30242 providing variable current Ic1 to charge energy storage module 404 through first switch 30244 when the first switch signal SW1 is asserted, ¶[0030]–[0031], Fig. 4); and when the polarity signal has a second logic value, to sink a current having a magnitude set based upon the updated magnitude signal from the integration input (second variable current source module 30248 discharging the energy storage module 404 through second switch 30246 when the second switch signal SW2 is asserted, ¶[0030]).
In regard to Claim 4:
Lee further discloses wherein the programmable current source comprises: a programmable current source circuit comprising a plurality of current sources and configured to activate a number of the plurality of current sources that is dependent upon the updated magnitude signal (first variable current source module 30242 comprising first fine-tune current circuits 302422, 302424, and 302426, wherein the variable current Ic1 is a sum of the first fixed current IF and a combination of the fine-tune currents IF1, IF2, and IF3 selected by the first control signals FCS1–FCS3, ¶[0032]–[0034], Fig. 5); and a programmable current sink circuit comprising a plurality of current sinks and configured to activate a number of the plurality of current sinks that is dependent upon the updated magnitude signal (second variable current source module 30248 comprising second fine-tune current circuits 302482, 302484, and 302486, wherein the variable current Ic2 is a sum of the second fixed current IS and a combination of the fine-tune currents IS1, IS2, and IS3 selected by the second control signals SCS1–SCS3, ¶[0035]–[0037], Fig. 6).
In regard to Claim 5:
Lee further discloses wherein the programmable current source circuit further comprises a first plurality of switches, each associated with a different one of the plurality of current sources, with activation of a given one of the plurality of current sources being performed by closing of a corresponding switch (first fine-tune switches 3024224, 3024244, and 3024264, each in series with a corresponding first fine-tune current source 3024222, 3024242, and 3024262 and controlled by the corresponding first control signal FCS1, FCS2, FCS3, ¶[0033], Fig. 5); and wherein the programmable current sink circuit further comprises a second plurality of switches, each associated with a different one of the plurality of current sinks (second fine-tune switches 3024822, 3024842, and 3024862, each in series with a corresponding second fine-tune current source 3024824, 3024844, and 3024864 and controlled by the corresponding second control signal SCS1, SCS2, SCS3, ¶[0036], Fig. 6).
In regard to Claim 6:
Lee further discloses wherein the programmable current source circuit activates the number of the plurality of current sources based upon a logical combination of the updated magnitude signal and the polarity signal, and wherein the programmable current sink circuit activates the number of the plurality of current sinks based upon a logical combination of the updated magnitude signal and the polarity signal (the fine-tune currents selected by control signals FCS1–FCS3 and SCS1–SCS3 contribute to the integration node only during the phase in which the corresponding switch signal SW1 or SW2 is asserted, such that the effective activation is a logical combination of the magnitude-selecting control signals output by counter module 30258 and the polarity-defining switch signals output by flip-flop module 30256, ¶[0029]–[0031], ¶[0034], ¶[0037]).
In regard to Claim 7:
Lee further discloses a switch circuit configured to connect the activated number of the plurality of current sources to the integration input when the polarity signal has the first logic value, but to connect the activated number of the plurality of current sinks to the integration input when the polarity signal has the second logic value (switch module 4022 comprising first switch 30244 controlled by first switch signal SW1 to connect the first variable current source module 30242 to the output terminal, and second switch 30246 controlled by second switch signal SW2 to connect the second variable current source module 30248 for discharge, ¶[0026]–[0028], ¶[0030]–[0031], Fig. 4).
In regard to Claim 8:
Lee further discloses wherein the programmable current source comprises: a programmable current source circuit comprising a first current source configured to source a first current to a first node (first fixed current source 302420 providing first fixed current IF, ¶[0032], Fig. 5) and a first plurality of current sources configured to be selectively coupled to the first node, with the number coupled being dependent upon the updated magnitude signal (first fine-tune current circuits 302422, 302424, 302426 selectively contributing fine-tune currents IF1–IF3 according to control signals FCS1–FCS3, ¶[0033]–[0034]); a programmable current sink circuit comprising a second current sink configured to sink a second current from a second node (second fixed current source 302480 providing second fixed current IS to ground, ¶[0035], Fig. 6) and a second plurality of current sinks configured to be selectively coupled to the second node dependent upon the updated magnitude signal (second fine-tune current circuits 302482, 302484, 302486 selectively contributing fine-tune currents IS1–IS3 according to control signals SCS1–SCS3, ¶[0036]–[0037]); and a switch circuit configured to connect the first node to the integration input when the polarity signal has the first logic value, but to connect the second node to the integration input when the polarity signal has the second logic value (first switch 30244 responsive to SW1 and second switch 30246 responsive to SW2, ¶[0026]–[0028], ¶[0030]–[0031])
In regard to Claim 12:
Lee does not disclose that the modulated carrier generation circuitry is implemented digitally in an integrated circuit such that the modulating wave, the noise shaping output, the fundamental period of the carrier wave, the new top count value, and the count are represented as digital values.
However, Park discloses that the noise shaping circuitry is implemented digitally in an integrated circuit wherein the processed signals are represented as series of digital values (the requantizer 10 rounding the lower digits so that an input signal having quantization digit B is represented by fewer Brq digits, with all noise shaper processing performed by digital signal processing on quantized digital values, ¶[0018]–[0019], ¶[0021]–[0022]; hardware implementation of the noise shaper, ¶[0033]; the number of digital multiplications performed per sample for oversampling and noise shaping, ¶[0066]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee to implement the modulated carrier generation circuitry digitally as taught by Park, the noise shaping output, the fundamental period of the carrier wave, the new top count value and the count are represented as digital values, in order to provide a fully digital implementation that improves processing flexibility programmability, and integration while achieving the predictable benefits of digital signal processing.
In regard to Claim 14:
Lee further discloses a constant peak-to-peak voltage, variable period carrier generation circuit comprising: a programmable current source comprising a first current source configured to source a first current to a first node (first fixed current source 302420 providing fixed current IF, ¶[0032]) and a plurality of current sources configured to be selectively coupled to the first node by respective switches (first fine-tune current circuits with fine-tune switches controlled by FCS1–FCS3, ¶[0033]–[0034], Fig. 5); an integration capacitor connected between the first node and ground (energy storage module 404, e.g. a capacitor, having a first terminal coupled to the output terminal and a second terminal coupled to ground GND, ¶[0025], ¶[0028], Fig. 4); and switched discharge upon assertion of the polarity signal (discharge of energy storage module 404 to ground GND through second switch 30246 upon assertion of second switch signal SW2, ¶[0030]), the charging with a magnitude-controlled current and the switched discharging together generating the constant peak-to-peak voltage, variable period carrier (storage voltage bounded between VREFH and VREFL with variable frequency, ¶[0030]–[0031], Fig. 7A).
In regard to Claim 15:
Lee does not disclose noise shaping circuitry comprising: an input summer configured to combine an error signal with the input to produce a quantizer input signal; a quantizer receiving the quantizer input signal and configured to requantize by a scaling relationship; an error summer configured to compare the quantizer input signal and the quantizer output signal to produce an intermediate output; and a noise shaping filter configured to apply a noise shaping filter function to the intermediate output to produce the error signal.
However, Park discloses noise shaping circuitry comprising: an input summer configured to combine an error signal with the input to produce a quantizer input signal (the requantizer input signal being the sum of the signal fed back by the requantization error compensator 40 and the noise shaper input signal, ¶[0021], Fig. 1); a quantizer receiving the quantizer input signal and configured to requantize by a scaling relationship (requantizer 10 rounding an input having quantization digit B to fewer Brq digits, corresponding to dividing the quantizer input signal by a scaling factor to produce the noise shaping output and multiplying by the scaling factor to produce the quantizer output signal, ¶[0019]); an error summer configured to compare the quantizer input signal and the quantizer output signal to produce an intermediate output (requantization error compensator 40 comparing the signal input to the requantizer 10 with the signal output from the requantizer 10 to calculate the requantization error erq, ¶[0020], Fig. 1); and a noise shaping filter configured to apply a noise shaping filter function to the intermediate output to produce the error signal (transfer function HNS(z) of the requantization error compensator, by which the power of the requantization error is minimized in the audible frequency band, ¶[0020]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee to include the noise shaping circuitry taught by Park in order to perform digital noise shaping of the modulating signal, thereby reducing in-band quantization noise while maintaining the advantages of the variable-period carrier generation of Lee.
In regard to Claim 16:
Lee does not disclose wherein the quantizer input signal and the quantizer output signal are digital and the quantizer is implemented digitally.
However, Park discloses wherein the quantizer input signal and the quantizer output signal are digital and the quantizer is implemented digitally (digital signal processing of quantized digit values throughout the noise shaper, ¶¶[0018]–[0019], ¶[0021]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee to implement the quantizer digitally as taught by Park, such that the quantizer input signal and the quantizer output signal are represented as digital values, in order to provide a fully digital implementation that improves processing flexibility, programmability, and integration while achieving the predictable benefits of digital signal processing.
In regard to Claim 20:
Lee does not disclose noise shaping circuitry comprising a modulator configured to receive the input signal and a quantizer output signal as inputs and apply filtering thereto to produce a quantizer input signal, and a quantizer producing the noise shaping output by requantization scaling.
However, Park discloses noise shaping circuitry comprising a modulator configured to receive the input signal and a quantizer output signal as inputs and apply filtering thereto to produce a quantizer input signal (the requantizer input formed from the noise shaper input signal and the error derived by comparing the requantizer input and output, fed back through HNS(z), constituting a two-input error-feedback filtering arrangement, ¶¶[0020]–[0021], Fig. 1), and a quantizer producing the noise shaping output by requantization scaling (requantizer 10, ¶[0019]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee to include the noise shaping circuitry taught by Park, wherein the modulator receives the input signal and the quantizer output signal and applies filtering to produce a quantizer input signal, and the quantizer produces the noise shaping output by requantization scaling, in order to reduce quantization noise while maintaining the advantages of the variable-period carrier generation of Lee.
In regard to Claim 21:
Lee discloses updating the period-control value once per carrier cycle in response to one polarity transition of the carrier (the first switch signal SW1, asserted when the storage voltage falls below the low reference voltage VREFL at the start of the charging phase, enables counter module 30258 such that the control signals are adjusted according to the first switch signal SW1, ¶[0031]).
However, Lee does not disclose wherein the noise shaping circuitry is activated to produce the new noise shaping output when the updated polarity signal is positive.
Park discloses noise shaping circuitry configured to generate a new noise shaping output by processing the input signal and the fed-back error signal (¶¶[0020]–[0021], Fig. 1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park such that the noise shaping circuitry is activated to produce a new noise shaping output when the updated polarity signal is positive, in order to synchronize the noise shaping operation with the carrier update while reducing quantization noise.In regard to Claim 22:
Lee discloses updating the period control value once per carrier cycle in response to one polarity transition of the carrier (the first switch signal SW1, asserted when the storage voltage falls below the low reference voltage VREFL at the start of the charging phase, enables counter module 30258 such that the control signals are adjusted according to the first switch signal SW1, ¶[0031]).
However, Lee does not disclose wherein the noise shaping circuitry is activated to produce the new noise shaping output only when the updated polarity signal is negative.
Park discloses noise shaping circuitry configured to generate a new noise shaping output by processing the input signal and the feedback error signal (¶¶[0020]-[0021], Fig. 1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park such that the noise shaping circuitry is activated to produce a new noise shaping output only when the updated polarity signal is negative, because Lee’s carrier operates with alternating positive and negative polarity phases, and selecting either polarity transition to initiate the once-per-cycle noise shaping update represents a selection from a finite number of identified, predictable alternatives while maintaining one update per carrier period.
In regard to Claim 28:
Lee further discloses wherein the fundamental period of the carrier wave is dependent upon a clock used to clock the carrier generation circuitry (counter module 30258 counts the switch signal and generates first control signals FCS1-FCS3 and second control signals SCS1-SCS3 that control the variable current source modules used to charge and discharge energy storage module 404, thereby determining the period of the triangular carrier wave VFT, ¶¶[0029]-[0031], [0038], Figs. 4-6).
Therefore, Lee in view of Park renders claim 28 obvious for the reasons discussed above with respect to claim 1, with Lee further disclosing that the fundamental period of the carrier wave is dependent upon the clock used to clock the carrier generation circuitry.
In regard to Claim 29:
Lee further discloses wherein the programmable current source circuit comprises a first current source selectively coupled to the integration input to source current thereto (first fixed current source 302420 supplies fixed current IF through first variable current source module 30242, which is selectively coupled to the integration input by first switch 30244); and a first plurality of switches, each associated with a different one of the plurality of current sources, with activation of a given current source being performed by closing its corresponding switch (first fine-tune switches 3024224, 3024244, and 3024264 respectively control first fine-tune current sources 3024222, 3024242, and 3024262, ¶¶[0032]–[0034], Figs. 4–5).
Lee further discloses wherein the programmable current sink circuit comprises a second current sink selectively coupled to the integration input to sink current therefrom (second fixed current source 302480 supplies fixed current IS through second variable current source module 30248, which is selectively coupled to the integration input by second switch 30246); and a second plurality of switches, each associated with a different one of the plurality of current sinks, with activation of a given current sink being performed by closing its corresponding switch (second fine-tune switches 3024822, 3024842, and 3024862 respectively control second fine-tune current sources 3024824, 3024844, and 3024864, ¶¶[0035]–[0037], Figs. 4 and 6).
Therefore, Lee in view of Park renders claim 29 obvious for the reasons discussed above with respect to claim 4, with Lee further disclosing the fixed current source and current sink and the respective pluralities of switches recited in claim 29.
5. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) and Park (KR 2013/0088679), as applied to claims 1–8, 12, 14–17, 20–22, 28, and 29 above, and further in view of Klaren et al. (US 2018/0083578).
In regard to Claim 9:
Lee in view of Park teaches the class-D amplifier as discussed above, including a programmable current source circuit comprising a plurality of current sources with a plurality of switches each associated with a different one of the current sources, a complementary programmable current sink circuit, and a switch circuit connecting the source side or the sink side to the integration input dependent upon the polarity signal (Lee, Figs. 4–6, ¶[0026]–[0028], ¶[0030]–[0031], ¶[0033], ¶[0036]).
Neither Lee nor Park discloses the programmable current source and sink circuits implemented with first and second cascode current mirrors having pluralities of cascode transistor circuits in a mirror arrangement.
Klaren discloses a current source implemented as a cascode current mirror arrangement wherein a reference current is sunk from the input of the mirror (current source I_mirror applied to the drain of FET Mb2 and the gate of FET Mb1 of the cascode reference circuit 204, thereby connecting Mb1 in a diode configuration such that the full value of the current is delivered through the stack of FETs in the cascode reference circuit, ¶[0062]–[0063], Fig. 3) and mirrored to its output (the current in the cascode reference circuit 204 being mirrored into the cascode amplifier 202 as I_final = m × I_mirror, where m is the device scaling factor, ¶[0063]); a plurality of cascode transistor circuits in a mirror arrangement with the cascode current mirror (cascode reference circuit 204 comprising a stack of serially-connected FETs Mb1–Mbn whose gates are coupled to the corresponding gates of the stacked FETs M1–Mn, the devices being scaled-down replicas such that the FET device stacking replicates the bias voltages and results in a more accurate current mirror, ¶[0042]); and that one or more of the current sources in the cascode reference circuit may be programmable or settable current sources, such as current digital-to-analog converters, with selectable current output levels allowing programmatic setting of levels (¶[0082], ¶[0086]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement the plurality of switched current sources and current sinks of Lee in view of Park using the cascode current mirror arrangement taught by Klaren, with each selectively-switched current source and current sink constituted as a cascode transistor circuit in mirror arrangement with a corresponding cascode current mirror, in order to compensate for the poor output resistance characteristics of short-channel devices and to improve the accuracy of the current mirroring, as expressly taught by Klaren (¶[0034], ¶[0042], ¶[0048]), thereby obtaining a predictable improvement in the precision of the magnitude-controlled currents that set the carrier period.
In regard to Claim 10:
Lee and Park do not disclose a voltage regulator arrangement configured to generate the reference current and sink the reference current from the input of the cascode current mirror.
However, Klaren discloses a voltage regulator arrangement configured to generate the reference current and sink the reference current from the input of the cascode current mirror (a reference current source implemented with a bandgap voltage reference across a resistor, the bandgap voltage reference producing a substantially constant voltage regardless of power supply variations, temperature changes, and circuit loading, ¶[0057]; see also first resistor R1 coupled to VDD and reference current source Iref, with the control loop regulating the current through the cascode reference stack such that Imirror/Iref = R1/R2, ¶¶[0068]–[0069], Fig. 5).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park and further in view of Klaren to include the voltage regulator arrangement taught by Klaren, in order to provide a stable reference current for the cascode current mirror, thereby improving current mirror accuracy and stability.
6. Claim 11 is rejected upder 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143), Park (KR 2013/0088679), and Klaren et al. (US 2018/0083578), as applied to claims 9 and 10 above, and further in view of Botker et al. (US 2005/0275452).
In regard to Claim 11:
Lee, Park, and Klaren do not disclose a diode coupled transistor selectively couplable to the first cascode current mirror to adjust an average current in the first cascode current mirror.
However, Botker discloses a cascode current mirror comprising a diode coupled transistor selectively couplable to the mirror (in a first chopping phase, FET MP1 is diode-connected via transistor MP3 and accepts the input current while the output current comes from MP2; in the second chopping phase, MP2 is diode-connected via transistor MP3 and MP1 becomes the output device, the diode coupling being selectively established by the switching network, ¶[0032], Fig. 3) to adjust an average current in the mirror (the alternating diode connection reduces transistor mismatch error in the average output current of the mirror, ¶¶[0006]–[0007], ¶[0009]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park and Klaren by incorporating the diode-coupled transistor arrangement taught by Botker, in order to reduce transistor mismatch errors and improve the accuracy of the average mirrored current.
7. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679), as applied to claim 12 above, and further in view of Adams et al. (WO 2004/105251 A1).
In regard to Claim 13:
Lee and Park do not disclose wherein the magnitude generation circuitry comprises a look-up circuit that looks up a value to use as the updated magnitude signal based upon the new top count value.
However, Adams discloses a look-up circuit that looks up a value to use as an updated magnitude signal based upon an input value (a non-linear mapping module that receives a signal associated with the input signal and tabulates the necessary hysteresis control information, Summary of the Invention, p. 4, ll. 11–22; lookup table 38 holding optimum values of the hysteresis factor H for each input range, Fig. 5 and Figs. 6–7, p. 11, ll. 12–18; a digital input addressing lookup table 42, Fig. 8, p. 11, ll. 19–24).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the magnitude generation circuitry of Lee in view of Park to include the look-up circuit taught by Adams, such that the updated magnitude signal corresponding to each new top count value is retrieved from stored values, in order to provide an optimized, programmable mapping of the period-control values using simple and efficient look-up hardware while achieving predictable control of the carrier switching period.
8. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679), as applied to claim 15 above, and further in view of Ribner et al. (US 5,283,578).
In regard to Claim 18:
Lee and Park do not disclose wherein the finite impulse response filter is configured with binomial coefficients derived from Pascal’s triangle interleaved with inserted zero-value coefficients.
However, Ribner discloses noise shaping employing transfer functions of the form (1+z^{-2})^N (output Equations (9) and (10) for the bandpass modulators, Ribner, col. 7, ll. 31–41), wherein the transfer function expands into binomial coefficients interleaved with zero-value coefficients, thereby providing band-reject noise shaping centered at one-fourth of the sampling frequency (Ribner, col. 7, ll. 31–41; col. 8, ll. 1–15).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the noise shaping circuitry of Lee in view of Park to include the finite impulse response filter taught by Ribner, in order to provide band-reject noise shaping and relocate the spectral null of the quantization noise to a selected non-zero frequency, thereby achieving predictable noise shaping performance.
9. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679), as applied to claim15 above, and further in view of Lesso (US 11,233,487 B2).
In regard to Claim 19:
Lee and Park do not disclose a dither generator configured to generate a dither signal having a range defined by the scaling factor, wherein the dither signal is injected into the quantizer input signal prior to quantization thereof by the quantizer.
However, Lesso discloses a dither generator configured to generate a dither signal (dither generator 401 of correlation controller 302 configured to generate dither signal Dt, which may comprise a linear feedback shift register or a Mersenne Twister, Fig. 4, p. 15, ll. 11–20), wherein the dither signal is injected into the quantizer input signal prior to quantization thereof by the quantizer (the dither signal Dt being added by adders 402p and 402n before being input to quantizers 202p and 202n, Fig. 4, p. 15, ll. 21–27).
Lesso does not expressly disclose that the range of the dither signal is defined by the scaling factor. However, Park discloses the scaling factor defining the requantization relationship (Park, ¶[0019]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park to include the dither generator taught by Lesso and to define the range of the dither signal based upon the scaling factor taught by Park, because the scaling factor determines the requantization interval and using that factor to set the dither range predictably matches the dither amplitude to the quantizer resolution, thereby reducing unwanted tones and quantization noise without excessive perturbation of the quantizer input signal.
10. Claims 23, 24, 26, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679), as applied to claim 1 above, and further in view of Haboosh et al. (US 6,809,586 B2).
In regard to Claim 23:
Lee and Park do not disclose wherein the integration circuitry is implemented digitally.
However, Haboosh discloses carrier generation circuitry implemented digitally (digital carrier signal generator 112 configured to generate digital samples of a sawtooth carrier signal, wherein the generator may comprise a memory storing the digital samples of the carrier, or a digital processor generating the digital samples from stored parameters such as slope and duration data, ¶[0015]; the modulation waveforms, including sawtooth and triangular waveforms, being digitally computed and digitally compared with the input signal samples to produce the pulse width modulation signal, ¶[0029]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park to implement the integration circuitry digitally as taught by Haboosh, in order to provide a programmable digital implementation that improves precision, repeatability, and implementation flexibility while producing predictable digital carrier generation.
In regard to Claim 24:
Lee and Park do not disclose wherein the integration circuitry is implemented digitally to produce the modulated carrier wave as a sawtooth waveform or a triangular waveform.
However, Haboosh discloses carrier generation circuitry implemented digitally to produce the carrier wave as a sawtooth waveform or a triangular waveform (digital carrier signal generator 112 generating digital samples of a sawtooth carrier signal, ¶[0015]; the digitally computed modulation waveforms including sawtooth, triangular, and the like, digitally compared with the input signal samples to produce the pulse width modulated signal, ¶[0029]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park to implement the integration circuitry digitally as taught by Haboosh, such that the modulated carrier wave is generated as a sawtooth waveform or a triangular waveform, in order to provide a programmable digital carrier generation circuit with predictable waveform generation and improved implementation flexibility.
In regard to Claim 26:
Lee and Park do not disclose wherein the digital integration circuitry generates a sawtooth waveform by positively integrating to a maximum value and subsequently resetting to a minimum value.
Haboosh discloses digital generation of sawtooth carrier samples, including generation from stored slope and duration parameters (¶[0015]), and further discloses digitally generated modulation waveforms including sawtooth waveforms (¶[0029], but does not expressly disclose generating the sawtooth waveform by positively integrating to a maximum value and subsequently resetting to a minimum value.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park and Haboosh to generate the sawtooth waveform by positively integrating to a maximum value and subsequently resetting to a minimum value, as a predictable implementation of the digitally generated sawtooth waveform taught by Haboosh.
In regard to Claim 27:
Lee and Park do not disclose wherein the digital integration circuitry generates a sawtooth waveform by negatively integrating to a minimum value and subsequently resetting to a maximum value.
Haboosh discloses digital generation of sawtooth carrier samples, including generation from stored slope and duration parameters (¶[0015], and further discloses digitally generated modulation waveforms including sawtooth waveforms (¶[0029]), but does not expressly disclose generating the sawtooth waveform by negatively integrating to a minimum value and subsequently resetting to a maximum value.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park and Haboosh to generate the sawtooth waveform by negatively integrating to a minimum value and subsequently resetting to a maximum value, since selecting between positive-slope and negative-slope sawtooth waveforms is a choice from a finite number of identified, predictable solutions with a reasonable expectation of success.
11. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2013/0335143) in view of Park (KR 2013/0088679) and Haboosh et al. (US 6,809,586 B2), as applied to claim 24 above, and further in view of Hanei et al. (US 4,772,996).
In regard to Claim 25:
Lee, Park, and Haboosh do not disclose that the digital integration circuitry comprises an edge detector, a multiplexer arrangement selecting between reset values and an accumulated value, and a digital summer with delayed feedback producing the triangular waveform.
However, Hanei discloses a digital triangular carrier generation circuit comprising a digital accumulation arrangement generating the carrier (up-down counter 25 acting as a carrier wave data generating part and counting clock pulses CLK generated from clock pulse generator 24 to generate carrier wave data DC, Fig. 5, col. 13, ll. 16–25); detection circuitry detecting when the carrier reaches its peak excursions (maximum value discrimination circuit 26 and minimum value discrimination circuit 27 generating carry and borrow signals through OR circuit 28, Figs. 5–6, col. 13, ll. 31–42); selection circuitry reversing the accumulation direction in response to the detected extremes (flip-flop 29 changed over by the carry or borrow signal to control the counting direction of up-down counter 25, col. 13, ll. 42–50); and a digital comparator producing the PWM signal (comparator 31 comparing carrier wave data DC with modulation data DMU to produce PWM signal SU, Fig. 5, col. 13, ll. 25–30).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the class-D amplifier of Lee in view of Park and Haboosh by implementing the digital integration circuitry using the digital triangular carrier generation circuit taught by Hanei, in order to provide a digital implementation capable of generating a triangular carrier waveform with predictable timing and operation.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIAM SADMAN whose telephone number is (571)270-0921. The examiner can normally be reached on M-TH 8-5.
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/S.S/
Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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