DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior arts cited in this office action:
Ichiyama et al. (DE 102009007480 A1, hereinafter “Ichiyama”)
Sasaki (US 20050038616 A1, hereinafter “Sasaki”)
Xu et al. (CN 116186573 A, hereinafter “Xu”)
Schuttert et al. (WO 2007010452 A2, hereinafter “schuttert”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ichiyama et al. (DE 102009007480 A1, hereinafter “Ichiyama”) in view of Sasaki (US 20050038616 A1, hereinafter “Sasaki”) and in view of Xu et al. (CN 116186573 A, hereinafter “Xu”).
Regarding claim 1:
Ichiyama teaches a system for introducing jitter to input signals, comprising:
a first delay circuit having a plurality of first element stages, the first delay circuit
configured to receive an input signal and introduce jitter to the input signal thereby providing a
jittered output signal, each of the first element stages defining a plurality of logical elements (Ichiyama [0035], [0054]-[0057], figs. 1, 3, 7, 9 and 13, where Ichiyama teaches a first delay circuit comprising a plurality of delay elements),
wherein the first delay circuit is configured to transmit at least a first version of the input signal and a second version of the input signal through the first element stages such that the first
version travels through first a path of the first delay circuit and the second version travels
through a second path of the first delay circuit (Ichiyama [0035], [0054]-[0059] figs. 1, 3, 7, 9 and 13, where two of the delay can be combined to form the first delay circuit);
a controller configured to apply a random number to the plurality of first element stages,
(Ichiyama [0035], [0054]-[0059], figs. 1, 3, 7, 9 and 13, where Ichiyama teaches a control circuit 40 designed to control which output of the version of the input signal to process and output); and
a first combiner configured to receive the first version of the input signal and the second
version of the input signal from the first delay circuit and to combine the first version and the
second version thereby forming the first jittered output signal, wherein process variations in the
plurality of first element stages cause random deviations in delays introduced by the first element
stages of the first delay circuit (Ichiyama [0035], [0054]-[0059], figs. 1, 3, 7, 9 and 13, where Ichiyama teaches a combiner that combine the first version of the input signal and the second version of the input signal).
Ichiyama fails to teaches wherein each of the first element stages is configured to receive a respective portion of the random number and control which logical element of the respective first element stage processes the first version of the input signal and which logical element of the respective first element stage processes the second version of the input signal based on the portion of the random number received by the respective first element stage
However, Sasaki in the same line of endeavor teaches a jitter adding circuit wherein A code generator 203 shown in FIG. 5 generates the control code indicating a numerical value within a predetermined range and the select code indicating one of the aforesaid three jitter adding circuits 201 according to the later-described procedure, and inputs the control code and the select code to the distributing circuit 202 via an input terminal for control information provided in the interconnect LSI. A noise measuring equipment 204 shown in FIG. 5 measures the magnitude of a noise component mixed in a data signal outputted from the Tx block 410 or a data signal outputted from the Rx block 420, and outputs the measurement result in association with the control code and the select code received from the code generator 203 (Sasaki [0102]-[0105], fig. 5, wherein the code is random to generate the noise or Gaussian to compare the noise receive).
Furthermore, Xu teaches the basic concept of each jitter is described in detail below.
2.1, Deterministic jitter (DJ): is caused by the identifiable interference signal, such jitter is generally limited, with specific (and non-random) generating reason. Relative to random jitter, deterministic jitter can be repeated and predicted time jitter, so the peak value of the DJ is bounded, and the position of the boundary along with the increase of the measurement times can approach the real value.
2. Random jitter (RJ): It refers to the time sequence change caused by the factor which is difficult to predict. For example, it can affect the semiconductor crystal material mobility of temperature factors, may cause random change of the carrier. In addition, the change of the semiconductor processing technique, such as doping density is not uniform, also may cause jitter.
The random jitter is time noise, and there is no known mode. Although in the theory of random process, random jitter may have a variety of probability distribution, but the jitter model is generally assumed that random jitter is Gaussian normal distribution. There are two reasons: first, in many circuits, the main source of the random noise is thermal noise, which has a Gaussian distribution; secondly, according to the central limit law, many independent non-correlation noise sources close to a Gaussian distribution after overlapping. Due to the random jitter satisfy the Gaussian distribution, so the peak is non-bounded, which is the important feature of random jitter different from deterministic jitter (Xu [0002], [0044]-[0047]).
Therefore, taking the teachings of Ichiyama, Sasaki and Xu as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use a random number generator to generate appropriate codes in order to select appropriate path to control the amount of jitter introduced and determine the jitter tolerance of the system and provide mitigation when necessary.
Regarding claim 2:
Ichiyama in view of Sasaki and in view of Xu teaches further comprising:
a second delay circuit having a plurality of second element stages, the second delay
circuit configured to receive the jittered output signal and introduce additional jitter to the jittered
output signal thereby providing a second jittered output signal, each of the second element stages
defining a plurality of logical elements, wherein the second delay circuit is configured to
transmit at least a first version of the jittered output signal and a second version of the jittered
output signal through the second element stages such that the first version travels through a first path of the second delay circuit and the second version travels through a second path of the
second delay circuit;
wherein the controller is configured to apply a second random number to the plurality of
second element stages of the second delay circuit;
wherein each of the second element stages of the second delay circuit is configured to
receive a respective portion of the second random number and control which logical element of
the respective second element stage processes the first version of the jittered output signal and
which logical element of the respective second element stage processes the second version of the
jittered output signal based on the portion of the random number received by the respective
second element stage; and
a second combiner configured to receive the first version of the jittered output signal and
the second version of the jittered output signal from the second delay circuit and to combine the
first version of the jittered output signal and the second version of the jittered output signal
thereby forming the second jittered output signal, wherein process variations in the plurality of
second element stages cause random deviations in delays introduced by the second element
stages of the second delay circuit (Ichiyama [0035], [0054]-[0059], figs. 1, 3, 7, 9 and 13; Sasaki [0102]-[0105], fig. 5, where more than 1 jitter adding circuit is used and are controlled by the code generator and distributing circuit. Also duplicating the same circuit many times is customary in the art and requires no undue burden).
Regarding claim 3:
Ichiyama in view of Sasaki and in view of Xu teaches further comprising one or more additional delay circuits each configured to provide an additional jittered output signal (Ichiyama [0035], [0054]-[0059], figs. 1, 3, 7, 9 and 13; Sasaki [0102]-[0105], fig. 5).
Regarding claim 4:
Ichiyama in view of Sasaki and in view of Xu teaches wherein each jittered output signal follows a Gaussian distribution Xu [0002], [0044]-[0047]).
Regarding claim 5:
wherein each of the delay circuit, the controller, and the combiner is implemented on a field programmable gate-array (Xu [0213].
Regarding claim 6:
Ichiyama in view of Sasaki and in view of Xu teaches wherein the first jittered output signal comprises a jittered rising edge and a jittered falling edge (Sasaki [0067], [0081]; Xu [0002], [0015]-[0016], [0022]-[0023]).
Regarding claim 7:
Ichiyama in view of Sasaki and in view of Xu teaches wherein:
the jittered rising edge is selected from a first rising edge associated with the first version
of the input signal and a second rising edge associated with the second version of the input
signal;
the jittered falling edge is selected from a first falling edge associated with the first
version of the input signal and a second falling edge associated with the second version of the
input signal; and
wherein the jittered rising edge and the jittered falling edge are associated with distinct versions of the input signal (Sasaki [0067], [0081]; Xu [0002], [0015]-[0016], [0022]-[0023], this is fall under the obviousness to try since invention is taught by the cited prior arts. One of ordinary skill in the art can perform the selection in anyway desired).
Regarding claim 8:
Ichiyama in view of Sasaki and in view of Xu teaches wherein the controller is configured to apply a third random number to the first combiner (Ichiyama fig. 13; (Sasaki [0102]-[0105], fig. 5, where Ichiyama includes switches for the combiner which can also be control using random number generator as taught by Sasaki and Xu).
Regarding claim 9:
Ichiyama in view of Sasaki and in view of Xu teaches wherein the first combiner combines the first version of the input signal and the second version of the input signal based on the third random number (Ichiyama fig. 13; (Sasaki [0102]-[0105], figs. 5, and 9, where Ichiyama includes switches for the combiner which can also be control using random number generator as taught by Sasaki and Xu).
.
Regarding claim 18:
Ichiyama in view of Sasaki and in view of Xu teaches A system for introducing jitter to input signals, comprising:
a first delay circuit having a plurality of first element stages, the first delay circuit
configured to receive an input signal and introduce jitter to the input signal thereby providing a
jittered output signal, each of the first element stages defining a plurality of logical elements,
wherein the first delay circuit is configured to transmit at least a first version of the input signal
and a second version of the input signal through the first element stages such that the first
version travels through first a path of the first delay circuit and the second version travels
through a second path of the first delay circuit;
a second delay circuit having a plurality of second element stages, the second delay
circuit configured to receive the jittered output signal and introduce additional jitter to the jittered
output signal thereby providing a second jittered output signal, each of the second element stages
defining a plurality of logical elements, wherein the second delay circuit is configured to
transmit at least a first version of the jittered output signal and a second version of the jittered
output signal through the second element stages such that the first version of the jittered output
signal travels through first a path of the second delay circuit and the second version of the
jittered output signal travels through a second path of the second delay circuit;
a controller configured to:
apply a first random number to the plurality of first element stages of the first
delay circuit, wherein each element stage of the first element stages is configured to
receive a respective portion of the first random number and control which logical element
of the respective first element stage processes the first version of the input signal and
which logical element of the respective first element stage processes the second version
of the input signal based on the portion of the first random number received by the
respective first element stage; and
apply a second random number to the plurality of second element stages of the
second delay circuit, wherein each element stage of the second element stages is
configured to receive a respective portion of the second random number and control
which logical element of the respective second element stage processes the first version
of the jittered output signal and which logical element of the respective second element
stage processes the second version of the jittered output signal based on the portion of the
second random number received by the respective second element stage;
a first combiner configured to receive the first version of the input signal and the second
version of the input signal from the first delay circuit and to combine the first version and the
second version thereby forming the jittered output signal;
a second combiner configured to receive the first version of the jittered output signal and
the second version of the jittered output signal from the second delay circuit and to combine the
first version and the second version thereby forming the second jittered output signal;
wherein process variations in the plurality of first stages cause random deviations in
delays introduced by the first element stages of the first delay circuit; and
wherein process variations in the plurality of the second stages cause random deviations
in delays introduced by the second element stages of the second delay circuit.
Claim 18 contains similar limitations as claims 1 and 2 and are rejected on the same grounds.
Regarding claim 19:
Ichiyama in view of Sasaki and in view of Xu teaches wherein the controller is configured to:
apply a third random number to the first combiner; and
apply a fourth random number to the second combiner (Ichiyama fig. 13; (Sasaki [0102]-[0105], figs. 5, and 9, where Ichiyama includes switches for the combiner which can also be control using random number generator as taught by Sasaki and Xu).
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ichiyama et al. (DE 102009007480 A1, hereinafter “Ichiyama”) in view of Sasaki (US 20050038616 A1, hereinafter “Sasaki”) and in view of Xu et al. (CN 116186573 A, hereinafter “Xu”) and in view of Schuttert et al. (WO 2007010452 A2, hereinafter “Schuttert”).
Regarding claim 10:
However, Ichiyama in view of Sasaki and in view of Xu teaches wherein the first combiner is configured to combine the first version of the input signal and the second version of the input signal using a function selected from an AND function and an OR function.
However, Schuttert teaches a system and method for controlling duty cycle wherein two paths comprising a plurality if delay elements are inputted in an AND gate and an OR gate and the output of the AND gate and the OR gate are inputted into a multiplexer wherein the multiplexer is able to chose between the output of the AND gate and the OR gate such the duty cycle is controlled accordingly (Schuttert page 8 line 23- page 9 line 28, claims 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use an AND gate as a first combiner for the first version of the input signal and an OR gate as a second combiner for the second version of the input signal and a switch/multiplexer (control by a random number) to select one of the gates outputs to obtain the signal output desired such that appropriate delay or jittered signal can be obtained.
Regarding claim 20:
Ichiyama in view of Sasaki, in view of Xu and in view of Schuttert teaches wherein:
the first combiner combines the first version of the input signal and the second version of
the input signal with a first function that is determined based on the third random number; and
the second combiner combines the first version of the jittered output signal and the
second version of the jittered output signal with a second function that is determined based on
the fourth random number (Schuttert page 8 line 23- page 9 line 28, claims 1 and 5).
Conclusion
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/WEDNEL CADEAU/Primary Examiner, Art Unit 2632 July 24, 2026
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