DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shimamoto (US 2021/0013847 A1) in view of Liu et al. (US 2023/0216457 A1).
Regarding claim 1: Shimamoto, fig. 1, fig. 2, discloses a limiter circuit comprising (clamp circuit 300), which suppresses the amplitude of RF1 and therefore performs as a limiter circuit, (paragraph [0088] lines 1-2): one or more first diodes (fig. 2. (301)) connected in series, each first diode (3012) having an anode electrically connected to a signal line (203) through which a high-frequency signal (RF1) passes, and a cathode electrically connected to a node (303/304); a transistor (302) having a source-drain path or an emitter-collector path electrically connected between a reference potential (304) and the node and a gate or a base (3021) to which a control voltage or a control current (Va) is input.
However, Shimamoto does not disclose a first constant current source configured to output a first constant current to the node.
Liu discloses a bias circuit configured to provide a bias voltage. The bias circuit includes current source (IREF 524) electrically connected between VBATT and the base of transistor (526) as part of the disclosed bias network (paragraph [0074], lines 4-9). A person of ordinary skill in the art would have understood that current source IREF524 serves as the reference current source for the disclosed bias circuit.
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Shimamoto’s limiter circuit to include Liu’s disclosed current-source bias circuit in order to provide a stable reference current for the bias network, to provide a stable bias current for the transistor while maintaining reliable operation of the limiter circuit.
Regarding claim 2: Shimamoto discloses one or more second diodes (301) connected in series, each second diode having an anode electrically connected to the node (303/304), and a cathode electrically connected to the signal line (203) (paragraph [0046], lines 1-2); [0048], lines 6-8; [0054].l lines 1-2).
Regarding claim 3: Shimamoto does not disclose a control circuit configured to output
the control voltage or the control current to the transistor (526), and to output
a first control signal for adjusting the first constant current to the first constant current source.
Liu does disclose a control circuit (bias circuit 504) configured to output the control voltage or the control current to the transistor (526), and to output a first control signal for adjusting the first constant current to the first constant current source (IREF 524).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Shimamoto’s limiter circuit using Liu’s bias control circuit in order to provide adaptive control of the amplifier bias/current, thereby improving amplifier operation under varying operating conditions, including robustness while maintaining amplifier performance.
Regarding claim 4: Shimamoto does not disclose a control circuit configured to output the control voltage or the control current to the transistor, and to output a first control signal for adjusting the first constant current to the first constant current source.
Liu does disclose a control circuit (bias circuit 504) configured to output the control voltage or the control current to the transistor (526), and to output a first control signal for adjusting the first constant current to the first constant current source (IREF 524).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Shimamoto’s limiter circuit, including the diode arrangement of claim 2, to incorporate Liu’s adaptive control circuitry in order to improve amplifier robustness and operating performance through adaptive bias/current control.
Regarding claim 6: Shimamoto, Fig. 1 and Fig. 2, discloses A matching network comprising (matching circuit 402): The limiter circuit (clamp circuit 300), wherein the matching network (402) is configured to match an output impedance of a first circuit (first amplifier 201) and an input impedance of a second circuit (second amplifier 202), wherein the first circuit (first amplifier 201) is configured to amplify a high-frequency signal (RF1), and wherein the second circuit (second amplifier 202) is configured to amplify the high-frequency signal (RF1) amplified by the first circuit (first amplifier 201).
Claim 7: Shimamoto, Fig. 1 and Fig. 2, discloses power amplifier circuit comprising: a first circuit (first amplifier 201) configured to amplify a high-frequency signal (RF1); a second circuit (second amplifier 202) configured to amplify the high-frequency signal (RF1) amplified by the first circuit (first amplifier 201); and a matching network (matching circuit 402) configured to match an output impedance of the first circuit and an input impedance of the second circuit, wherein the matching network comprises the limiter circuit (clamp circuit 300)
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, none of the references teaches a second constant current source configured to output a second constant current to the node, wherein the control circuit is further configured to output a second control signal for adjusting the second constant current to the second constant current source.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art of record, including:
Araki (US 5384549 A) discloses an amplifier including a current-limiting protection circuit.
Zhu (WO 2022226935 A1) discloses an RF amplifier including a clipping (limiting) circuit associated with the amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
NATASHA Y. MARANO
Examiner
Art Unit 2843
Prosecution Insights