DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 19-23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Fumitake et al. (US 20150171085) in view of Youn et al. (US 20140227857).
Regarding claim 19, Fumitake (see annotated fig. 14; ¶¶0029, 0068-0072) teaches a semiconductor device, comprising:
a substrate 100;
a first active pattern 1 extending in a first direction on the substrate;
a second active pattern 2 extending in the first direction on the substrate and being spaced apart from the first active pattern in a second direction intersecting the first direction;
a third active pattern 3 extending in the first direction on the substrate and being spaced apart from the second active pattern in the second direction;
a fourth active pattern 4 extending in the first direction on the substrate and being spaced apart from the third active pattern in the second direction;
a first device isolation layer between the second active pattern and the third active pattern;
a second device isolation layer between the first active pattern and the second active pattern;
a third device isolation layer between the third active pattern and the fourth active pattern;
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a gate electrode 212 on the first active pattern, the second active pattern, the third active pattern and the fourth active pattern, the gate electrode extending in the second direction;
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a first source/drain pattern 312 on the first active pattern and the second active pattern; and
a second source/drain pattern 311 on the third active pattern and the fourth active pattern.
Fumitake teaches that first and second source/drain patterns are adjacent to a side of the gate electrode, a lowermost point of the first source/drain pattern 312 is at a first level, a lowermost point of the second source/drain pattern 311 is at a second level. The first level is higher than the second level and the lowermost point of the first source/drain pattern 312 and the lowermost point of the second source/drain pattern 311 is paced apart from an upper surface of the substrate 100. Although Fumitake depicts that the three isolation layers have the same thickness, it is suggested that the first isolation could be larger than depicted to prevent leakage or punch-through phenomenon from occurring between the source and drain of a N-type FinFET and a P-type FinFET (¶0073). Nonetheless, it is not disclosed that the thickness of the first isolation is greater than the thickness of the second and third isolation regions.
However, Youn (see annotated. fig. 2P) discloses a semiconductor device including FinFET regions 102 separated by an isolation region 105R which include a thickness that is larger than the thickness of the other isolation layers 104 (¶0051).
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It would have been obvious to one of ordinary skill in the art at the time of the invention was made to make the first isolation layer disclosed by Fumitake having a thickness greater than the thickness of the second and third isolation layers suggested by Youn to prevent leakage or punch-through phenomenon from occurring between the source and drain of a N-type FinFET and a P-type FinFET.
Regarding claim 20, Fumitake teaches that a pitch between the first active pattern and the second active pattern is substantially the same as a pitch between the third active pattern and the fourth active pattern.
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Regarding claim 21, Fumitake teaches a first bottom surface of the gate electrode 212 that is between the first active pattern and the second active pattern and a second bottom surface of the gate electrode that is between the third active pattern and the fourth active pattern are located at substantially the same vertical level as each other.
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Regarding claim 22, Fumitake in view of Youn teaches that the thickness of the second device isolation layer is substantially the same with the thickness of the third device isolation layer (see fig. 14; 2P above).
Regarding claim 23, Youn teaches that a width of the first device isolation layer is greater than a width of the second device isolation layer, and wherein the width of the first device isolation layer is greater than a width of the third device isolation layer (e.g. fig. 2P, above).
Regarding claim 26, Fumitake teaches the first source/drain pattern has a different shape from the second source/drain pattern (e.g. triangular vs rhombic).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Fumitake et al. (US 20150171085) in view of Youn et al. (US 20140227857) and further in view of Lee (US 20090315112).
Regarding claim 24, Fumitake (e.g. fig. 14) does not teach that each of the adjacent epitaxial source /drain layers (312/312; 311/311) are merged. However, Lee (e.g. fig. 7C) teaches a FinFET transistor including consecutive source/drain regions 50 merged to each other and including an air gap 52 (¶ 0026).
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to overgrow the semiconductor regions 312/311, and to include an air gap between the merged epitaxial source/drain layer of the instant combination as suggested by Lee because merging adjacent the source/drain layers reduce the tensile stress of the gate channel. This tensile stress is generated by semiconductor layers formed on top of the fins. Also, this structure allows forming an air gap that will reduce the parasitic capacitance between adjacent fins.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Fumitake et al. (US 20150171085) in view of Youn et al. (US 20140227857) and further in view of Wen et al. (US 9,275,905).
Regarding claim 25, Fumitake in view of Youn does not teach the claimed limitations of: an etch stop layer covering the first and second source/drain regions and the device isolation layer. Fumitake suggests that the process of making their invention contemplates the use of a dummy gate but does not disclose the use of an etch stop layer covering the source/drain regions (¶ 0089). Nevertheless, Wen teaches a method of making a FinFET transistor including an etch stop layer 211 covering the first and second source/drain regions 207/209 and the device isolation layer (col. 7/ll. 45-50). According to Wen, the use of an etch stop layer over the source/drain area will allow the use of a dummy gate structure during the initial processing steps. This dummy gate is eventually replaced by a final gate structure.
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to have used an etch stop layer over the source and drain regions disclosed by Fumitake in view of Youn to protect the source and drain regions during the removal of the dummy gate that is eventually replaced by a functional gate as suggested by Wen.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Fumitake et al. (US 20150171085) in view of Chang et al. (US 20150236131) and further in view of Youn et al. (US 20140227857).
Regarding claim 36, Fumitake (see annotated fig. 14; ¶¶0029, 0068-0072) teaches a semiconductor device comprising:
a substrate 100;
a first active pattern 1 extending in a first direction on the substrate;
a second active pattern 2 extending in the first direction on the substrate;
a third active pattern 3 extending in the first direction on the substrate;
a fourth active pattern 4 extending in the first direction on the substrate;
a first isolation on the substrate and between the first active pattern and the second active pattern;
a second isolation on the substrate and between the second active pattern and the third active pattern;
a third isolation on the substrate and between the third active pattern and the fourth active pattern;
a first gate electrode extending in a second direction intersecting the first direction on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first isolation, the second isolation and the third isolation;
a first epitaxial source/drain 312 on the first active pattern [¶0068];
a second epitaxial source/drain 312 on the second active pattern;
a third epitaxial source/drain 311 on the third active pattern [¶0048],
and a fourth epitaxial 311 source/drain on the fourth active pattern.
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Fumitake teaches that a lowermost portion of the first epitaxial source/drain 312 is higher than a lowermost portion of the third epitaxial source/drain 311, the lowermost portion of the first epitaxial source/drain 312 and the lowermost portion of the third epitaxial source/drain 311 are spaced apart from an upper surface of the substrate.
Fumitake does not teach that a width of the first isolation is less than a width of the second isolation, a width of the third isolation is less than a width of the second isolation. Also, Fumitake does not show that the first to fourth epitaxial source/drain layers are located between a first gate and a second gate.
Moreover, it is known in the art that a FinFET semiconductor device comprises a plurality of FinFET units having several gates parallel to each other and crossing a plurality of fins in a perpendicular angle to form a grid. However, Fumitake only shows a single unit comprising one gate over a plurality of fins (see fig. 6). Therefore, Fumitake does not show that the first to fourth epitaxial source/drain layers are located between a first gate and a second gate.
However, Chang (see fig. 2) discloses a conventional FinFET layout showing a plurality of gates 110 formed over a plurality of fins 104. The top surface of the fins 104 located between the gates are recognized as the source/drain areas and the space between the fins 104 are recognized as the isolation regions 108 (see fig. 1; ¶¶ 0020; 0016).
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It would have been obvious to one of ordinary skill in the art at the time of the invention to form a plurality gate electrodes, parallel to each other, over the fin structure disclosed by Fumitake and to form the first to fourth epitaxial source/drain regions between the gate electrodes as disclosed by Chang to achieve a complete circuit integration, and to provide an adequate bit density which is required to perform the functions of an electrical circuit.
Although Fumitake depicts that the three isolation layers have the same width, it is suggested that the second isolation could be larger than depicted to prevent leakage or punch-through phenomenon from occurring between the source and drain of a N-type FinFET and a P-type FinFET (¶0073). Nonetheless, it is not disclosed that the width of the second isolation is greater than the width of the first isolation, and the width of the third isolation.
However, Youn (see annotated. fig. 2P) discloses a semiconductor device including FinFET regions 102 separated by an isolation region 105R which include a width that is larger than the width of the other isolation layers 104 (¶0051).
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It would have been obvious to one of ordinary skill in the art at the time of the invention was made to make the second isolation layer disclosed by Fumitake in view of Chang having a width greater than the width of the first and second isolation layers as suggested by Youn to prevent leakage or punch-through phenomenon from occurring between the source and drain of a N-type FinFET and a P-type FinFET.
Claims 37 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Fumitake et al. (US 20150171085) in view of Chang et al. (US 20150236131) and further in view of Youn et al. (US 20140227857) further in view of Lee (US 20090315112).
Regarding claims 37 and 38, Fumitake (e.g. fig. 14) does not teach that each of adjacent epitaxial source /drain layers (312/312; 311/311) are merged. However, Lee (e.g. fig. 7C) teaches a FinFET transistor including consecutive source/drain regions 50 merged to each other and including an air gap 52 (¶ 0026).
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to overgrow the semiconductor regions 312/311, and to include an air gap between the merged epitaxial source/drain layer of the instant combination as suggested by Lee because merging adjacent the source/drain layers reduce the tensile stress of the gate channel. This tensile stress is generated by semiconductor layers formed on top of the fins. Also, this structure allows forming an air gap that will reduce the parasitic capacitance between adjacent fins.
Allowable Subject Matter
Claims 27-35 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 27, the prior art does not teach a device where a lowermost level of an upper surface of the second device isolation layer is higher than a lowermost level of an upper surface of the third device isolation layer, and a lowermost level of an upper surface of the first device isolation layer is lower than the lowermost level of the upper surface of the third device isolation as claimed.
Regarding independent claim 32, the prior art does not teach a semiconductor device where the first active pattern has a first width in the first direction at the first level, the second active pattern has a second width in the first direction at the second level, the second width is greater than the first width, the first air gap is separated from the etch stop layer, and a lowermost point of the first source/drain region and a lowermost point of the second source/drain region is spaced apart from an upper surface of the substrate as claimed.
Regarding dependent claims 28-31 and 33-35 they are allowed as being dependent of one of allowed independent claims 27 and 32
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEONARDO ANDUJAR whose telephone number is (571)272-1912. The examiner can normally be reached Monday to Thursday 10 AM to 8 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patricia L Engle can be reached on (571)272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEONARDO ANDUJAR/ Primary Examiner, Art Unit 3991
Conferees:
/LEE E SANDERSON/Reexamination Specialist, Art Unit 3991
/Patricia L Engle/SPRS, Art Unit 3991
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