DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US Patent Pub. # 2022/0245084).
As to claim 1, Kim (Fig. 3, 6, 7A, and 7B) discloses a camera system, comprising:
a plurality of camera image sensors (first image sensor 230 and second image sensor 240) each including a Mobile Industry Processor Interface (MIPI) Differential Physical Layer (D-PHY) interface (Para 45 and 54); and
a circuit (application processor (AP) 220) to process (process) image frames (frames) obtained from the plurality of camera image sensors (230 and 240) through a single MIPI D-PHY interface (single reception circuit 221) of the circuit (220), the circuit (220) to transmit one or more trigger signals (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) to the plurality of camera image sensors (230 and 240) to cause obtaining the image frames (frames) from the plurality of camera image sensors (230 and 240) one at a time based on the one or more trigger signals (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state), the image frames to be transmitted through a single MIPI D-PHY connection (221) between the single MIPI D-PHY interface (220) of the circuit and MIPI D-PHY interfaces of the plurality of camera image sensors (230 and 240) (Para 60, 67-74).
As to claim 2, Kim Figs. 7A and 7B) teaches wherein transmission of the one or more trigger signals (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) comprises the circuit (220) to transmit a single trigger signal (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) is to a first camera image sensor (430) of the plurality of camera image sensors (430 and 440) as a first trigger input to the first camera image sensor (430), and wherein the first camera image sensor (430) is to be triggered to transmit (transmits data to the processor) a first set of image frames (frame) from the first camera image sensor (430) towards the circuit (420) and to transmit a first trigger output to a second camera image sensor (440) of the plurality of camera image sensors (430 and 440) as a second trigger input (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) to the second camera image sensor (440), and wherein the second camera image sensor (440) is to be triggered to transmit (transmits data to the processor) a second set of image frames (frames) from the second camera image sensor (440) towards the circuit (420) and to transmit a second trigger output to a third camera image sensor (1100C) of the plurality of camera image sensors as a third trigger input (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) to the third camera image sensor (1100C) (Para 66, 70-74, and 131). Kim teaches the camera nodule group 1100 may be modified to include n (n is a natural number equal to or greater than four) number of camera modules. Further, at least one of the plurality of camera modules 1100a, 1100b, and 1100c included in the camera module group 1100 may include an image sensor described in the example embodiments with reference to FIGS. 1 to 17 (Para 131).
As to claim 3, Kim teaches wherein the first camera image sensor (430) is to be triggered to transmit the first trigger (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) output to the second camera image sensor of the plurality of camera image sensors (430 and 440) as the second trigger input to the second camera image sensor (430) after a previously configured delay (when the first transmission circuit 431 is in a first mode, the second transmission circuit 441 may have a high impedance state) (Para 70 and 71).
As to claim 4, Kim teaches wherein the previously configured delay (when the first transmission circuit 431 is in a first mode, the second transmission circuit 441 may have a high impedance state) is set based on data processing capability of the circuit (420) (Para 70 and 71).
As to claim 5, Kim teaches wherein the first camera image sensor’s MIPI D-PHY interface (431) is to enter a high impedance state (high impedance (Hi-impedance or Hi-Z) state)) after transmission of the first set of image frames (frame) from the first camera image sensor (430) towards the circuit (420) (Para 71 and 72).
As to claim 11, Kim teaches wherein the image frames (frames) transmitted (transmits data to the processor) from the plurality of camera image sensors (430 and 440) are transmitted through a same physical channel of the single MIPI D-PHY connection (reception circuit 421) (Para 67-74).
As to claim 12, Kim teaches wherein the circuit is a System on a chip (SoC) (system on a chip (SoC)) that comprises a chip dedicated to providing the single MIPI D-PHY connection (221 or 421) (Para 26).
As to claim 13, Kim teaches wherein transmission of the one or more trigger signals (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state) comprises the circuit to transmit a plurality of trigger signals (image sensor not transmitting data may need to be in a high impedance (Hi-impedance or Hi-Z) state), each to one of the plurality of camera image sensors (430 and 440) to cause obtaining the image frames (frames) from the plurality of camera image sensors (430 and 440) one at a time (Para 70 and 71).
As to claim 14, Kim teaches wherein a camera image sensor (430 and 440) of the plurality of camera image sensors (430 and 440) is to enter a high impedance state (high impedance (Hi-impedance or Hi-Z) state)) after transmission of a set of image frames from the camera image sensor (430 and 440) towards the circuit (420) (Para 70 and 71).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Patent Pub. # 2022/0245084) in view of Miyamoto (US Patent Pub. # 2023/0164123).
As to claim 6, note the discussion above in regards claim 1. Kim teaches wherein transmitting (transmits data to the processor) a first image frame (frame) from a first camera image sensor (430) towards the circuit (420) (Para 70 and 71). Kim does not teach transmitting virtual channel (VC) tag information of the first image frame to identify from which camera image sensor the first image frame is transmitted. Miyamoto (Fig. 3) teaches transmitting virtual channel (VC) tag information (VC (Virtual Channel)) of the first image frame to identify from which camera image sensor (image sensor 21) the first image frame (frame) is transmitted (Para 148). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a packet header stores a VC (Virtual Channel) as taught by Miyamoto to the electronic device of Kim, to use a nonce value specifically with more enhanced safety (Para 6 of Miyamoto).
As to claim 7, Miyamoto teachers wherein the virtual channel (VC) tag information (VC (Virtual Channel)) of the first image frame (frame) comprises a virtual channel (VC) identifier (ID) with a header (packet header stores a VC (Virtual Channel)) of the first image frame (Para 148).
As to claim 8, Miyamoto teachers wherein the circuit (application processor 1212) is to store the first image frame to a buffer (storage sections 1324) apart from one to store a second image frame transmitted from a second camera image sensor based on the virtual channel (VC) tag information (VC (Virtual Channel)) of the first image frame (Para 148 and 775).
As to claim 9, Miyamoto teachers wherein the image frames transmitted from the plurality of camera image sensors include packets that each comprise a data type field (data type), a virtual channel (VC) identifier (ID) field (VC (Virtual Channel)), a data field with a set of bits (data) (Para 148).
As to claim 10, Miyamoto teachers wherein at least a subset of the packets further comprises a data length field (WC (Word Count) representing the data length of a payload) to indicate length of the data field and an authenticity check field (packet footer stores a CRC (Cyclic Redundancy Check)) (Para 148 and 839). Miyamoto teachers a message authentication code, a digital signature, and the like may be stored in the extended packet footer. In that case, further tolerance can be achieved against malicious tampering by an attacker. Note that a CRC of cyclic redundancy checking, which is one type of error detection code, may be stored in an extended packet footer (s) “ePF1” or “ePF1 and ePF0” (Para 839).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER K PETERSON whose telephone number is (571)270-1704. The examiner can normally be reached Monday-Friday 7AM-4PM.
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/CHRISTOPHER K PETERSON/Primary Examiner, Art Unit 2637 2/4/2026