DETAILED ACTION
This action is responsive to the communication filed 26 June 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species 1 (FIG. 3B) embodiment in the reply filed on 26 June 2026 is acknowledged.
Claims 8, 12-13, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding claim 7: claim 7 states, in relevant part, “and the electrode is an n-type electrode.” The scope of the claim is unclear because the term “n-type electrode” is susceptible to more than one plausible interpretation. Namely it is unclear whether an “n-type electrode” refers to either (1) an electrode formed from an n-type material, or (2) an electrode for an n-type semiconductor layer. For the purposes of examination, the relevant language has been interpreted according to interpretation (1).
Regarding claim 10: claim 10 states, in relevant part, “and the electrode is an n-type electrode.” The scope of the claim is unclear because the term “n-type electrode” is susceptible to more than one plausible interpretation. Namely it is unclear whether an “n-type electrode” refers to either (1) an electrode formed from an n-type material, or (2) an electrode for an n-type semiconductor layer. For the purposes of examination, the relevant language has been interpreted according to interpretation (1).
Claim 11, which depends from claim 10, is rejected under § 112(b) for at least the same reasons as claim 10.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2021/0111325 (filed Sept. 18, 2020) (hereinafter “Kim”).
Regarding independent claim 1, Kim discloses: A light-emitting device comprising:
a first type semiconductor layer (FIG. 15, first type semiconductor layer 51, [0101]);
a passivation layer (FIG. 15, passivation layer 57, [0138]) disposed to cover a side surface of the first type semiconductor layer and an edge of an upper surface of the first type semiconductor layer (FIG. 15, depicting wherein the passivation layer 57 covers a side surface of the first type semiconductor layer 51 and an edge of an upper surface of the first type semiconductor layer 51);
an active layer (FIG. 15, light emitting layer 53, [0138]) disposed above the first type semiconductor layer and the passivation layer (FIG. 15, depicting wherein the light emitting layer 53 is disposed above the first type semiconductor layer 51 and the passivation layer 57);
a second type semiconductor layer (FIG. 15, second type semiconductor layer 55, [0138]) disposed above the active layer (FIG. 15, depicting wherein the second type semiconductor layer 55 is disposed above the light emitting layer 53); and
an electrode (FIG. 15, upper electrode 59, [0138]) disposed to cover a side surface of the passivation layer, a side surface of the active layer, a side surface of the second type semiconductor layer, and an upper surface of the second type semiconductor layer (FIG. 15, depicting wherein the upper electrode covers side surfaces of the passivation layer 57, the light emitting layer 53, and the second type semiconductor layer 55, as well as an upper surface of the second type semiconductor layer 55).
Regarding claim 2, Kim further discloses wherein the passivation layer is disposed to expose a part of the upper surface of the first type semiconductor layer, and the active layer contacts the exposed part of the upper surface of the first type semiconductor layer (FIG. 15, depicting wherein the passivation layer 57 is disposed to expose a part of the upper surface of the first type semiconductor layer 51, and the light emitting layer 53 contacts the exposed part of the upper surface of the first semiconductor layer 51).
Regarding claim 3, Kim further discloses wherein the electrode is a transparent electrode (FIG. 15; [0143]: “Here, the upper electrode 59 included in the LED 50 may be implemented as a transparent electrode.”).
Regarding claim 4, Kim further discloses wherein the electrode is disposed above an outermost layer disposed above a side surface and an upper surface of the light-emitting device (FIG. 15, depicting wherein the upper electrode 59 is disposed above an upper surface and a side surface of an outermost layer of, e.g., the second type semiconductor layer 55).
Regarding claim 5, Kim further discloses wherein a lower end of the electrode and a lower end of the first type semiconductor layer are disposed above a same plane (FIG. 15, depicting wherein the lower ends of the first type semiconductor layer 51 and the upper electrode 59 are disposed above a same plane, e.g., the plane in which the substrate 10 is disposed).
Regarding claim 6, Kim further discloses wherein the passivation layer is disposed between the electrode and the first type semiconductor layer (FIG. 15, depicting wherein the passivation layer 57 is disposed between the upper electrode 59 and the first type semiconductor layer 51).
Regarding claim 7, Kim further discloses wherein the first type semiconductor layer is a semiconductor layer doped with p-type impurities (FIG. 15, [0116]: “The first type semiconductor layer 51 may be one of an n-type semiconductor and a p-type semiconductor, and the second type semiconductor layer 55 may be one different from the first type semiconductor layer 51 of the n-type semiconductor and the p-type semiconductor.”), the second type semiconductor layer is a semiconductor layer doped with n-type impurities (FIG. 15, [0116]: “The first type semiconductor layer 51 may be one of an n-type semiconductor and a p-type semiconductor, and the second type semiconductor layer 55 may be one different from the first type semiconductor layer 51 of the n-type semiconductor and the p-type semiconductor.”), and the electrode is an n-type electrode (FIG. 15, depicting wherein the upper electrode 59 is an electrode for the second type semiconductor layer 55, which may be an n-type semiconductor; see also [0144]: “Here, the transparent electrode may include at least one of carbon nano tube (CNT), graphene, or metal nano wire, and may also be implemented with various materials such as indium tin oxide (ITO), conductive polymer (e.g., Pedot:pss, or the like), Au, Pt, SnO2, and TiO2, which have high light transmittance and electrical conductivity.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Patent Publication No. 2022/0293670 (filed Dec. 9, 2021) (hereinafter “Lee”).
Regarding independent claim 9, Kim discloses: A display device comprising:
a substrate (FIG. 15, substrate 10, [0095]) above which a plurality of pixels each comprising a plurality of subpixels are disposed (FIGS. 1/15, depicting a plurality of pixels 100 each comprising a plurality of subpixels, [0087]);
a plurality of transistors respectively disposed above the plurality of subpixels (FIGS. 3/15, depicting, for each LED 50, a driving circuit layer 20 including a pixel circuit, wherein each pixel circuit 21 includes a switching element, wherein the switching element may be a TFT, [0099]);
a first connection electrode (FIGS. 3/15, e.g., first electrode 28, [0101]) connected to the plurality of transistors (FIG. 15, depicting wherein the first electrode 28 is electrically connected to the driving circuit layer including the TFT);
a second connection electrode (FIGS. 3/15, e.g., second electrode 29, [0101]) spaced apart from the first connection electrode (FIG. 15, depicting wherein the second electrode 29 is spaced apart from the first electrode 28); and
a light-emitting element (FIG. 15, LED 50, [0087]) disposed above the first connection electrode and the second connection electrode (FIG. 15, depicting wherein the LED 50 is disposed above the electrodes 28/29), and electrically connected to the first connection electrode and the second connection electrode (FIG. 15, depicting wherein the LED 50 is electrically connected to the electrodes 28/29),
wherein the light-emitting element includes:
a first type semiconductor layer (FIG. 15, first type semiconductor layer 51, [0101]);
a passivation layer (FIG. 15, passivation layer 57, [0138]) disposed to cover a side surface of the first type semiconductor layer and an edge of an upper surface of the first type semiconductor layer (FIG. 15, depicting wherein the passivation layer 57 covers a side surface of the first type semiconductor layer 51 and an edge of an upper surface of the first type semiconductor layer 51);
an active layer (FIG. 15, light emitting layer 53, [0138]) disposed above the first type semiconductor layer and the passivation layer (FIG. 15, depicting wherein the light emitting layer 53 is disposed above the first type semiconductor layer 51 and the passivation layer 57);
a second type semiconductor layer (FIG. 15, second type semiconductor layer 55, [0138]) disposed above the active layer (FIG. 15, depicting wherein the second type semiconductor layer 55 is disposed above the light emitting layer 53); and
an electrode (FIG. 15, upper electrode 59, [0138]) disposed to cover a side surface of the passivation layer, a side surface of the active layer, a side surface of the second type semiconductor layer, and an upper surface of the second type semiconductor layer (FIG. 15, depicting wherein the upper electrode covers side surfaces of the passivation layer 57, the light emitting layer 53, and the second type semiconductor layer 55, as well as an upper surface of the second type semiconductor layer 55).
Kim does not specifically disclose a first planarization layer disposed above the plurality of transistors.
In the same field of endeavor, Lee discloses a light emitting device including a planarization layer disposed above a plurality of transistors (FIG. 3, planarization layer OC1 disposed above a plurality of thin film transistors TFT, [0093]). Regarding the planarization layer, in [0093], Lee states: “The first planarization layer OC1 may be provided on the first passivation layer PAS1 and may planarize the tops of the thin-film transistors TFT.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Kim by adding the planarization layer of Lee in order to planarize the tops of the TFTs of Kim. See Lee [0093].
Moreover, addition of the planarization layer OC1 of Lee would result in a configuration wherein the electrodes 28/29 are disposed above the planarization layer OC1.
Regarding claim 10, Kim in vie of Lee further discloses wherein the first type semiconductor layer is a semiconductor layer doped with p-type impurities (FIG. 15, [0116]: “The first type semiconductor layer 51 may be one of an n-type semiconductor and a p-type semiconductor, and the second type semiconductor layer 55 may be one different from the first type semiconductor layer 51 of the n-type semiconductor and the p-type semiconductor.”), the second type semiconductor layer is a semiconductor layer doped with n-type impurities (FIG. 15, [0116]: “The first type semiconductor layer 51 may be one of an n-type semiconductor and a p-type semiconductor, and the second type semiconductor layer 55 may be one different from the first type semiconductor layer 51 of the n-type semiconductor and the p-type semiconductor.”), and the electrode is an n-type electrode (FIG. 15, depicting wherein the upper electrode 59 is an electrode for the second type semiconductor layer 55, which may be an n-type semiconductor; see also [0144]: “Here, the transparent electrode may include at least one of carbon nano tube (CNT), graphene, or metal nano wire, and may also be implemented with various materials such as indium tin oxide (ITO), conductive polymer (e.g., Pedot:pss, or the like), Au, Pt, SnO2, and TiO2, which have high light transmittance and electrical conductivity.”).
Regarding claim 11, Kim in view of Lee further discloses wherein the electrode of the light-emitting element is electrically connected to the second connection electrode (FIG. 15, depicting wherein the upper electrode 59 is electrically connected to the second electrode 29), and the first type semiconductor layer of the light-emitting element is electrically connected to the first connection electrode (FIG. 15, depicting wherein the first type semiconductor layer 51 is electrically connected to the first electrode 28).
Regarding claim 14, Kim in view of Lee further discloses a second planarization layer (FIGS. 3/15, intermediate substrate including an adhesive portion 43, [0105]-[0106]) disposed above the first planarization layer and the second connection electrode and configured to surround the light-emitting element (FIG. 15, depicting wherein the adhesive portion is disposed above the planarization layer OC1 of Lee and the second electrode 29 and configured to surround the LED 50).
Regarding claim 15, Kim in view of Lee further discloses wherein the second planarization layer is disposed to expose a part of the second connection electrode and the first connection electrode (FIG. 15, depicting wherein the adhesive portion 43 is disposed to expose a part of the second electrode 29 and the first electrode 28), and the light-emitting element is disposed above the exposed part of the second connection electrode and the exposed first connection electrode (FIG. 15, depicting wherein the LED 50 is disposed above the exposed parts of the first and second electrodes 28/29).
Regarding claim 16, Kim in view of Lee further discloses a bank (FIG. 15, black matrix 60, [0160]) disposed above the second planarization layer, wherein the bank includes a black material (FIG. 15, depicting wherein the black matrix 60 is disposed above the adhesive portion 43 and includes a material that has a black color, [0161]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 2022/0254961 (published Aug. 11, 2022) (disclosing an inorganic led with various electrode and passivation configurations); 2017/0117257 (published Apr. 27, 2017) (disclosing an inorganic led with various electrode and passivation configurations); 2018/0358339 (filed Nov. 9, 2016) (disclosing an inorganic led with various electrode and passivation configurations); 2021/0057609 (filed Aug. 18, 2020) (disclosing an inorganic led with various electrode and passivation configurations); 2018/0040774 (filed June 28, 2017); 2017/0104009 (filed Oct. 6, 2016) (disclosing an inorganic led with various electrode and passivation configurations).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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