DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed 05/06/2024 has been considered by the Examiner.
Specification
The disclosure is objected to because of the following informalities:
Par. [0014], line 5: “function blacks” should be changed to “function blocks”.
Par. [0047], line 4: “with in” should be “within”.
Appropriate correction is required.
Claim Interpretation
The term “level elevator” used throughout the claims appears to be synonymous with the term “level shifter”, a well-known term in the art for describing a circuit used to translate signals from one logic level or voltage domain to another.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The Applicant’s disclosure was reviewed to ensure that the Applicant had written description support for the claims. It is noted that Applicant was found to have written description for the instant claims, specifically in Pars. [0124-0132] of the Specification and in Figs. 14A-D.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation “the electrodes” renders claim 20 (line 2) indefinite. It is unclear if the “electrodes” are the same as the “electrode nodes” introduced in claim 1. Please consider revising to “the electrode nodes”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, and 10-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 10,786,665 (hereinafter ‘665 Patent). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claims 1-2, 4, and 10-12 of the instant application, claim 3 of the ‘665 Patent discloses:
A pulse generator (Claim 1, line 1), comprising:
a plurality of electrode nodes, each electrode node configured to be coupled to an electrode to provide stimulation pulses to a patient’s tissue (Claim 1, lines 2-4);
digital-to-analog converter circuitry (Claim 1, line 5), comprising
a source circuit configured to source a source current to any of the electrode nodes (Claim 1, lines 6-7), and
a sink circuit configured to sink a sink current from any of the electrode nodes (Claim 1, lines 11-12); and
a plurality of level elevators, wherein the level elevators are configured to convert first digital control signals issued in a first power domain to second digital control signals issued in a second power domain (Claim 3, lines 4-8), wherein the second control signals are configured to control operation of the source circuit (Claim 3, lines 7-8 – first control signals are of the first power domain; Claim 1, lines 6-10 – first power domain associated with source circuit).
The pulse generator of claim 1, wherein the second power domain is defined by a first power supply voltage and a second power supply voltage (Claim 1, lines 8-10).
The pulse generator of claim 2, wherein the source circuit is powered by the first and second power supply voltages (Claim 1, lines 7-10).
The pulse generator of claim 2, wherein the first power domain is defined by a third power supply voltage and a fourth power supply voltage (Claim 1, lines 12-15).
The pulse generator of claim 10, wherein the first digital control signals comprise logic states comprising the third and fourth power supply voltages (Claim 3, lines 2-4; Claim 1, lines 12-15).
The pulse generator of claim 10, wherein the sink circuit is powered by the third and fourth power supply voltages (Claim 1, lines 11-15).
Claim 3 of the ‘665 Patent anticipates instant claims 1-2, 4, and 10-12. Therefore, the instant claims 1-2, 4, and 10-12 are not patentable over claim 3 of the ‘665 Patent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Parramon, et al. (U.S. Patent No. 8,620,436 – cited on IDS).
Regarding claim 1, Parramon teaches (Fig. 1, # 100) a pulse generator (Abstract – Disclosed herein is a current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG); Col. 1, lines 15-20 and 41-45; Col. 6, lines 33-48; Col. 8, lines 31-41), comprising:
(Fig. 8A and 10, # E1-n – electrode nodes) a plurality of electrode nodes, each electrode node configured to be coupled to an electrode to provide stimulation pulses to a patient’s tissue (Col. 6, lines 33-48 – e.g., spinal cord stimulation (SCS); Col. 8, lines 31-41 – electrodes Ex on the IPG 100);
(Figs. 8-10, # NDAC and PDAC) digital-to-analog converter circuitry (Col. 5, lines 32-43 – the dedicated circuitry preferably comprises digital-to-analog current converters (DACs); Col. 6, lines 49-55; Col. 7, lines 47-67), comprising
(Fig. 8A-B and 10, # 400 – source circuitry) a source circuit configured to source a source current to any of the electrode nodes (Col. 9, lines 7-17 – dedicated source and sink circuitry at each electrode), and
(Figs. 8A-B, # 401 – sink circuitry) a sink circuit configured to sink a sink current from any of the electrode nodes (Col. 9, lines 7-17 – dedicated source and sink circuitry at each electrode); and
(Fig. 10, # 400 – source circuitry, 415 – level shifters, i.e. level elevators) a plurality of level elevators, wherein the level elevators are configured to convert first digital control signals issued in a first power domain to second digital control signals issued in a second power domain, wherein the second control signals are configured to control operation of the source circuit (Col. 7, lines 31-46 – As shown in Fig. 10, the control signals to the switches 417 may need to be level shifted to DC values appropriate for the switches 417, which can easily occur via level shifters 415, as one skilled in the art will understand).
Therefore, claim 1 is unpatentable over Parramon, et al.
Regarding claim 20, Parramon teaches the pulse generator of claim 1, further comprising (Fig. 1, # 102 – lead, 106 – electrodes) at least one implantable lead, wherein the electrodes are located on the lead (Col. 1, lines 41-61 – The IPG is coupled to electrodes 106 via one or more electrode leads (two such leads 102 and 104 are shown), such that the electrodes 106 form an electrode array 110).
Therefore, claim 20 is unpatentable over Parramon, et al.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-7 and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Parramon, et al. (U.S. Patent No. 8,620,436 – cited on IDS) in view of Liu, et al. (U.S. PGPub No. 2016/0038739).
Regarding claim 2, Parramon teaches the pulse generator of claim 1, as indicated hereinabove. Parramon does not explicitly teach the limitation of instant claim 2, that is wherein the second power domain is defined by a first power supply voltage and a second power supply voltage.
Liu, which is directed to analogous art, teaches a high channel count high-voltage neural stimulator that provides an external circuit which communicates power and data to a neural stimulator implant circuit (Title, Abstract). Liu also teaches the limitation of instant claim 2, that is wherein (Fig. 12A, # 276 – level shifter; Fig. 12B; Fig. 12C) the second power domain is defined by a first power supply voltage and a second power supply voltage (Par. [0069]; Par. [0070] – Fig. 12B depicts 3 stages of the level shifter, from a voltage of +1.8V to ±1.8V in a first shift; then from ±1.8V to +12V/-1.8V in a second shift; then from +12V/-1.8V to ±12V in the third shift.; Par. [0071]; It is noted that the resulting output from the level shifter (i.e., level elevator) is a power domain (i.e., second power domain) defined by a first power supply voltage and a second power supply voltage. For instance, the output of level shifter 1 includes first and second powers of -1.8V and 1.8V.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented Liu’s feature of the second power domain being defined by first and second power supply voltages into Parramon’s level shifters, because doing so would simply be applying well-known features of level shifters, as evidenced by Liu. One of ordinary skill in the art would recognize that Parramon broadly suggests using level shifters and explains that one of ordinary skill in the art would understand how to use them (Col. 7, lines 31-46 of Parramon). One of ordinary skill in the art would have therefore been motivated to look to Liu for further specific direction as to implementation of level shifters being used to elevate the voltage levels in a stimulation device.
Therefore, claim 2 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 3, Parramon, in view of Liu, renders obvious the pulse generator of claim 2, as indicated hereinabove. Liu also teaches the limitation of instant claim 3, that is wherein (Fig. 12A-C) the second digital control signals comprise logic states comprising the first and second power supply voltages (Par. [0069] – a command is received 272 from the DPSK to a global digital control (GDC) circuit 274, which outputs digital control lines to a level shifter 276; Par. [0070-0071]; the level shifter shifts the control signals corresponding to logic states from the DPSK to second digital control signals comprising logic states comprising the first and second power supply voltages).
Therefore, claim 3 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 4, Parramon, in view of Liu, renders obvious the pulse generator of claim 2, as indicated hereinabove. Liu also teaches the limitation of instant claim 4, that is wherein (Figs. 12A-C) the source circuit is powered by the first and second power supply voltages (Par. [0069-0071]).
Therefore, claim 4 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 5, Parramon, in view of Liu, renders obvious the pulse generator of claim 4, as indicated hereinabove. Liu also teaches the limitation of instant claim 5, that is wherein (Fig. 12B) the first and second power supply voltages are configured to vary (Par. [0070]).
Therefore, claim 5 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 6, Parramon, in view of Liu, renders obvious the pulse generator of claim 5, as indicated hereinabove. Parramon teaches the limitation of instant claim 6, that is wherein (Fig. 1, # 116) the pulse generator is further comprising a battery with a battery voltage, and boost circuitry for producing the first power supply voltage from the battery voltage (Col. 1, lines 41-61 – the case 116 hods the circuitry and power source or battery necessary for the IPG to function).
Therefore, claim 6 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 7, Parramon, in view of Liu, renders obvious the pulse generator of claim 5, as indicated hereinabove. Liu also teaches the limitation of instant claim 7, that is wherein (Fig. 12B) the variable second power supply voltage comprises a fixed difference with the variable first power supply voltage (Par. [0070] – It should also be appreciated that different voltage levels may be utilized for these low and high voltages without limitation).
Therefore, claim 7 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 9, Parramon, in view of Liu, renders obvious the pulse generator of claim 2, as indicated hereinabove. Liu also teaches the limitation of instant claim 9, that is wherein (Fig. 9, # 34; Fig. 12A, # 274; Fig. 12B) the pulse generator is further comprising a ground power supply voltage equal to ground, wherein neither the first nor the second power supply voltages are ground (Par. [0060]; Par. [0069] – Global digital control (GDC) circuit 274 comprises a voltage equal to ground (i.e., 0V) (see Fig. 12A); Par. [0070] – Neither the first nor second power supply voltages are ground. For instance, these supply voltages can be -1.8V and 1.8V).
Therefore, claim 9 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 10, Parramon, in view of Liu, renders obvious the pulse generator of claim 2, as indicated hereinabove. Liu also teaches the limitations of instant claim 10, that is wherein (Fig. 12A, # 274 and 276) the first power domain is defined by a third power supply voltage and a fourth power supply voltage (Par. [0069] – the outputted digital control lines from the GDC 274 to the level shifter 276 has a first power domain defined by third and fourth power voltages (0V and -1.8V)).
Therefore, claim 10 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 11, Parramon, in view of Liu, renders obvious the pulse generator of claim 10, as indicated hereinabove. Liu also teaches the limitation of instant claim 11, that is wherein (Figs. 12A-C) the first digital control signals comprise logic states comprising the third and fourth power supply voltages (Par. [0069] – a command is received 272 from the DPSK to a global digital control (GDC) circuit 274, which outputs digital control lines to a level shifter 276; Par. [0070-0071]; the level shifter shifts the first control signals corresponding to logic states from the DPSK that correspond to third and fourth power supply voltages).
Therefore, claim 11 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 12, Parramon, in view of Liu, renders obvious the pulse generator of claim 10, as indicated hereinabove. Parramon also teaches the limitation of instant claim 12, that is wherein (Fig. 8A, # 401) the sink circuit is powered by the third and fourth power supply voltages (Col. 6, line 56-Col. 7, line 19; the sink circuit 401 is powered by two supply voltages (i.e., third and fourth power supply voltages)).
Therefore, claim 12 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 13, Parramon, in view of Liu, renders obvious the pulse generator of claim 10, as indicated hereinabove. Liu also teaches the limitation of instant claim 13, that is wherein (Fig. 12A, # 274 and 276) the third and fourth power supply voltages are constant (Par. [0069] – the outputted digital control lines from the GDC 274 to the level shifter 276 has a first power domain defined by third and fourth power voltages (0V and -1.8V), which stay constant).
Therefore, claim 13 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 14, Parramon, in view of Liu, renders obvious the pulse generator of claim 13, as indicated hereinabove. Liu also teaches the limitation of instant claim 14, that is wherein (Fig. 12A, # 274 and 276) the fourth power supply voltage is equal to ground (Par. [0069] – the outputted digital control lines from the GDC 274 to the level shifter 276 has a first power domain defined by third and fourth power voltages (0V and -1.8V); 0V=ground).
Therefore, claim 14 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 15, Parramon, in view of Liu, renders obvious the pulse generator of claim 10, as indicated hereinabove. Liu also teaches the limitation of instant claim 15, that is wherein (Fig. 12A, # 274 and 276) the fourth power supply voltage comprises a fixed difference with the third power supply voltage (Par. [0069] – the outputted digital control lines from the GDC 274 to the level shifter 276 has a first power domain defined by third and fourth power voltages (0V and -1.8V) (i.e., fixed difference)).
Therefore, claim 15 is unpatentable over Parramon, et al. and Liu, et al.
Regarding claim 16, Parramon, in view of Liu, renders obvious the pulse generator of claim 15, as indicated hereinabove. Liu also teaches the limitation of instant claim 16, that is wherein (Fig. 12B) the first and second power supply voltages differ by the fixed difference (Par. [0070] – It should also be appreciated that different voltage levels may be utilized for these low and high voltages without limitation).
Therefore, claim 16 is unpatentable over Parramon, et al. and Liu, et al.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Parramon, et al. (U.S. Patent No. 8,620,436 – cited on IDS) and Liu, et al. (U.S. PGPub No. 2016/0038739), further in view of Shi, et al. (U.S. Patent No. 7,444,181 – cited on IDS).
Regarding claim 8, Parramon, in view of Liu, renders obvious the pulse generator of claim 5, as indicated hereinabove. Neither Parramon nor Liu explicitly teach the limitation of instant claim 8, that is wherein the first and second power supply voltages are configured to vary based on a first measurement taken from the source circuit and/or a second measurement taken from the sink circuit.
Shi is directed to analogous art, and teaches techniques for sensing and adjusting a compliance voltage in an implantable stimulator device (Title, Abstract). Shi also teaches the limitation of instant claim 8, that is wherein (Fig. 10, # 500 and 501) the first and second power supply voltages are configured to vary based on a first measurement taken from the source circuit and/or a second measurement taken from the sink circuit (Col. 12, line 52-Col. 13, line 3 – should the measured voltages across the output of the PDAC or NDAC be outside of the guard band voltages, the compliance voltage, V+, is changed to attempt to bring such measured voltages within acceptable limits.; Col. 19, lines 40-50; Claim 1).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented Shi’s feature of regulating the voltages of the PDAC or NDAC (i.e., source and sink circuits) based on measurements into Parramon’s, as modified by Liu, device, as doing so would be an example of using a known technique to improve similar devices in the same way. One of ordinary skill in the art would have desired implementing Shi’s technique of measuring and adjusting the voltage in order for the voltages of the source and sink circuits to be compliant and within acceptable limits.
Therefore, claim 8 is unpatentable over Parramon, et al., Liu, et al., and Shi, et al.
Allowable Subject Matter
Claims 17-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record (namely Parramon, et al. and Liu, et al.) does not disclose or fairly suggest either singly or in combination the claimed invention of dependent claim 17 when taken as a whole, comprising, in addition to the other recited claim elements, wherein each level elevator converts logic ‘0’ signals in the first power domain from a first voltage to a second voltage in the second power domain, and wherein each level elevator converts logic ‘1’ signals in the first power domain from a third voltage to a fourth voltage in the second power domain. As shown throughout this office action, Liu is relied upon to teach other aspects of the level elevators (i.e., level shifters). For instance, Liu does teach first power domain, second power domain, first, second, third, and fourth voltages (see prior art rejections hereinabove). However, Liu does not reasonably teach or suggest wherein each level elevator converts logic ‘0’ signals in the first power domain from a first voltage to a second voltage in the second power domain, and wherein each level elevator converts logic ‘1’ signals in the first power domain from a third voltage to a fourth voltage in the second power domain. No other prior art reference could be found that teaches or renders obvious the limitations of instant claim 17. Due to their dependency on claim 17, instant claims 18-19 are also considered to contain allowable subject matter.
Therefore, in view of the prior art and its deficiencies, the claimed invention as a whole is rendered novel and non-obvious, and thus, is allowable as claimed.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a). Specifically, double patenting rejections, 35 U.S.C. 112(b) rejections, 35 U.S.C. 102 rejections, and 35 U.S.C. 103 rejections need to be addressed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Khalil, et al. (U.S. PGPub No. 2014/0277265)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL TAYLOR HOLTZCLAW whose telephone number is (571)272-6626. The examiner can normally be reached Monday-Friday (7:30 a.m.-5:00 p.m. EST).
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/MICHAEL T. HOLTZCLAW/Primary Examiner, Art Unit 3796