DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-8, 11, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ranish U.S. Pat. App. Pub. No. 2023/0396295 in view of Grynewicz et al. U.S. Pat. App. Pub. No. 2023/0261700.
Regarding claim 1, Ranish discloses an apparatus for signal transmission in Figure 6, comprising: a first transmission chain including a first clock (via 64-1) and a first digital-to-analog (DAC) converter (63-1), the first clock coupled to a clock input of the first DAC, wherein the first transmission chain includes a first digital data path coupled to an input of the first DAC; a second transmission chain including a second clock (via 64-2) and a second DAC (63-2), the second clock coupled to a clock input of the second DAC, wherein the second transmission chain includes a second digital data path coupled to an input of the second DAC; and a controller (not shown but providing separate control to delay line circuitry of each channel (see abstract, ¶ [0037]) to set a first data phase associated with the first digital data path based on a first clock phase associated with the first clock generator, as multiple delay parts are jointly provided to the data path and DAC, where the delay for the DAC can be provided by control of DAC sampling (¶¶ [0034-[0035]).
Ranish does not expressly disclose that each chain includes its own clock generator to provide the clock output to the input of the respective DACs.
Grynewicz discloses a multi-beam system employing beamforming channel devices 112 each including their own clock generator for providing a clock signal for respective DACs/ADCs of the device (see Fig. 1A). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide clock generators for each channel device, as suggested by Grynewicz, in the apparatus of Ranish, as it is a known way to provide clock signals in transmission chains of a multi-beam system, yielding predictable results (see § MPEP 2143.I.A.).
Regarding claim 3, in the proposed combination, Ranish further discloses that the controller sets the clock phases to reduce cross-coupling of spurs between the first and second transmission chains, as Ranish discloses that the DACs are employed to reduce transmit quantization noise, where one skilled in the art would recognize that such noise may cause cross-coupling spurs between chains.
Regarding claim 4, in the proposed combination, Ranish further discloses that the first and second transmission chains are configured to perform beamformed transmissions (¶ [0037]).
Regarding claim 5, in the proposed combination, Grynewicz further discloses that the output from the clock generation circuitry may be divided by a frequency divider (¶ [0029]), which would provide an output based on an input clock signal of the divider.
Regarding claim 6, in the proposed combination, the phase of the output clock signal is based on a reset phase of the clock divider (¶ [0031]).
Regarding claim 7, in the proposed combination, the controller of Ranish would also be configured to set a second data phase associated with the second digital data path based on a second clock phase associated with the second clock generator, as the second chain has the same components as the first chain, but are independently controlled in order to apply different delays to each of the signals in the different channels (¶ [0032]).
Regarding claim 8, in the proposed combination, the controller of Ranish would provide first and second clock phases that are different as they are independently controlled in order to apply different delays to each of the signals in the different channels (¶ [0032]).
Regarding claim 11, Ranish discloses a method, comprising setting a first clock phase associated with a clock generator of an apparatus (see Fig. 6), the apparatus comprising: a first transmission chain including a first clock (via 64-1) and a first digital-to-analog (DAC) converter (63-1), the first clock coupled to a clock input of the first DAC, wherein the first transmission chain includes a first digital data path coupled to an input of the first DAC; and a second transmission chain including a second clock (via 64-2) and a second DAC (63-2), the second clock coupled to a clock input of the second DAC, wherein the second transmission chain includes a second digital data path coupled to an input of the second DAC, and setting a first data phase associated with the first digital data path based on the first clock phase associated with the first clock generator, as multiple delay parts are jointly provided to the data path and DAC, where the delay for the DAC can be provided by control of DAC sampling (¶¶ [0034-[0035]).
Ranish does not expressly disclose that each chain includes its own clock generator to provide the clock output to the input of the respective DACs.
Grynewicz discloses a multi-beam system employing beamforming channel devices 112 each including their own clock generator for providing a clock signal for respective DACs/ADCs of the device (see Fig. 1A). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide clock generators for each channel device, as suggested by Grynewicz, in the apparatus of the method of Ranish, as it is a known way to provide clock signals in transmission chains of a multi-beam system, yielding predictable results (see § MPEP 2143.I.A.).
Regarding claim 13, in the proposed combination, Ranish further discloses that the controller sets the clock phases to reduce cross-coupling of spurs between the first and second transmission chains, as Ranish discloses that the DACs are employed to reduce transmit quantization noise, where one skilled in the art would recognize that such noise may cause cross-coupling spurs between chains.
Regarding claim 14, in the proposed combination, Grynewicz further discloses that the output from the clock generation circuitry may be divided by a frequency divider (¶ [0029]), which would provide an output based on an input clock signal of the divider.
Regarding claim 15, in the proposed combination, the phase of the output clock signal is based on a reset phase of the clock divider (¶ [0031]).
Regarding claim 16, in the proposed combination, the controller of Ranish would also be configured to set a second data phase associated with the second digital data path based on a second clock phase associated with the second clock generator, as the second chain has the same components as the first chain, but are independently controlled in order to apply different delays to each of the signals in the different channels (¶ [0032]).
Regarding claim 17, in the proposed combination, the controller of Ranish would provide first and second clock phases that are different as they are independently controlled in order to apply different delays to each of the signals in the different channels (¶ [0032]).
Regarding claim 20, Ranish discloses an apparatus for signal transmission in Figure 6, comprising: at least one first antenna 67-1; a first transmission chain coupled to the first antenna and including a first clock (via 64-1) and a first digital-to-analog (DAC) converter (63-1), the first clock coupled to a clock input of the first DAC, wherein the first transmission chain includes a first digital data path coupled to an input of the first DAC; at least one second antenna 67-2; a second transmission chain coupled to the second antenna and including a second clock (via 64-2) and a second DAC (63-2), the second clock coupled to a clock input of the second DAC, wherein the second transmission chain includes a second digital data path coupled to an input of the second DAC’ and a controller (not shown but providing separate control to delay line circuitry of each channel (see abstract, ¶ [0037]) to set a first data phase associated with the first digital data path based on a first clock phase associated with the first clock generator, as multiple delay parts are jointly provided to the data path and DAC, where the delay for the DAC can be provided by control of DAC sampling (¶¶ [0034-[0035]).
Ranish does not expressly disclose that each chain includes its own clock generator to provide the clock output to the input of the respective DACs.
Grynewicz discloses a multi-beam system employing beamforming channel devices 112 each including their own clock generator for providing a clock signal for respective DACs/ADCs of the device (see Fig. 1A). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide clock generators for each channel device, as suggested by Grynewicz, in the apparatus of Ranish, as it is a known way to provide clock signals in transmission chains of a multi-beam system, yielding predictable results (see § MPEP 2143.I.A.).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ranish in view of Grynewicz et al., as applied to claims 1 and 11 above, and further in view of Quek U.S. Pat. No. 10,128,827.
Regarding claims 2 and 12, Ranish in combination with Grynewicz disclose an apparatus and associated method for signal transmission where a clock phase of a DAC is set, as described above, but do not expressly disclose that the controller sets the first clock phase based on a LUT.
Quek discloses use of a LUT to store settings associated with phase settings of a clock provided to a DAC (col. 6, ll. 39-47). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to employ a LUT to control phase settings of an input provided to a DAC, as suggested by Quek, in the apparatus and method of Ranish and Grynewicz, to provide for predetermined DAC control, thereby reducing calculations required in real time.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ranish in view of Grynewicz et al., as applied to claims 1 and 11 above, and further in view of Kjosness et al. U.S. Pat. No. 7,977,996.
Regarding claims 9 and 18, Ranish in combination with Grynewicz disclose an apparatus and associated method for signal transmission, as described above, but do not expressly disclose that the first digital data path comprises a fractional delay filter to set the first data phase.
Kjosness discloses use of a fractional delay filter 10 for controlling the phase of data input to a D/A converter 20 (see Fig. 1). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide a fractional delay filter to control phase of data to a DAC as suggested by Kjosness, in the apparatus and method of Ranish and Grynewicz, as it provides accurate low jitter edge placement of data (see Kjosness, col. 1, ll. 38-67).
Allowable Subject Matter
Claims 6, 10, 15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Maenza U.S Pat. No. 6,424,282 disclose a method and apparatus for noise compensation in digital to analog converters.
Garg et al. U.S Pat. No. 9,685,969 disclose a digital-to-analog converter architecture with spur calibration.
Gunasekaran et al. U.S. Pat. App. Pub. No. 2022/0239304 disclose DAC spur estimation and correction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David B. Lugo whose telephone number is 571-272-3043. The examiner can normally be reached M-F, 9-6.
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah Wang can be reached at 571-272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID B LUGO/Primary Examiner, Art Unit 2631 1/9/2026