Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/06/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 9–15 and 19–25 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Representative Claim 9 recites: “A method comprising: programming display pixels of an electronic display with a plurality of test patterns; measuring resulting currents through pixel circuitry of the display pixels using test circuitry disposed in the electronic display; and identifying a presence or absence of vertical or horizontal cross talk based on the measurements.”
The claim limitations reciting the judicial exception are highlighted in bold above; the remaining limitations are treated as additional elements.
Step 1 – Statutory Category
Under Step 1 of the eligibility analysis, it is determined whether the claims fall within one of the four statutory categories of patentable subject matter.
Claim 9, as well as claims 10–15 and 19–25, are methods and are therefore considered to fall within a statutory category (process).
Step 2A, Prong One – Judicial Exception
Under Step 2A, Prong One, it is determined whether the claims recite a judicial exception.
Under their broadest reasonable interpretation, the highlighted portions of Claim 9 recite an abstract idea because they fall within the groupings of abstract ideas identified in the 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG), specifically:
• Mental processes, including observation, evaluation, and judgment
• Data analysis and comparison
In particular:
• The step of measuring resulting currents constitutes data collection.
• The step of identifying a presence or absence of vertical or horizontal cross talk based on the measurements constitutes an evaluation and judgment based on collected data.
These steps can be practically performed by a human using routine measurement tools and comparing measured values to expected behavior or specifications. Nothing in the claim precludes such identification from being performed mentally once the data is obtained. Accordingly, Claim 9 recites a judicial exception.
Step 2A, Prong Two – Practical Application
Under Step 2A, Prong Two, it is evaluated whether the claim integrates the judicial exception into a practical application.
Claim 9 recites the following additional elements: Programming display pixels with test patterns & Measuring currents using test circuitry disposed in the electronic display. These additional elements constitute mere data gathering and conventional testing activity, which is considered insignificant extra-solution activity. The test circuitry and display pixels are recited at a high level of generality and function only as generic components used to collect information for the abstract evaluation step.
The claim does not improve the functioning of the display, the pixel circuitry, or the test circuitry itself, nor does it affect a transformation of matter beyond data acquisition.
Therefore, Claim 9 does not integrate the judicial exception into a practical application and requires analysis under Step 2B.
Step 2B – Significantly More
Claim 9 does not include additional elements that amount to significantly more than the judicial exception.
The additional elements are well-understood, routine, and conventional in the art, as evidenced by Somerville et al. (U.S. 2010/0295860 A1), which discloses: A display panel including scan lines, data lines, and color pixels; Pixel driving transistors; Scan drivers and data drivers for applying signals; Controllers that calculate and apply voltages based on measured or derived pixel behavior & Signal controllers that generate control and image data signals. As in the present claims, Somerville et al. employ standard electrical measurements and control logic without improving the underlying technology of the display hardware itself. Accordingly, the ordered combination of elements in claim 9 amounts to nothing more than applying abstract data evaluation using conventional display components.
Independent claims 19 & 22 recite limitations similar to claim 9 and is therefore rejected on the same grounds for being directed to an abstract idea without significantly more
Dependent Claims
Claims 10–12 and 18 add limitations relating to the absence of self-emissive elements and determinations to discard or proceed with installation based on the identification result. These limitations merely add post-solution decision-making steps, which remain within the mental process grouping and do not add meaningful technical limitations. The presence or absence of self-emissive elements does not change the abstract nature of the evaluation itself. Accordingly, Claims 10–12 and 18 are rejected on the same grounds as Claim 9.
Claim 13 recites: measuring display pixel currents and identifying a defect based on the measured currents.
Claims 14 and 15 further specify identifying scan line integrity based on whether currents fall within a specification. These steps constitute abstract data analysis and mental evaluation and do not recite a practical application beyond generic testing.
Claim 19 recites applying bias or stress, measuring aggregate current, and identifying a defective pixel based on whether the current is outside a specification.
Claims 20 & 21 further recite repetition using binary search patterns and pre-installation conditions. These claims recite abstract evaluation of electrical measurements and iterative searching, which are mental processes and data analysis techniques. The application of stress and repetition do not meaningfully limit the abstract idea.
Claim 22 recites enabling a source driver, measuring voltage over time, and identifying a defect based on measured voltage behavior.
Claims 23–25 add stress conditions, temperature, and time duration. These claims recite observing signal behavior and identifying defects based on expected versus observed values, which constitutes abstract evaluation. The recited circuitry and stress conditions are conventional and do not amount to significantly more.
Eligible Claims
Claims 16–18 are not rejected under 35 U.S.C. § 101, as they recite specific operational testing configurations that integrate electrical measurements with concrete defect detection mechanisms, including bright dot pixel detection and binary search localization, which together constitute a practical application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-23 & 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chaji et al. (US 2014/0329339 A1).
Regarding claim 1, Chaji et al. disclose in Figs. 1-3, a system comprising: an electronic display(12)(see [0039]) configured to connect anodes of self-emissive elements (via OLED 52) (via OLEDs arranged as display pixels, see paragraphs [0049] & [0053]) of selected display pixels (67)(see [0047]) to a test signal (146) not supplied by pixel circuitry ( 64)(see [0046]); and a testing device (68 & 76)(see [0048]) configured to measure an aggregate current out of cathodes of the self-emissive elements (via OLED 52) of the selected display pixels (67)(see [0047]) that results due to the test signal (146) to enable a current-voltage (IV) characterization of the self-emissive elements (via OLED 52) of the selected display pixels (67)(see paragraphs [0058]).
Regarding claim 2, Chaji et al. disclose the system of claim 1, wherein Chaji et al. further disclose the selected display pixels (67)(see [0047]) comprise a plurality of rows (see [0060]) of display pixels (67)(see [0047]) of the electronic display representing fewer than all rows (see [0060]) of the electronic display (paragraphs [0186]–[0189], [0195]).
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Regarding claim 3, Chaji et al. disclose the system of claim 2, wherein Chaji et al. further disclose the plurality of rows (see [0060]) are centrally located in the electronic display (see selecting rows of pixels within the active display area, including internal reference rows and centrally located rows used for measurement and compensation, see paragraph [0060] & claim 3).
Regarding claim 4, Chaji et al. disclose the system of claim 2, wherein Chaji et al. further disclose he plurality of rows (see [0060]) are located closer to an upper or lower region of the electronic display (see [0053] wherein selecting rows (see [0060]) near edges and peripheral regions of the display for diagnostic testing and reference purposes)
Regarding claim 5, Chaji et al. disclose the system of claim 1, wherein Chaji et al. further disclose the electronic display is configured to supply a plurality of test signals (146) (Chaji et al. disclose supplying multiple test signals including different reference currents, programming voltages, bias voltages, and stress signals during testing (paragraphs [0057]–[0058]).
Regarding claim 6, Chaji et al. disclose the system of claim 5, wherein Chaji et al. further disclose the selected display pixels (67)(see [0047]) comprise a first plurality of rows (see [0060]) of display pixels (67)(see [0047]) of the electronic display when a first test signal (146) of the plurality of test signals (146) is supplied and a second plurality of rows (see [0060]) of display pixels (67)(see [0047]) of the electronic display when a second test signal (146) of the plurality of test signals (146) is supplied (Chaji et al. disclose [0058] varying tested row groups based on applied test signals and different testing modes, including quick scans and detailed scans using different bias conditions).
Regarding claim 7, Chaji et al. disclose the system of claim 6, wherein Chaji et al. further disclose the first plurality of rows (see [0060]) is greater than the second plurality of rows (see [0060]) and the first test signal (146) has a lower voltage than the second test signal (146)(Chaji et al. disclose applying different test voltages and currents to different pixel groups, including coarse scans using lower stress signals and narrower scans using higher stress signals (paragraphs [0057]).
Regarding claim 9 Chaji et al. disclose a method comprising: programming (18, see [0036]) display pixels (67)(see [0047]) of an electronic display with a plurality of test patterns (see [0062]); measuring resulting currents through pixel circuitry ( 64)(see [0046]) of the display pixels (67)(see [0047]) using test circuitry disposed in the electronic display; and identifying a presence or absence of vertical or horizontal cross talk based on the measurements (Chaji et al. disclose [0062] programming pixels with test patterns, measuring pixel currents using integrated test circuitry, and identifying line shorts and cross talk based on measured current and voltage behavior).
Regarding claim 10, Chaji et al. disclose the method of claim 9, wherein Chaji et al. further disclose the electronic display lacks self-emissive elements (via OLED 52) during programming (18, see [0036]) and measuring (Chaji et al. disclose testing a TFT backplane prior to OLED deposition, wherein no self-emissive elements (via OLED 52) are present during measurement).
Regarding claim 11, Chaji et al. disclose the method of claim 10, wherein Chaji et al. further disclose determining to discard the electronic display in response to identifying the presence of the vertical or horizontal cross talk based on the measurements (Chaji et al. disclose determining whether to continue fabrication, repair, or discard a panel based on detected defects exceeding thresholds (paragraphs [0186]–[0189]).
Regarding claim 12, Chaji et al. disclose the method of claim 10, wherein Chaji et al. further disclose determining to install self-emissive elements (via OLED 52) in the display pixels (67)(see [0047]) of the electronic display in response to identifying the absence of the vertical or horizontal cross talk based on the measurements (Chaji et al. disclose proceeding with OLED deposition only after backplane testing confirms acceptable defect levels, see [0159]).
Regarding claim 13, Chaji et al. disclose the measuring display pixel currents associated with at least two display pixels (67)(see [0047]) of an electronic display using electrical test circuitry disposed in the electronic display (measuring currents of multiple display pixels 104 using test circuitry 200 integrated in electronic display 100, FIGS. 1–2, paragraphs [0051]–[0053]); and identifying a defect of the electronic display based on the measured display pixel currents (defect identification logic implemented using current comparison against specification thresholds, paragraphs [0054]–[0057]).
Regarding claim 14, Chaji et al. disclose the method of claim 13, wherein Chaji et al. further disclose the at least two display pixels (67)(see [0047]) comprise a first display pixel of a row and a last display pixel of the row (see [0042] wherein first and last pixels 104 located along a common scan line, FIG. 1 & [0045]); and identifying the defect comprises identifying an integrity of a horizontal scan line based on whether the measured display pixel currents of the at least two display pixels (67)(see [0047]) fall within a specification (see paragraphs [0068]–[0070]).
Regarding claim 15, Chaji et al. disclose the method of claim 13, wherein Chaji et al. further disclose the test signal (146) is applied to anodes of the self-emissive elements (via OLED 52) (Chaji et al. disclose applying programming (18, see [0036]), bias, and test voltages directly to OLED anodes through data lines, monitor lines, probe pads, and test circuitry (paragraphs [0049] & [0054]).
Regarding claim 16, Chaji et al. disclose the method of claim 13, wherein Chaji et al. further disclose all the display pixels (67)(see [0047]) of the electronic display; and identifying the defect comprises identifying a presence of a bright dot pixel defect based on whether the measured currents of the at least two display pixels (67) are nonzero (see paragraphs [0061] & [0072])
Regarding claim 17, Chaji et al. disclose the method of claim 13, wherein Chaji et al. further disclose the programming (18, see [0036]), measuring, and identifying in a binary search pattern in response to identifying the presence of the bright dot pixel defect (Chaji et al. disclose selective pixel testing including partial rows (see [0060]), columns, groups, and priority-based subsets of pixels rather than the full display (see [0085-0086]).
Regarding claim 18, Chaji et al. disclose the method of claim 13, wherein Chaji et al. further disclose the plurality of display pixels (67)(see [0047]) are selected based on a location in the electronic display (Chaji et al. disclose selecting pixels based on spatial location including rows, columns, peripheral regions, central regions, and defect-localized regions, see paragraph [0053]).
Regarding claim 19, Chaji et al. disclose a method comprising: applying a bias or stress, or both, to display pixels (67)(see [0047]) of an electronic display; measuring an aggregate current of all columns of the display pixels (67)(see [0047]); and identifying a presence or absence of a defective pixel based on a presence of a current that is outside of a specification (Chaji et al. disclose identifying row-to-row and column-to-column shorts and cross talk by comparing measured currents under different biasing and programming conditions (see, [0036-0038]).
Regarding claim 20, Chaji et al. disclose the method of claim 19, wherein Chaji et al. further disclose identifying a defect in the electronic display based on the measured current (Chaji et al. disclose [0049] detecting defects including shorts, opens, leakage, non-uniformities, and aging effects based on measured current and voltage data, see [0053]).
Regarding claim 21, Chaji et al. disclose the method of claim 19, wherein Chaji et al. further disclose the method is performed before any self-emissive elements (via OLED 52) are installed on the electronic display (Chaji et al. disclose processor-executed algorithms stored in memory and implemented via software, firmware, or hardware for performing pixel measurement, see[0056] & [0085])
Regarding claim 22, Chaji et al. disclose The non-transitory computer-readable medium of claim 21, wherein the instructions cause the processor to select the plurality of display pixels (67)(see [0047]) based on a location in the electronic display (Chaji et al. disclose software-controlled selection of pixels based on location, defect regions, priority regions, and scan optimization logic, see [0074] & [0158]).
Regarding claim 23, Chaji et al. disclose the method of claim 23, wherein Chaji et al. further disclose applying a stress (see [0086]) to the electronic display while at least part of the method is carried out (Chaji et al. disclose software-based analysis of measured current data to identify cross talk and line defects, see paragraphs [0108]).
Regarding claim 25, Chaji et al. disclose the method 22 is performed over a plurality of minutes (see [0107-0108]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 & 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaji et al. (U.S. 2014/0329339 A1) in view of Zou et al. (U.S. 2019/0073955 A1).
Regarding claim 8, Chaji et al. are not understood to explicitly disclose that the test signal is supplied over an anode reset line of the electronic display.
Zou et al. disclose that the test signal is supplied over an anode reset line of the electronic display (see [0059-0060] wherein pixel driving circuits for self-emissive OLED displays in which anodes of light-emitting elements are reset through dedicated reset circuits and reset signal lines prior to and during driving and testing stages (see first reset circuit 50, reset terminal RST, and anode reset operations, paragraphs [0078]–[0082]). Zou et al. further disclose applying voltages to OLED anodes via reset lines during non-emission stages to establish known electrical conditions).
It therefore would have been obvious to one skilled in the art, prior to the effective filing date, to modify Chaji et al. by supplying the test signal over an anode reset line as taught by Zou et al., as doing so would provide a predictable and controlled electrical path for applying test and reset voltages to OLED anodes during diagnostic testing because Zou et al. emphasize in paragraphs [0062-0065] that reset lines and reset stages are specifically designed to establish stable and known anode voltage conditions for OLED pixel operation and evaluation, thereby improving measurement reliability and consistency in display testing applications.
Regarding claim 24, Chaji et al. are not understood to explicitly disclose varying a magnitude of the test signal based on a number of display pixels being measured.
Zou et al. disclose varying a magnitude of the test signal based on a number of display pixels being measured (see [0055-0057] wherein applying different voltage levels, bias conditions, and stress magnitudes during different operational and testing stages of OLED pixel circuits, including adjusting voltages based on circuit loading and pixel configuration see gate-source voltage adjustment stages and variable adjustment voltage terminal Vadjust, paragraphs [0099] & [0117]). Zou et al. emphasize adjusting voltage magnitudes to account for circuit conditions and the number of active elements to maintain stable operation).
It therefore would have been obvious to one skilled in the art, prior to the effective filing date, to modify Chaji et al. by varying the magnitude of the test signal based on the number of display pixels being measured as taught by Zou et al., as doing so would maintain measurement accuracy and prevent saturation or insufficient biasing when testing different pixel group sizes because Zou et al. emphasize in paragraphs [0112] & [0115] that voltage magnitude adjustment is used to accommodate varying circuit loading conditions, thereby improving robustness and reliability of electrical measurements in display testing systems.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2007/0080905 A1 to Takahara discloses in Fig. 1 an EL display apparatus includes EL elements 15 and driving transistors 11a placed like a matrix, a voltage gradation circuit 1271 for generating a program voltage signal, a current gradation circuit 164 for generating a program current signal, and a drive circuit means of applying a signal to the driving transistors 11a, having switches 151a and 151b for switching between the program voltage signal and the program current signal.
U.S. 2018/0204492 A1 to Kuo et al. disclose in Fig. 1, a display panel (102) comprising a set of gate lines, a set of data lines, a display region and a non-display region. A set of dummy pixels (P1-P5) is fixed at a region formed by corresponding gate lines and corresponding data lines intersecting one another. A part of the dummy pixels is connected to one another. A driver circuit (104) is coupled to the display panel, and provides gate driving voltage to the gate lines corresponding to the dummy pixels, and provides test data voltage to the corresponding data lines, such that the dummy pixels connected to one another to generate a charging rate test signal in response to the test data voltage.
U.S. 2008/0284760 A1 to Brunner discloses methods and apparatus for determining whether a malfunctioning pixel in a large area substrate, such as a liquid crystal display (LCD) panel, is due to the pixel itself or to the driver circuit for that pixel and for localizing any driver circuit defects are provided. In an effort to localize the driver circuit defects, test pads coupled to the input and/or output of certain driver circuits may be fabricated on the substrate. The voltage or charge of these test pads may be detected using any suitable sensing device, such as an electron beam, an electro-optical sensor, or an electrode in close proximity to the surface of the pixels and/or drivers capacitively coupled to the pixel or driver. For some embodiments, the defective driver circuits may be repaired in the same area as the test area or may be transported via conveyor or robot to a separate repair station.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
January 7, 2026
/HUY Q PHAN/ Supervisory Patent Examiner, Art Unit 2858