DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yuki (WO 2021/106939, using US 2022/0336682 as the English translation).
As to claim 1, Yuki teaches a semiconductor device (figs. 1, 6, and 8) comprising, as an electrostatic protection diode (13, [0027], a lateral NDMOS transistor (fig. 8) thyristorized by having a p-type dopant region (56) formed in a drain (54) thereof (fig. 6, [0068] and [0075].
As to claim 9, Yuki further teaches the lateral NDMOS transistor (fig. 8) includes:
a semiconductor layer (25/35) of a first conductivity type (n-type) having a main face (21) and including a device region ([0038]);
a base region (40) of a second conductivity type (p-type) formed in the device region, in a superficial part of the main face ([0055]);
a source region (41) of the first conductivity type (n-type) formed in a superficial part of the base region (40) at an interval inward from an edge part of the base region, the source region demarcating a channel region from the semiconductor layer ([0057] – [0059];
a base contact region (43) of the second conductivity type (p-type) formed in a superficial part of the base region, in a region different from the source region (see figs. 7 and 8), the base contact region having a dopant concentration more than a dopant concentration in the base region ([0060]);
a well region (50) of the first conductivity type (n-type) formed in the device region, in a superficial part of the main face at an interval from the base region, the well region demarcating a drift region from the base region ([0063] – [0066]);
a drain region (54) of the first conductivity type (n-type) formed in a superficial part of the well region ([0068]);
a dopant region (56) of the second conductivity type (p-type) formed in a superficial part of the well region and electrically connected to the drain region (fig. 6, [0075] – [0078]); and
a gate structure (71, [0101]) having: a gate insulation film (72) coating the channel region on the main face ([0102]); and a gate electrode (73) on the gate insulation film (72), the gate electrode facing the channel region and electrically connected to the source region and to the base contact region ([0103] – [0104]).
Claim(s) 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimada (JP 2017054864, see machine translation cited in IDS dated 5/7/24).
As to claim 10, Shimada teaches a semiconductor device (Fig. 1A) comprising: a first signal terminal (101c); a second signal terminal (101b); a ground terminal (101a); at least one first electrostatic protection diode (104c) configured to be connected, with a first polarity, between the first signal terminal (101c) and an internal node (103); at least one second electrostatic protection diode (104b) configured to be connected, with the first polarity, between the second signal terminal (101b) and the internal node (103); and at least one third electrostatic protection diode (104a) configured to be connected, with a second polarity reverse to the first polarity, between the internal node (103) and the ground terminal (101a, [0034] – [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada in view of Yuki.
As to claim 2, Shimada teaches a semiconductor device (fig. 1A) comprising: a first signal terminal (101c); a second signal terminal (101b); a ground terminal (101a); and a first electrostatic protection diode (104c), a second electrostatic protection diode (104b), and a third electrostatic protection diode (104a), an anode (123c) of the first electrostatic protection diode (104c) is connected to the first signal terminal (101c, see fig. 1B); an anode (123b) of the second electrostatic protection diode (104b) is connected to the second signal terminal (101b, fig. 1B); an anode (123a) of the third electrostatic protection diode (104a) is connected to the ground terminal (101a); and cathodes (122a/122b/122c) of the first, second, and third electrostatic protection diodes are connected together (to internal terminal 103, fig. 1B, [0030] – [0043]).
Shimada does not teach the first, second, and third electrostatic protection diodes are each a lateral NDMOS transistor thyristorized by having a p-type dopant region formed in a drain thereof.
However, Yuki teaches ESDs that are lateral NDMOS transistor thyristorized by having a p-type dopant region formed in a drain (see claims 1 and 9 rejection).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the thyristorized lateral NDMOS transistors of Yuki in the device of Shimada so as to improve electrostatic withstand capacity (Yuki, [0012]).
As to claim 3, Yuki further teaches the first, second, and third electrostatic protection diodes are each formed in a rectangular shape as seen in a plan view (see 28 of fig. 2), the first and second electrostatic protection diodes are disposed so as to share one side (see fig. 2),
Yuki does not teach the third electrostatic protection diode is disposed so as to be contiguous evenly with the first and second electrostatic protection diodes. However, Shimada teaches the third ESD. Although it’s exact location and size with respect to the other ESDs is not shown, using a similar diode as the third ESD would have been obvious so as to use similar sized devices that would reduce costs associated with using different sized devices. Finding the optimal location would also have been obvious so as to reduce footprint size and wire/conductor lengths. If that leads to a location contiguous to the other two ESDs, then that is the result of ordinary skill in the art and not innovation.
As to claim 4, Yuki further teaches the semiconductor device (fig. 1) is a CAN transceiver ([0023]), the first signal terminal is a high-side bus input/output terminal, and the second signal terminal is a low-side bus input/output terminal ([0027] – [0029]).
As to claim 5, Yuki further teaches a high-side output circuit (3) configured to switch between a conducting state and a cut-off state a path between the first signal terminal and a supply terminal; and a low-side output circuit (4) configured to switch between a conducting state and a cut-off state a path between the second signal terminal and ground terminal ([0027] – [0029]).
As to claim 6, Yuki further teaches the high-side output circuit (3) includes a first reverse current prevention diode (13) configured to prevent a reverse current from the first signal terminal to the supply terminal ([0027]).
As to claim 7, Yuki further teaches the low-side output circuit (4) includes a second reverse current prevention diode (17) configured to prevent a reverse current from the ground terminal to the second signal terminal ([0029]).
As to claim 8, Yuki further teaches the low-side output circuit shares the second electrostatic protection diode as the second reverse current prevention diode configured to prevent a reverse current from the ground terminal to the second signal terminal ([0027] – [0029]).
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
8/20/26
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