DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, Group 1-A including claims 1-4, 6, 7, 9-16 and 20 in the reply filed on 06/08/2026 is acknowledged. The traversal is on the ground(s) that the Office has failed to demonstrate that a serious search and/or examination burden would be placed on the Office if the restriction were not required.
This is not found persuasive because there is a burden of search and the burden is shown by one of the following: a) each invention can be shown to have formed a separate subject for inventive effort even though the two inventions are classified together. Separate status in the art may be shown by citing patents which are evidence of such separate status, and also of a separate field of search, b) where it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different CPC groups or electronic resources or employing different search queries). The indicated different field of search must in fact be pertinent to the type of subject matter covered by the claims.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Lee et al. US 2022/0173120 in view of Kim et al. US 2020/0350249.
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Lee et al. US 2022/0173120
Regarding claim 1, Lee et al. in Fig. 12L and [0028]-[0142] discloses a semiconductor device, comprising:
a first semiconductor structure PERI including a substrate 201 and circuit devices 220 on the substrate 201 [0028]; and
a second semiconductor structure CELL [0028] on the first semiconductor structure PERI, wherein the second semiconductor structure includes, a plate layer 102 [0033] having a first region and a second region,
gate electrodes 130 [0033] stacked and spaced apart from each other in a first direction on the first region, the gate electrodes 130 extending by different lengths in a second direction on the second region, the gate electrodes each including a pad region 130P [0045] having an upper surface exposed upwardly in the second region and a stack region other than the pad region,
the gate electrodes 130 including a first gate electrode 130U [0043] and a second gate electrode 130U-130L [0043] below the first gate electrode, interlayer insulating layers120 [0033] alternately stacked with the gate electrodes 130,
channel structures CH [0033] penetrating through the gate electrodes 130, the channel structures CH extending in the first direction, the channel structures CH each including a channel layer 140 [0037],
a gate contact plug 170 [0033] penetrating through the pad region 130P, Fig. 3 of the first gate electrode 130 and the stack region of the second gate electrode 130U-130L, the gate contact plug 170 electrically connected to the first gate electrode 130, the gate contact plug 170 spaced apart from the second gate electrode 130U-130L.
Lee et al. does not expressly disclose a first contact plug insulating layer on the interlayer insulating layers in the pad region of the first gate electrode, the first contact plug insulating layer surrounding the gate contact plug, the first contact plug insulating layer vertically overlapping the first gate electrode, and second contact plug insulating layers alternating with the interlayer insulating layers below the pad region of the first gate electrode, the second contact plug insulating layers surrounding the gate contact plug.
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Kim et al. US 2020/0350249
However, Kim et al. in Fig. 11A (annotated above) and [0072]-[0085] teach a memory device of an embodiment, a first contact plug insulating layer 140 on the interlayer insulating layers 112 in the pad region of the first gate electrode 160, the first contact plug insulating layer surrounding the gate contact plug 150, the first contact plug insulating layer 140 vertically overlapping the first gate electrode 160, and second contact plug insulating layers 140 alternating with the interlayer insulating layers 112 below the pad region of the first gate electrode 160, the second contact plug insulating layers 140 surrounding the gate contact plug 150. Kim et al. further teach in [0085] since the bottom surface of the contact plug 150 connected to each of the first conductive patterns 160A functioning as gate electrode layers is connected directly to the peripheral circuit element 105, there is an advantage in that formation of an additional connecting member is not necessary.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim et al. in the semiconductor memory device of Lee et al. for the purpose of improving the process of forming the device.
Regarding claim 2, Lee et al. in view of Kim et al. teach the semiconductor device of claim 1. Kim et al. in Fig. 11A and [0072]-[0085] teach wherein the first gate electrode 160 covers a side surface 160A and an upper surface 160B of the first contact plug insulating layer 140.
Regarding claim 3, Lee et al. in view of Kim et al. teach the semiconductor device of claim 1. Kim et al. in Fig. 11A and [0072]-[0085] teach wherein the first gate electrode 160B is in contact with the gate contact plug 150 on an upper surface of the first contact plug insulating layer 140.
Regarding claim 9, Lee et al. in view of Kim et al. teach the semiconductor device of claim 1, but do not teach wherein the first contact plug insulating layer 140 has a first thickness, and wherein each of the second contact plug insulating layers 140 has a second thickness equal to the first thickness.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 10, Lee et al. in view of Kim et al. teach the semiconductor device of claim 1, but do not teach wherein each of the gate electrodes 160 has a first gate thickness in the stack region and a second gate thickness greater than the first gate thickness in the pad region.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Kim et al. as applied to claim 1 above, and further in view of Choi US 2022/0399365.
Regarding claim 11, Lee et al. in view of Kim et al. teach the semiconductor device of claim 1 but not teach wherein the gate contact plug 150 includes a vertical extension portion extending in the first direction and a horizontal extension portion extending from the vertical extension portion in the second direction perpendicular to the first direction and in contact with the pad region wherein a first length of the vertical extension portion in the second direction is smaller than a second length of the first contact plug insulating layer in the second direction.
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Choi US 2022/0399365
Choi in Figs. 3B-4 and [0013]-[0071] teach a semiconductor memory device including a gate contact plug 181A with a vertical extension portion extending in the first direction and a horizontal extension portion extending from the vertical extension portion in the second direction perpendicular to the first direction and in contact with the pad region. Although Choi shows a first and second length of the gate contact plug, Choi does not expressly teach wherein a first length of the vertical extension portion in the second direction is smaller than a second length of the first contact plug insulating layer in the second direction.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 12, Lee et al. in view of Kim et al. and further in view of Choi teach the semiconductor device of claim 11, but do not teach wherein the second length is equal to a third length of the second contact plug insulating layers in the second direction.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Allowable Subject Matter
Claims 4, 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims,
4. The semiconductor device of claim 1, further comprising: a sacrificial insulating pattern covering a portion of the pad region of the first gate electrode, at least a portion of a side surface of the first gate electrode, and at least a portion of a side surface of the interlayer insulating layers, the sacrificial insulating pattern including boron (B).
6. The semiconductor device of claim 1, wherein the first gate electrode includes a first portion covering a side surface and an upper surface of the first contact plug insulating layer and a second portion between an upper surface of the first contact plug insulating layer and a lower surface of the first contact plug insulating layer, the first portion being at a level higher than a level of the upper surface of the first contact plug insulating layer.
7. The semiconductor device of claim 6, wherein a thickness of the first portion is equal to or smaller than a thickness of the second portion.
Claims 13-16 and 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record neither anticipates nor renders obvious in the context of the claims, a sacrificial insulating pattern covering a portion of the pad region of the first gate electrode, at least a portion of a side surface of the first gate electrode, and at least a portion of a side surface of the interlayer insulating layers, the sacrificial insulating pattern including boron (B).
Claims 14-16 directly or indirectly depend from claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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