DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 11,632,230 B2), in view of Zhao (US 8,970,270 B2).
Regarding Claim 1 and equivalent method Claim 13, Li et al. discloses in Figure 3A a clock signal duty ratio correction circuit comprising:
a period indication signal generation circuit configured to generate a period indication signal according to a clock signal, wherein a period indication level of the period indication signal is correlated with a period time of the clock signal (using 310);
a first ramp signal generation circuit configured to generate a first ramp signal according to the clock signal (using 320, which outputs signal Vramp); and
a clock signal regeneration circuit configured to generate a clock regeneration signal according to a triggering of the clock signal, such that the clock regeneration signal has a target duty ratio (circuitry which generates DTC_Code; wherein Figure 6 further illustrates DTC_Code, as outputted from 650, is based in part on Vout);
wherein a slope of the first ramp signal is correlated with the target duty ratio (wherein signal Vramp slope is based in part on the adjustment across capacitor C4);
but does not explicitly teach the clock regeneration signal is according to a comparison of the first ramp signal with the period indication level.
Zhao teaches in Figure 1 and 2 the clock regeneration signal is according to a comparison of the first ramp signal with the period indication level (Figure 1: 104; Figure 2: 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the comparison teachings of Zhao within the feedback control loop of Li et al. for the purpose of generating a “square wave signal with the high-precision duty cycle” for better signal control. Zhao, Col. 2, lines 38-39.
Regarding Claims 2 and 14, Li et al. and Zhao, as a whole, teach all the limitations of the present invention, wherein Li et al. further teaches the clock signal duty ratio correction circuit,
wherein the first ramp signal generation circuit charges a first capacitor with a first current to generate the first ramp signal (Figures 3A: controlled adjustment of capacitor C4),
wherein the first current is inversely correlated with the target duty ratio, or a first capacitance of the first capacitor is positively correlated with the target duty ratio (where the current across capacitor C4 is correlated with the controlled adjustment using DTC_Code).
Allowable Subject Matter
Claims 3-12 and 15-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art does not disclose, teach or suggest the clock signal duty ratio correction circuit, further comprising a frequency divider circuit coupled with the period indication signal generation circuit, configured to divide a frequency of the clock signal and generate a frequency divided clock signal;
in combination with all the other claimed limitations.
Claims 4-10 are objected to for depending from Claim 3.
Regarding Claim 11, the prior art does not disclose, teach or suggest the clock signal duty ratio correction circuit, wherein the clock signal duty ratio correction circuit is applied to plural operation circuits coupled to one another in a daisy chain topology, wherein each of the plural operation circuits generates a corresponding output clock signal according to a corresponding input clock signal, wherein the corresponding output clock signal serves as the corresponding input clock signal for an adjacent next operation circuit of the plural operation circuits; wherein each of the plural operation circuits includes the clock signal duty ratio correction circuit, wherein the clock signal duty ratio correction circuit is configured to generate the clock regeneration signal according to the input clock signal, and to generate the output clock signal according to the clock regeneration signal;
in combination with all the other claimed limitations.
Claim 12 is objected to for depending from Claim 11.
Regarding Claim 15, the prior art does not disclose, teach or suggest the duty ratio correction method 14, further comprising: dividing the clock signal to generate a frequency divided clock signal;
in combination with all the other claimed limitations.
Claims 16-22 are objected to for depending from Claim 15.
Regarding Claim 23, the prior art does not disclose, teach or suggest the duty ratio correction method, wherein the duty ratio correction method is utilized for a clock signal duty ratio correction circuit which is applied to plural operation circuits coupled to one another in a daisy chain topology, wherein each of the plural operation circuits generates a corresponding output clock signal according to a corresponding input clock signal, wherein the corresponding output clock signal serves as the corresponding input clock signal for an adjacent next operation circuit of the plural operation circuits; wherein each of the plural operation circuits includes the clock signal duty ratio correction circuit, wherein the clock signal duty ratio correction circuit is configured to generate the clock regeneration signal according to the input clock signal, and to generate the output clock signal according to the clock regeneration signal;
in combination with all the other claimed limitations.
Claim 24 is objected to for depending from Claim 23.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIANA J. CHENG/Primary Examiner, Art Unit 2849