DETAILED ACTION
This is in response to the application filed on May 7, 2024 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 9, and 17 are in independent form. Note that there are two claims numbered as claim 6.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/26/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not).
Applicant’s have submitted a claim set with two claims labeled as claim 6. The examiner will address these claims as “the first claim 6” and “the second claim 6” in this Office Action.
Specification
The disclosure is objected to because of the following informalities: throughout the specification are citations of one of multiple items using the phrase “a said” following a description of a plurality of the items (“a said first set of configuration-bit values,” “a said second set of configuration-bit values,” “a said data set,” “a said configuration bit dataset,” “a said input bus”). However, for example, referring to “a said first set of configuration-bit values” when “a first set of configuration-bit values” has not been previously disclosed is improper. As above, this applies to many different items in Applicant’s specification. The examiner suggests amendments such as “a first of said set of configuration-bit values,” “a second of said set of configuration-bit values,” “one of said plurality of data sets,” “one of said configuration bit datasets,” “a first of said input buses,” or the like.
Appropriate correction is required.
The disclosure is objected to because of the following informalities: Applicant’s specification (page 27 lines 20-22) states “a plurality of input buses 669, each of said input buses comprising an identical plurality of wires; and an output bus 668 comprising a plurality of wires identical to a said input bus.” This statement is misleading because if each bus was comprised of an identical plurality of wires, then each bus would be the same bus made up of the same wires. Similarly, the output bus would be the same bus as the input bus. The examiner believes that Applicant is attempting to describe “a plurality of input buses 669, each of said input buses comprising an identical number of wires; and an output bus 668 comprising an identical number of wires to a said input bus.”
Appropriate correction is required.
The disclosure is objected to because of the following informalities: Applicant’s specification (page 27 lines 16-18 and 22-24) states “Logic tile 650 comprising: a configurable switch 652 having a configuration bit or a control signal to facilitate all the wires of a plurality of bus interconnects 651 to individually couple to an input bus 669 of a multiplexer 653 coupled to the bus 668” and “a plurality of configuration bits, a said configuration bit facilitating all the wires of a said input bus 669 to individually couple to all the wires of said output bus 668 by configuring the said configuration bit.” The examiner believes that Applicant is attempting to describe “Logic tile 650 comprising: a configurable switch 652 having a configuration bit or a control signal to facilitate each of the wires of a plurality of bus interconnects 651 to respectively couple to an input bus 669 of a multiplexer 653 coupled to the bus 668” and “a plurality of configuration bits, a said configuration bit facilitating each of the wires of one of es 669 to respectively couple to all the wires of said output bus 668 by configuring the said configuration bit.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a said input port" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 1 describes ‘a plurality of input ports.’ Therefore, recitation of ‘a said input port’ causes an antecedent basis issue. The examiner recommends amending claim 1 to state ‘a first of said plurality of input ports’ or ‘ one of said plurality of input ports’ or the like. Claims 2 – 8 inherit this rejection based on their dependencies.
Claim 1 recites the limitation "to configure the switches" in line 6. There is insufficient antecedent basis for this limitation in the claim. Claim 1 describes ‘a configurable switch.’ Therefore, recitation of ‘the switches’ causes an antecedent basis issue. The examiner recommends amending claim 1 to state ‘to configure the switch’ or the like. Claims 2 – 8 inherit this rejection based on their dependencies.
Claim 2 recites the limitation “to couple the output to a said plurality of inputs as specified in the bit-code” in line4 - 5. There is insufficient antecedent basis for this limitation in the claim. As above, claim 1 describes ‘a plurality of input ports.’ Therefore, recitation of ‘a said plurality of inputs’ causes an antecedent basis issue. The examiner recommends amending claim 2 to state “to couple the output to one of said plurality of input ports as specified in the bit-code” or “to couple the output to first of said plurality of input ports as specified in the bit-code” or the like. Claims 3 – 5 inherit this rejection based on their dependencies.
The first claim 6 recites the limitation “to couple the output to a said plurality of inputs” in line 6. There is insufficient antecedent basis for this limitation in the claim. As above, claim 1 describes ‘a plurality of input ports.’ Therefore, recitation of ‘a said plurality of inputs’ causes an antecedent basis issue. The examiner recommends amending the first claim 6 to state “to couple the output to one of said plurality of input ports” or “to couple the output to first of said plurality of input ports” or the like. Claims 3 – 5 inherit this rejection based on their dependencies.
Claim 8 recites the limitations “in a first period of a clock-cycle” and “in a second period of the clock-cycle.” However, “a period” is commonly used synonymously with a “clock-cycle” in the art. This makes Applicant’s claim 8 confusing. The examiner recommends amending claim 8 to state “in a first portion of a clock-cycle” and “in a second portion of the clock-cycle.”
Claim 9 recites the limitation "each input bus comprising an identical plurality of input bus wires" in line. Applicant’s wording of "each input bus comprising an identical plurality of input bus wires" actually describes a single bus. In other words, if multiple buses comprise “an identical plurality of input bus wires,” then the multiple buses are in fact a single bus. The examiner believes that Applicant is attempting to describe each input bus comprising an identical number of input bus wires. The examiner recommends amending claim 9 to state ‘each input bus comprising an identical number of input bus wires’ or the like. Similarly, claim 9 later refers to an input port and states “the input port comprising said identical plurality of input bus wires” in lines 4 – 5. The examiner recommends amending claim 9 to state “the input port comprising said identical number of input bus wires.” Claims 10 – 16 inherit this rejection based on their dependencies.
Claim 9 recites the limitation "a said plurality of input bus wires" in line 6. There is insufficient antecedent basis for this limitation in the claim. Independent claim 9 describes ‘an identical plurality of input bus wires.’ Therefore, recitation of ‘a said plurality of input bus wires’ causes an antecedent basis issue. The examiner recommends amending claim 9 to state “ one of said plurality of input bus wires” or “a first of said plurality of input bus wires” or the like. Claims 10 – 16 inherit this rejection based on their dependencies.
Claim 9 recites the limitation "a said plurality of input buses" in line 9. There is insufficient antecedent basis for this limitation in the claim. Independent claim 9 describes ‘a plurality of configurable input buses.’ Therefore, recitation of ‘a said plurality of input buses’ causes an antecedent basis issue. The examiner recommends amending claim 9 to state “ one of said plurality of input buses” or “a first of said plurality of input buses” or the like. Claims 10 – 16 inherit this rejection based on their dependencies.
Claim 10 recites the limitation "a said byte configurable switch" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim 10 describes ‘a plurality of byte configurable switches.’ Therefore, recitation of ‘a said byte configurable switch’ causes an antecedent basis issue. The examiner recommends amending claim 10 to state “ first of said byte configurable switches” or “ one of said byte configurable switches” or “ each of said byte configurable switches” or the like. Claims 14 – 16 inherit this rejection based on their dependencies.
Claim 13 recites the limitation " each of said first and second tile buses comprising an identical plurality of tile bus wires" in line - 4. Applicant’s wording of "each of said first and second tile buses comprising an identical plurality of tile bus wires" actually describes a single bus. In other words, if multiple buses comprise “an identical plurality of tile bus wires,” then the multiple buses are in fact a single bus. The examiner believes that Applicant is attempting to describe each input bus comprising an identical number of input bus wires. The examiner recommends amending claim 13 to state ‘each of said first and second tile buses comprising an identical number of tile bus wires’ or the like.
Claim 13 recites the limitation “a said register comprising” in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 13 describes ‘a first and second register banks.’ Therefore, recitation of ‘a said register’ causes an antecedent basis issue. The examiner recommends amending claim 13 to state “a first and second register banks, each register of the first and second register banks comprising” or “ one register of the first and second register banks comprising” or the like.
Claim 14 recites the limitation “the configuration memory elements as specified by the bit-pattern” in line 4. There is insufficient antecedent basis for this limitation in the claim. The examiner recommends amending claim 14 to state “ a bit-pattern” or the like.
Claim 17 recites the limitation "a said byte configurable switch" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim 17 describes ‘a plurality of byte configurable switches.’ Therefore, recitation of ‘a said byte configurable switch’ causes an antecedent basis issue. The examiner recommends amending claim 17 to state “ first of said byte configurable switches” or “ one of said byte configurable switches” or “ each of said byte configurable switches” or the like. Claims 18 – 20 inherit this rejection based on their dependencies.
Claim 17 recites the limitation "a said bit configurable switch" in line 6. There is insufficient antecedent basis for this limitation in the claim. Claim 17 describes ‘a plurality of bit configurable switches.’ Therefore, recitation of ‘a said bit configurable switch’ causes an antecedent basis issue. The examiner recommends amending claim 17 to state “ first of said bit configurable switches” or “ one of said bit configurable switches” or “ each of said bit configurable switches” or the like. Claims 18 – 20 inherit this rejection based on their dependencies.
Claim Objections
Claims 10 and 14 – 16 are objected to because of the following informalities: Claim 10 recites the limitation "a plurality of bit-level wires, and a plurality of byte-level wire buses, each byte-level wire bus comprising a plurality of identical bit-level wires" in lines 2 - 3. It is unclear whether the “plurality of identical bit-level wires” of each byte-level wire bus are the same as the earlier claimed “plurality of bit-level wires.” The examiner recommends amending claim 10 to state "a first plurality of bit-level wires, and a plurality of byte-level wire buses, each byte-level wire bus comprising a plurality of identical second bit-level wires" or the like. Claims 14 – 16 inherit this objection based on their dependencies. Appropriate correction is required.
Claims 10 and 14 – 16 are objected to because of the following informalities: Claim 10 recites the limitation "a configurable memory element to couple two byte-level wire buses individually" in lines 4 - 5. As above in regards to the specification, Applicant’s use of the term ‘individually’ appears to refer to coupling each wire bus ‘respectively.’ The examiner recommends amending claim 10 to state "a configurable memory element to couple two byte-level wire buses respectively" or the like. Claims 14 – 16 inherit this objection based on their dependencies. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: Claim 13 recites the limitations "a configurable first and second tile buses" in line 3 and “a first and second register banks” in line 5. For clarity, the examiner recommends amending claim 13 to state " configurable tile buses" in line 3 and “. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: Claim 13 recites the limitations "a byte configurable switch capable of coupling two equal pluralities of wires individually" in lines 9 – 10 and “to configure a byte configurable switch to couple two sets of wires individually” in lines 12 - 13. As above in regards to the specification, Applicant’s use of the term ‘individually’ appears to refer to coupling each wire bus ‘respectively.’ The examiner recommends amending claim 13 to state "a byte configurable switch capable of coupling two equal pluralities of wires respectively" in lines 9 – 10 and “to configure a byte configurable switch to couple two sets of wires respectively.” Appropriate correction is required.
Claims 17 – 20 are objected to because of the following informalities: Claim 17 recites the limitation “a plurality of buses, each bus comprising a plurality of identical number of wires; and a plurality of wires" in lines 2 - 3. It is unclear whether the “plurality of identical number of wires” of each bus are the same as the later claimed “plurality of wires.” The examiner recommends amending claim 17 to state "a plurality of buses, each bus comprising a first plurality of identical number of wires, and a second plurality of wires" or the like. Claims 18 – 20 inherit this objection based on their dependencies. Appropriate correction is required.
Claims 17 – 20 are objected to because of the following informalities: Claim 17 recites the limitation "coupling a first bus plurality of wires individually to a second bus plurality of wires” in line 5. For improved clarity and grammar, the examiner suggests amending claim 17 to state "coupling a of a first bus respectively to a of a second bus” or the like. Claims 18 – 20 inherit this objection based on their dependencies. Appropriate correction is requited.
Claims 19 – 20 are objected to because of the following informalities: Claim 19 recites the limitations “to program the plurality of bit configurable memory elements and portion of the byte configurable memory elements” in lines 3-4 and “to generate dynamically program a second portion” in lines 5-6. For improved clarity and grammar, the examiner suggests amending claim 19 to state “to program the plurality of bit configurable memory elements and a portion of the byte configurable memory elements” in lines 3-4 and “to
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: ‘a configurable means of coupling the output port to the plurality of input ports’ in claim 1 and ‘a configurable means of coupling a said plurality of input bus wires to the input port’ in claim 9. Also, claims 13 and 14 provide more structure defining the ‘means.’
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 5, and “the first claim 6” are rejected under 35 U.S.C. 103 as being unpatentable over Boesch et al., European Patent Application EP 3,346,426 B1 (hereinafter referred to as Boesch) in view of Liu, U.S. Patent Application 2009/0206876 (hereinafter referred to as Liu).
Referring to claim 1, Boesch discloses “A configurable data router in an interconnect structure” (Fig. 5A), “comprising: an output port comprising a wire to transmit data” (Fig. 5A output port 516 and NA..D output path); “and a plurality of input ports, each of the input ports comprising a wire to receive data” (Fig. 5A input ports 504 with A, B, C, and D inputs); “and a configurable means of coupling the output port to the plurality of input ports comprising: a configurable switch to couple the output port to a said input port” (Fig. 5A data switch 506), “and a configurable signal generation unit to configure the switch[es]” (Fig. 5A config logic 510 and [0195] “based on the selection mechanism 508, the input data from one of input ports A, B, C, D is passed through the data switch 506 to an output of the data switch 506”); “and a programmable method to program the signal generation unit” (Fig. 5A msg/cmd logic 512 and [0196] “the stream switch configuration logic 510 may also take direction from message/command logic 512”).
As above regarding 35 USC 112, there is no antecedent basis for “the switches.” However, in an effort to advance prosecution, the examiner will treat claim 1 as if there is antecedent basis for “the switches.” Boesch does not appear to explicitly disclose configuring “the switches.”
However, Liu discloses another data routing structure including “a configurable signal generation unit to configure the switches” (Fig. 4 programmable logic sending data for an output permutation of a network of switches).
Boesch and Liu are analogous art because they are from the same field of endeavor, which is configurable data routing structures.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Boesch and Liu before him or her, to modify the teachings of Boesch to include the teachings of Liu so that the configurable signal generation unit configures multiple switches.
The motivation for doing so would have been to provide a means for simultaneously controlling a network of switches to dynamically route input signals for desired processing (as taught by Liu at [0039]).
Therefore, it would have been obvious to combine Liu with Boesch to obtain the invention as specified in the instant claim.
As per claim 2, Boesch discloses “the programmable method further comprising the signal generation unit to: receive a bit-code; and decode the bit-code and generate a plurality of switch control signals to couple the output to a said plurality of inputs as specified in the bit-code” ([0196] "The selection mechanism 508 is directed according to stream switch configuration logic 510," logic 510 determines and forms an appropriate selection signal that is passed to the data switch,” and [0198] "the message/command logic 512 is arranged to provide direction or particular actionable information to the stream switch configuration logic 510").
As per claim 3, Boesch discloses “the bit-code is generated by one of: a control unit of a microprocessor, and a programmable logic unit” ([0138] CAF control registers 402 accessible by host processor, DSP, applications processor, or another processor and used to control the framework. Also [0166] stream links configured by control registers and [0196] “stream switch 510 may take direction from CAF control registers, from a DSP of the DSP cluster 122 (FIG. 3), from the application processor 128, or from some other control device. In addition, the stream switch configuration logic 510 may
also take direction from message/command logic 512”).
As per claim 5, Boesch discloses “the configurable signal generation unit further comprises a plurality of configurable memory elements, each memory element comprising at least two memory states to activate or deactivate a switch” ([0138] CAF control registers 402 accessible by host processor, DSP, applications processor, or another processor and used to control the framework. Also [0166] stream links configured by control registers and [0196] “stream switch 510 may take direction from CAF control registers, from a DSP of the DSP cluster 122 (FIG. 3), from the application processor 128, or from some other control device).
As per the first claim 6, Boesch discloses “the programmable method further comprising the signal generation unit to: receive a bit-code; and decode the bit-code” ([0196] "The selection mechanism 508 is directed according to stream switch configuration logic 510," logic 510 determines and forms an appropriate selection signal that is passed to the data switch,” and [0198] "the message/command logic 512 is arranged to provide direction or particular actionable information to the stream switch configuration logic 510"), “and program the plurality of configurable memory elements in the signal generation unit as specified in the bit-code” ([0138] CAF control registers 402 accessible by host processor, DSP, applications processor, or another processor and used to control the framework); “and generate the plurality of switch-control signals to couple the output to a said plurality of inputs” (Fig. 5A and [0196] "The selection mechanism 508 is directed according to stream switch configuration logic 510," logic 510 determines and forms an appropriate selection signal that is passed to the data switch”).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Boesch in view of Farabet et al., U.S. Patent Application 2012/0303932 (hereinafter referred to as Farabet), further in view of Liu.
Referring to claim 9, Boesch discloses “A configurable interconnect structure” (Fig. 5A), “comprising: a plurality of configurable input buses, each input bus comprising an identical plurality of input bus wires” (Fig. 5A and [0183] “The stream switch 500 includes a user-selectable, design-time configurable first number of stream link input ports 504”); “and an input port of a configurable” stream link 502, “the input port comprising said identical plurality of input bus wires” (Fig. 5 stream links 502/502a/502b each connect A,B,C,D), “and said” stream link “further comprising a first wire and a second wire” (Fig. 5 inputs to data switch 506 and output of data switch 506); “and a configurable means of coupling” “said first wire to said second wire, the configurable means further comprising a configurable signal generation unit” (Fig. 5A data switch 506 with config logic 510 and [0195] “based on the selection mechanism 508, the input data from one of input ports A, B, C, D is passed through the data switch 506 to an output of the data switch 506”); “and a programmable method to couple and decouple” “the first and second wires inside the" stream link (Fig. 5A msg/cmd logic 512 and [0196] “the stream switch configuration logic 510 may also take direction from message/command logic 512” and [0195] “based on the selection mechanism 508, the input data from one of input ports A, B, C, D is passed through the data switch 506 to an output of the data switch 506”).
Boesch describes a stream switch 500 in Fig. 5A. However, this stream switch 500 is part of a configurable accelerator framework (CAF) 400 (Fig. 4), which is part of a System-on-chip 110 (Fig. 3) including DSP clusters 138.
Boesch does not appear to explicitly disclose the “configurable interconnect structure” being part “of a configurable logic tile.”
However, Farabet discloses another reconfigurable system including numerous processing tiles 110 and a controller or control unit 120 (Fig. 1). Farabet discloses the controller 120 uses the runtime configuration bus 160 to reconfigure the processing tiles 110 and the memory access module 130 at runtime ([0021]).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Farabet with Boesch so that the interconnect structure is part “of a configurable logic tile.”
Boesch and Farabet are analogous art because they are from the same field of endeavor, which is configurable data routing structures.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Boesch and Farabet before him or her, to modify the teachings of Boesch to include the teachings of Farabet so that the configurable interconnect structure is part of a configurable logic tile.
The motivation for doing so would have been to provide a means for improving throughput (as taught by Farabet at [0022]).
Neither Boesch nor Farabet appears to explicitly disclose “a configurable means of coupling a said plurality of input bus wires to the input port” and “a programmable method to couple and decouple a said plurality of input buses to the input port.”
However, Liu discloses another data routing structure including “a configurable means of coupling a said plurality of input bus wires to the input port” and a “method to couple and decouple a said plurality of input buses to the input port” ([0040] "In one embodiment, the permutation network of switches 408 may be configured to dynamically map a selected subset of the relatively large number of input signals 406 from the plurality of fixed logic circuits 404 to the relatively smaller number (e.g., 8) of input signals 422 to the programmable logic core 402. It is understood that in various embodiments, not all of the input signals 422 to the programmable logic core 402 may be used, and therefore, in some of these embodiments the permutation network of switches 408 may be configured to map the unused portion of the input signals 422 to a fixed or known value (e.g., "high", "low", etc.).").
Boesch, Farabet, and Liu are analogous art because they are from the same field of endeavor, which is configurable data routing structures.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Boesch, Farabet, and Liu before him or her, to modify the teachings of Boesch and Farabet to include the teachings of Liu so that the configurable means includes means for coupling a said plurality of input bus wires to the input port and a programmable method to couple and decouple a said plurality of input buses to the input port.
The motivation for doing so would have been to provide a means for simultaneously controlling a network of switches to dynamically route input signals for desired processing (as taught by Liu at [0039]).
Therefore, it would have been obvious to combine Liu with Boesch to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 4, “second claim 6,” 7, 8, and 10 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17 – 20 contain allowable subject matter.
The following is an examiner’s statement of reasons for indicating allowable subject matter: The primary reason for the indication of allowable subject matter of the claims in this application is the inclusion of the specific details of a configurable interconnect structure with both buses and wires, a plurality of byte configurable switches to couple each line of a bus to each line of another bus, respectively, a plurality of bit configurable switches to couple a first wire to a second wire, a configuration circuit to configure the bit and byte configurable switches, and programming the bit and byte configurable switches to configure the interconnect structure, as are now included in all of the independent claims, in combination with the other elements recited, which is not found in the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patents 6211697, 6242945, 6693452, 6798239, 7696782, and 9430239 teach programmable pipelines using switches.
U.S. Patent 6693452 teaches a programmable unit with tiles and providing selective connectivity between inputs and outputs.
U.S. Patents 6622195, 6654841, 7809866, and 9405717 teach input port coupling and decoupling.
European Patent Application EP 3346426 B1 teaches a bus switching circuit with a path selecting circuit, control circuit, and encoding circuit.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184