DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20260123395 A1 – hereinafter Cheng).
Regarding independent claim 1, Cheng teaches:
A semiconductor device (100 – Fig. 1A – [0034] – “semiconductor
device 100”), comprising:
front end of line (FEOL) devices (120 – Fig. 1A – [0035] – “FEOL/MOL
structure 120”) arranged in a FEOL layer ([0036] – “the FEOL layer comprises FET devices (such as FinFET devices, planar MOSFET device, etc.), bipolar transistors, diodes, capacitors, inductors, resistors, isolation devices, etc., which are formed in or on the active surface of the semiconductor substrate 110”) defining a frontside (Fig. 11 – [0020] – “FIG. 11 is a cross-sectional schematic side view of a semiconductor device comprising air gap spacers that are integrally formed within a FEOL/MOL structure of the semiconductor device” – hereinafter ‘F-Front’) and a backside (if a surface has a frontside, then it must have a backside – hereinafter ‘Back’) opposite the frontside (F-Front);
a single composition dielectric material (236 – Fig. 12 – [0076] – “PMD layer 236 may be formed with any suitable insulating/dielectric materials such as, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, porous dielectrics, or organic dielectrics including porous organic dielectrics, etc. The PMD layer 236 may be formed using known deposition techniques, such as, for example, ALD, CVD, PECVD, spin on deposition, or PVD, followed by a standard planarization process (e.g., CMP)” – this describes a single composition dielectric material) covering the FEOL devices (120 – {[0073] – “FIG. 11 further illustrates a first interconnect level of a BEOL structure formed over the FEOL/MOL layers”}, {[0074] – “FIG. 12 is cross-sectional schematic view of the semiconductor device 200 at an intermediate stage of fabrication” – Fig. 12 shows this) and disposed in shallow trench isolation regions (236-1 – Fig. 12 – [0077] – “after patterning the PMD layer 236 to form contact openings 236-1 between the gate structures 230-1, 230-2, 230-3 of the vertical transistor structures M1, M2, M3 down to the source/drain regions 225. The contact openings 236-1 can be formed using known etching techniques and etching chemistries to etch the material of the PMD layer 236 selective to the insulating material of the capping layers 232 and sidewall spacers 234” – this describes shallow trench isolation regions) between the FEOL devices (120); and
the single composition dielectric material (236) having voids ([0070] – “air gap spacers 262” – these must be formed in voids, hereinafter ‘V’) disposed therein that provide airgaps (262 – Fig. 11 – [0070] – “air gap spacers 262”) between the FEOL devices (120).
Regarding claim 2, Cheng teaches claim 1 from which claim 2 depends. Cheng further teaches
wherein the single composition dielectric material (236) fills the
shallow trench isolation regions (236-1) and includes a backside airgap (262) within the shallow trench isolation regions (236-1).
Regarding claim 3, Cheng teaches claim 2 from which claim 3 depends. Cheng further teaches
wherein the backside airgap (262) extends under a gate conductor
(230-1 – [0067] – “gate structures 230-1”) on the backside.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sabuncuoglo et al. (US 20120013022 A1 – hereinafter Sabuncuoglu).
Regarding independent claim 10, Sabuncuoglu teaches:
A semiconductor device ([0002] – “disclosure relates to the field of
forming interconnect structures such as Through Silicon Vias (TSV) to be used in the stacking of semiconductor devices” – hereinafter ‘Device’), comprising:
front end of line (FEOL) devices ([0059] – “the substrate (1) is a semiconductor
wafer or die comprising a back-end-of-line (BEOL) and a front-end-of-line (FEOL), wherein the first main surface (S1) is the backside of the wafer or die, i.e. the side which is most remote from the BEOL (13)”) arranged in a FEOL layer ([0059] – “end-of-line (FEOL), wherein the first main surface (S1) is the backside of the wafer or die, i.e. the side which is most remote from the BEOL (13)” – hereinafter ‘FEOL’) defining a
frontside (S2 – Fig. 4a – [0060] – “second main surface (S2) opposite the first main surface (S1)”) and a backside (S1 – Fig. 4a – [0059] – “end-of-line (FEOL), wherein the first main surface (S1) is the backside of the wafer or die, i.e. the side which is most remote from the BEOL (13)”) opposite the frontside (S1);
a single composition dielectric material (24 – Fig. 4a – {[0063] – “The dielectric liner material (24) can be patterned so as to free at least the location of the substrate pillar structure (22), removing, e.g. etching away, the substrate pillar structure (22), e.g. silicon substrate or silicon substrate further comprising ILD layer, thus leaving a pillar vacancy (23) “}, {[0068] – “layer is an inter level dielectric (ILD) layer, which is a layer present in a back-end-of-line (BEOL) interconnect structure; having a function of electrically isolating the metal interconnects in the BEOL from for example the front-end-of-line (FEOL)”}) covering the FEOL devices and disposed in shallow trench isolation regions (R1 – Fig. 4b – [0050] – “trench-like structure (R1)”) between the FEOL devices; and
the single composition dielectric (24 – Fig. 3a – [0061] – “a dielectric liner (24)”) having an airgap (20 – Fig. 3a – [0061] – “airgap (20)”) that extends from within the shallow trench isolation regions (2a – Fig. 2 – [0047] – “ring-structure (2a) is fabricated in the substrate (1) by removing substrate material, e.g. by etching a circular trench in the substrate (1) e.g. Si substrate etch, thus producing an inner pillar structure (4) of substrate material” – this is interpreted as a shallow trench isolation region) to a region of a frontside (S2 – Fig. 4a – [0060] – “second main surface (S2) opposite the first main surface (S1)”) interlayer dielectric (13 – Fig. 4a – this is interpreted as a dielectric on the BEOL) between the FEOL devices.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Chang et al. (US 20250266293 A1 – hereinafter Chang).
Regarding claim 4, Cheng teaches claim 2 from which claim 4 depends. Cheng does not expressly disclose the limitations of claim 4.
However, in an analogous art, Chang teaches
wherein the backside airgap (272 – Fig. 24 – [0067] – “air gaps 272”) extends
between backside contacts (292 – Fig. 24 – [0075] – “backside vias 292, so as to make electrical connection” – these are vias that become contacts).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside airgap structure as taught by Chang into Cheng.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result of [0013] – “One advantageous feature having the air gaps is that air in the air gap exhibits a relative permittivity (or called dielectric constant) approximately equal to 1. Such a low dielectric constant helps to reduce the capacitive coupling between adjacent backside vias. Such reduced capacitive coupling may help to improve reliability characteristics.”
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sabuncuoglu in view of Chang.
Regarding claim 12, Sabuncuoglu teaches claim 10 from which claim 12 depends. Sabuncuoglu does not expressly disclose the limitations of claim 12.
However, in an analogous art, Chang teaches
wherein the airgap (272 – Fig. 24 – [0067] – “air gaps 272”) extends between
backside contacts (292 – Fig. 24 – [0075] – “backside vias 292, so as to make electrical connection” – these are vias that become contacts).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside airgap structure as taught by Chang into Sabuncuoglu.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable result as stated above in claim 4.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Mariottini et al. (US 20260075894 A1 – hereinafter Mariottini).
Regarding claim 8, Cheng teaches claim 1 from which claim 8 depends. Cheng does not expressly disclose the limitations of claim 8.
However, in an analogous art, Mariottini teaches
further comprising backside power rails (128 – Fig. 1A – [0031] – “Backside
conductive structures 128 may include any suitable conductive material such as tungsten or molybdenum, and may provide power or ground rails for the integrated circuit”) to connect to the FEOL devices by backside contacts (162 – fig 12) (mar (230 – Fig. 2I’ – [0051] – “conductive structures 230”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside power rail structure as taught by Mariottini into Cheng.
An ordinary artisan would have been motivated to use the known technique of Mariottini in the manner set forth above to produce the predictable result [0010] – “to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials.”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Mariottini and Seo et al. (US 20240243064 A1 – hereinafter Seo).
Regarding claim 9, Cheng, as modified by Mariottini, teaches claim 8 from which claim 9 depends. Cheng and Mariottini do not expressly disclose the limitations of claim 9.
However, in an analogous art, Seo teaches
wherein the backside power rails (BPW3 – Fig. 5 – [0101] – “backside power
rail BPW3”) include an extension (BV3 – Fig. 5 – [0103] – “backside power rail BPW3 may include a main rail BM3, a protrusion rail BP3, and a vertical extension BV3”) that forms a portion of the backside contacts (VPR – Fig. 3B – [0088] – “the plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected to the via power rail VPR on the via power rail VPR” – this is a backside contact).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside power rail structure as taught by Seo into Cheng and Mariottini.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result to [0004] – “provides an integrated circuit (IC) device having improved integration density and electrical reliability.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sabuncuoglu in view of Cheng.
Regarding claim 14, Sabuncuoglu teaches claim 10 from which claim 14 depends. Sabuncuoglu does not expressly disclose the limitations of claim 14.
However, in an analogous art, Cheng teaches
wherein the airgap (262 – Fig. 11 – [0070] – “air gap spacers 262”) is
disposed between source/drain regions (225 – Fig. 11 – [0069] – “epitaxial source (S)/drain (D) regions 225”) of the FEOL devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the airgap structure as taught by Cheng into Sabuncuoglu.
An ordinary artisan would have been motivated to use the known technique of Cheng in the manner set forth above to produce the predictable result [0003] – “to reduce parasitic coupling between adjacent conductive structures, the semiconductor industry has adopted the use of low dielectric constant (low-k) dielectrics and ultra-low-k (ULK) dielectrics (in place of conventional SiO.sub.2 (k=4.0)) as insulating materials for MOL and BEOL layers of ultra-large-scale integration (ULSI) integrated circuits. The advent of low-k dielectrics coupled with aggressive scaling, however, has led to critical challenges in the long-term reliability of such low-k materials. For example, low-k TDDB (time-dependent dielectric breakdown) is commonly considered a critical issue because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO, dielectrics.”
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sabuncuoglu in view of Seo.
Regarding claim 15, Sabuncuoglu teaches claim 10 from which claim 15 depends. Sabuncuoglu does not expressly disclose the limitations of claim 15.
However, in an analogous art, Seo teaches
further comprising backside power rails (BPW3 – Fig. 5 – [0101] – “backside
power rail BPW3”) to connect to the FEOL devices by backside contacts (VPR – Fig. 3B – [0088] – “the plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected to the via power rail VPR on the via power rail VPR” – this is a backside contact).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside power rail structure as taught by Seo into Sabuncuoglu.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result as stated above in claim 9.
Regarding claim 16, Sabuncuoglu teaches claim 10 from which claim 16 depends. Sabuncuoglu does not expressly disclose the limitations of claim 16.
However, in an analogous art, Seo teaches
wherein the backside power rails (BPW3) include an extension (BV3 – Fig. 5
– [0103] – “backside power rail BPW3 may include a main rail BM3, a protrusion rail BP3, and a vertical extension BV3”) that forms a portion of the backside contacts (VPR).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside power rail structure as taught by Seo into Sabuncuoglu.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result as stated above in claim 9.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Sabuncuoglu and Xie et al. (US 20220406715 A1 – hereinafter Xie).
Regarding independent claim 17, Cheng teaches:
A semiconductor device (100 – Fig. 1A – [0034] – “semiconductor
device 100”), comprising:
front end of line (FEOL) devices (120 – Fig. 1A – [0035] – “FEOL/MOL
structure 120”) arranged in a FEOL layer ([0036] – “the FEOL layer comprises FET devices (such as FinFET devices, planar MOSFET device, etc.), bipolar transistors, diodes, capacitors, inductors, resistors, isolation devices, etc., which are formed in or on the active surface of the semiconductor substrate 110”) defining a frontside (Fig. 11 – [0020] – “FIG. 11 is a cross-sectional schematic side view of a semiconductor device comprising air gap spacers that are integrally formed within a FEOL/MOL structure of the semiconductor device” – hereinafter ‘F-Front’) and a backside (if a surface has a frontside, then it must have a backside – hereinafter ‘Back’) opposite the frontside (F-Front);
a single composition dielectric material (236 – Fig. 12 – [0076] – “PMD layer 236 may be formed with any suitable insulating/dielectric materials such as, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, porous dielectrics, or organic dielectrics including porous organic dielectrics, etc. The PMD layer 236 may be formed using known deposition techniques, such as, for example, ALD, CVD, PECVD, spin on deposition, or PVD, followed by a standard planarization process (e.g., CMP)” – this describes a single composition dielectric material) covering the FEOL devices (che (120 – {[0073] – “FIG. 11 further illustrates a first interconnect level of a BEOL structure formed over the FEOL/MOL layers”}, {[0074] – “FIG. 12 is cross-sectional schematic view of the semiconductor device 200 at an intermediate stage of fabrication” – Fig. 12 shows this) and disposed in shallow trench isolation regions (236-1 – Fig. 12 – [0077] – “after patterning the PMD layer 236 to form contact openings 236-1 between the gate structures 230-1, 230-2, 230-3 of the vertical transistor structures M1, M2, M3 down to the source/drain regions 225. The contact openings 236-1 can be formed using known etching techniques and etching chemistries to etch the material of the PMD layer 236 selective to the insulating material of the capping layers 232 and sidewall spacers 234” – this describes shallow trench isolation regions) between the FEOL devices (120);
the single composition dielectric having an airgap that extends from within the shallow trench isolation regions to a region of a frontside interlayer dielectric between the FEOL devices; and
the single composition dielectric includes in a backside interlayer dielectric and is disposed between backside contacts and buried power rails.
Cheng does not expressly disclose the other limitations of claim 17.
However, in an analogous art, Sabuncuoglu teaches
the single composition dielectric (24 – Fig. 3a – [0061] – “a dielectric liner (24)”) having an airgap (20 – Fig. 3a – [0061] – “airgap (20)”) that extends from within the shallow trench isolation regions (2a – Fig. 2 – [0047] – “ring-structure (2a) is fabricated in the substrate (1) by removing substrate material, e.g. by etching a circular trench in the substrate (1) e.g. Si substrate etch, thus producing an inner pillar structure (4) of substrate material” – this is interpreted as a shallow trench isolation region) to a region of a frontside (S2 – Fig. 4a – [0060] – “second main surface (S2) opposite the first main surface (S1)”) interlayer dielectric (13 – Fig. 4a – this is interpreted as a dielectric on the BEOL) between the FEOL devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the single composition dielectric structure as taught by Sabuncuoglu into Cheng.
An ordinary artisan would have been motivated to use the known technique of Sabuncuoglu in the manner set forth above to produce the predictable result [0002] – “of forming airgaps whereby said airgaps are surrounding at least part of a TSV interconnect structure in order to reduce the capacitance of the interconnect structure. The disclosure further relates to devices thus obtained.”
Cheng and Sabuncuoglu do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Xie teaches
the single composition dielectric (12 – Fig. 14A – [0087] – “insulator layer 12” – this is a dielectric) includes in a backside interlayer dielectric (12 and 72 – Fig. 14B – [0089] – “inter-layer dielectric (ILD) 72” – elements 12 and 72 form a dielectric layer) and is disposed between backside contacts (1300 – Fig. 14A – [0088] – “backside local interconnect 1300”) and buried power rails (1410 – Fig. 14A – [0087] – “buried power rail (BPR) 1410”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric structure as taught by Xie into Cheng and Sabuncuoglu.
An ordinary artisan would have been motivated to use the known technique of Xie in the manner set forth above to produce the predictable result to [0002] – “improve the contact scheme for stacked FET by utilizing novel contact architectures from both frontside and backside of the wafer.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Sabuncuoglu, Xie, and Seo.
Regarding claim 20, Chen, as modified by Sabuncuoglu and Xie, teaches claim 17 from which claim 20 depends. Chen, Sabuncuoglu, and Xie do not expressly disclose the limitations of claim 20.
However, in an analogous art, Seo teaches
wherein the backside power rails (BPW3 – Fig. 5 – [0101] – “backside power
rail BPW3”) include an extension (BV3 – Fig. 5 – [0103] – “backside power rail BPW3 may include a main rail BM3, a protrusion rail BP3, and a vertical extension BV3”) that forms a portion of the backside contacts (VPR – Fig. 3B – [0088] – “the plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside power rail structure as taught by Seo into Chen, Sabuncuoglu, and Xie.
An ordinary artisan would have been motivated to use the known technique of Seo in the manner set forth above to produce the predictable result as stated above in claim 9.
Allowable Subject Matter
Claims 5-7, 11, 13, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, prior art of record fails to teach or suggest wherein the
single composition dielectric material lines a region of a frontside interlayer dielectric and includes a frontside airgap within a region of the frontside interlayer dielectric.
Claims 6 and 7 depends on claim 5 and is therefore allowable if claim 5 is rewritten.
Regarding claim 11, prior art of record fails to teach or suggest wherein the
airgap extends under a gate conductor on the backside.
Regarding claim 13, prior art of record fails to teach or suggest wherein the
airgap is disposed between middle of the line contacts.
Regarding claim 18, prior art of record fails to teach or suggest wherein the
airgap extends under a gate conductor and between the backside contacts on the backside.
Regarding claim 19, prior art of record fails to teach or suggest wherein the
airgap is disposed between middle of the line contacts and between source/drain regions of the FEOL devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights