DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: line 14 recites “omitting the black period”. It appears to be “omitting the additional black period”. Claim 8 and 13 have similar issues. Appropriate correction are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 8, 9, 13, 14, 18-19, 21 and 22 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Onishi et al. U.S. Patent Publication No. 2016/0379580 (hereinafter Onishi).
Consider claim 1, Onishi teaches a display device comprising: a display panel for displaying images (Figures 1-3, display frame image); a driver for driving the display panel (Figure 1, 20-30); and a timing controller for controlling the driver (Figure 1, 14-16), wherein, in operation, the timing controller changes, during an existing blank period between a first frame and a second frame (Figure 3, Frame B and Frame 1), a driving frequency from a first frequency to a second frequency and controls the displaying images without an additional black period between the first frame immediately before the transition between displaying images with the first frequency and displaying images with the second frequency and the second frame immediately after the transition based on at least a first signal transmitted to the timing controller (Figure 3, BR0 in between USUAL mode and PSR mode omits blanking period BR1 (see also figure 3 in between PSR mode and USUAL mode). [0061] and figure 3, frequency, PSR mode; image data of the frame stored in the storage unit 13), the first frame and the second frame being two separate frames with the existing blank period therebetween (Figure 3, Frame B, Frame 1 and BR0), and wherein the timing controller is configured to generate a mute-off signal for forcibly omitting the black period (Figure 3, PSR_ON) in addition to a driving mode switching signal for changing the driving frequency (Figure 3 and [0061-0062], switching from USUAL mode to PSR mode. Figure 3, omits BR1 in the display frame image).
Consider claim 2, Onishi teaches all the limitations of claim 1. In addition, Onishi teaches wherein the timing controller is configured to change the driving frequency and allow a period during which black is displayed on the display panel (Figure 3, BR1 in between PSR mode and Usual mode) based on a second signal transmitted to the timing controller through a communication channel different from that of the first signal (Figure 1 and [0061-0062], acquires image data from transfer controller 12).
Consider claim 4, Onishi teaches all the limitations of claim 2. In addition, Onishi teaches wherein at least one of the first signal or the second signal is applied in a blank period in which no image is displayed on the display panel (Figure 3, PSR_ON during blank BR0).
Consider claim 8, it includes the limitations mentioned above in claim 1 and thus rejected by the same reasoning.
Consider claim 9, it includes the limitations mentioned above in claim 4 and thus rejected by the same reasoning.
Consider claim 13, Onishi teaches a display device, comprising: a display panel for displaying images (Figure 3, display frame image); a driver for driving the display panel (Figure 1, 20-30); and a timing controller for controlling the driver (Figure 1, 14-16), the timing controller including a selection unit and a signal reception circuit, the selection unit configured to select one of a first signal or a second signal to transmit to the signal reception circuit (Figure 1 and [0061], data acquisition unit 14 receives from 11-13 and 100; first signal or second signal corresponding to PSR mode or Normal mode), and the signal reception circuit configured to issue a control signal to control image displaying with a driving frequency changed from a first driving frequency to a second driving frequency based on the selected one of the first signal or the second signal (Figure 3, Usual mode and PSR mode; [0061], drive frequency), wherein the control signal includes one or more of a first control signal or a second control signal, the first control signal configured to control a driving mode of a driving frequency ([0061], drive frequency is set by adjusting a clock frequency and thus a corresponding control signal or adjusting signal), and the second control signal configured to control omitting a period during which black is displayed ([0063] and figure 3, PSR_ON) so that the displaying images continues with the driving frequency being changed, during an existing blank period between a first frame and a second frame, from the first driving frequency to the second driving frequency and there is no additional black period between the first frame immediately before the driving frequency being changed from the first driving frequency to the second driving frequency and the second frame immediately after the driving frequency being changed (Figure 3, BR0 in between USUAL mode and PSR mode omits blanking period BR1 (see also figure 3 in between PSR mode and USUAL mode). [0061] and figure 3, frequency, PSR mode; image data of the frame stored in the storage unit 13), the first frame and the second frame being two separate frames with the existing blank period therebetween (Figure 3, Frame B, Frame 1 and BR0), and wherein the timing controller is configured to generate a mute-off signal for forcibly omitting the period during which black is displayed on the display panel in addition to a driving mode switching signal for changing the driving frequency (Figure 3 and [0061-0062], switching from USUAL mode to PSR mode. Figure 3, omits BR1 in the display frame image).
Consider claim 14, Onishi teaches all the limitations of claim 13. In addition, Onishi teaches wherein the selection unit is configured to receive the first signal or the second signal through two different channels (Figure 1, through 13 or 12).
Consider claim 18, Onishi teaches all the limitations of claim 13. In addition, Onishi teaches wherein the signal reception circuit is configured to issue the first control signal and the second control signal in a case that the first signal is received at the signal reception circuit (Figure 1 and [0061], data acquisition unit 14 receives from 11-13 and 100; signals corresponding to PSR mode or Usual mode. [0061], the drive frequency is set by adjusting a clock frequency).
Consider claim 19, Onishi teaches all the limitations of claim 13. In addition, Onishi teaches wherein the signal reception circuit is configured to issue the first control signal without the second control signal (Figure 3, without PSR_ON (second control signal) or with PSR_OFF. [0061], the drive frequency is set by adjusting a clock frequency (first control signal)) in a case that the second signal is received at the signal reception circuit (Figure 1 and [0061], data acquisition unit 14 receives from 11-13 and 100; signals corresponding to PSR mode or Usual mode).
Consider claim 21, Onishi teaches all the limitations of claim 1. In addition, Onishi teaches wherein the timing controller includes a signal reception circuit (Figure 1 and [0061], data acquisition unit 14 receives from 11-13 and 100; first signal or second signal corresponding to PSR mode or Normal mode) that generates the mute-off signal and the driving mode switching signal (Figure 3, Usual mode and PSR mode; [0061], drive frequency. Figure 3, omits BR1 in the display frame image).
Consider claim 22, Onishi teaches all the limitations of claim 21. In addition, Onishi teaches wherein the timing controller further includes a controller configured not to output a black data signal in response to the mute-off signal output from the signal reception circuit (Figure 1 and [0061], data acquisition unit 14 receives from 11-13 and 100; signals corresponding to PSR mode or Usual mode. [0061], the drive frequency is set by adjusting a clock frequency), and an image processor configured to perform image processing for compensating a data signal based on a data enable signal and the driving mode switching signal (Figure 1 and [0066], determination process. [0061], driver frequency is set by adjusting a clock frequency).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-7, 10-12, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onishi as applied to claim 1 above, and further in view of Cho et al. WO2022045676A1 (English Translation provided by U.S. Patent Publication No. 2023/0306890 (hereinafter Cho).
Consider claim 5, Onishi teaches all the limitations of claim 2.
Onishi does not appear to specifically disclose wherein a display module including the display panel, the driver, and the timing controller is configured to sense elements included in subpixels of the display panel and compensate for a data signal to an elements that is determined to have deterioration based on the sensing the elements.
However, in a related field of endeavor, Cho teaches a display receiving variable frequency in figure 7 and further teaches wherein a display module including the display panel, the driver, and the timing controller (Figure 1, 12-14) is configured to sense elements included in subpixels of the display panel (Figure 2, PXL and SU) and compensate for a data signal to an elements that is determined to have deterioration based on the sensing the elements [0056] and [0074].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to sense and compensate as taught by Cho in order to display corrected data and improve display quality as suggested in [0074] and [0003].
Consider claim 6, Onishi and Cho teach all the limitations of claim 5.
Onishi does not appear to specifically disclose wherein the timing controller is configured to count a data enable signal, determine whether a time threshold to sense the elements is met when the driving frequency is switched, and control a sensing operation for sensing the elements to be skipped when the time threshold to sense the elements is not met.
However, Cho teaches wherein the timing controller is configured to count a data enable signal ([0089], TCMP), determine whether a time threshold to sense the elements is met when the driving frequency is switched ([0089] and figure 12, in other words, the host system may skip generation of a compensation command signal CCMD in response to the vertical blank period shorter than one sensing period TCMP. [0087], variable frame frequency), and control a sensing operation for sensing the elements to be skipped when the time threshold to sense the elements is not met [0087] and [0089].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to skip generation of a compensation command as taught by Cho with the benefit that it is possible to prevent accuracy in sensing from being reduced due to insufficient sensing time as suggested in [0089].
Consider claim 7, Onishi and Cho teach all the limitations of claim 6. In addition, Cho teaches wherein the timing controller is configured to control sensing line initialization (Figure 12, CCMD during Vblank3), the sensing line initialization including: discarding sensing values acquired during a frame in which the sensing operation has been skipped [0087] and [0089]; and performing initialization in addition to the skipping the sensing operation (Figure 12, CCMD during Vblank3), see motivation to combine in claim 6.
Consider claim 10, it includes the limitations mentioned above in claim 5 and thus rejected by the same reasoning.
Consider claim 11, it includes the limitations mentioned above in claim 6 and thus rejected by the same reasoning.
Consider claim 12, it includes the limitations mentioned above in claim 7 and thus rejected by the same reasoning.
Consider claim 20, Onishi teaches all the limitations of claim 13.
Onishi does not appear to specifically disclose wherein the first control signal is configured to be applied during a blank period.
However, Cho teaches wherein the first control signal is configured to be applied during a blank period ([0048], the graphics processing unit GPU may secure data rendering time by varying the length of the vertical blank period depending on complexity of an image…frame frequency is variable. Thus, the control is during the blank period in order to vary the length of the blank period).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to control during a blank period since it is possible to more easily control the operation of the panel drive circuit as suggested in [0048].
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onishi as applied to claim 14 above, and further in view of Morita U.S. Patent Publication No. 2016/0217758 (hereinafter Morita).
Consider claim 15, Onishi teaches all the limitations of claim 14.
Onishi does not appear to specifically disclose wherein the selection unit is configured to receive the first signal through a differential voltage communication channel.
However, in a related field of endeavor, Morita teaches an electro-optical display panel in [0179] and further teaches wherein the selection unit is configured to receive the first signal through a differential voltage communication channel ([0163], LVDS).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide LVDS as taught by Morita since the interfacing process is carries out on serial communication. In addition, it carries out serial/parallel conversion on control data, image data, and so on as suggested in [0163].
Consider claim 16, Onishi teaches all the limitations of claim 14.
Onishi does not appear to specifically disclose wherein the selection unit is configured to receive the second signal through a serial communication channel.
However, in a related field of endeavor, Morita teaches an electro-optical display panel in [0179] and further teaches wherein the selection unit is configured to receive the second signal through a serial communication channel ([0163], serial communication).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide serial communication as taught by Morita since it carries out serial/parallel conversion on control data, image data, and so on as suggested in [0163].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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