DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-11 and 16-24 in the reply filed on 10 July 2026 is acknowledged.
Claims12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 18, 19, 20, 22 and 23 are objected to because of the following informalities:
18. The semiconductor device of claim 16, wherein the first field dielectric of the first columnar trench has a thickness that is greater on a lower portion of the first side wall than on an upper portion of the first side wall and the second field dielectric of the second columnar trench has a thickness that is substantially uniform.
19. The semiconductor device of claim 16, wherein the first field dielectric of the first columnar trench has a thickness (t1) in an upper region of the first side wall and a thickness (t2) in a lower region of the side wall, and wherein t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2.
20. The semiconductor device of claim 16, wherein the side face of the first field plate of the first columnar trenches comprises a step such that an upper portion of the first field plate has a width that is greater than a width of a lower portion of the first field plate and such that the first field dielectric has a first thickness in the first region of the first columnar trench and a second thickness different than the first thickness in the second region of the first columnar trench.
22. The semiconductor device of claim 16, wherein the second inactive cells each comprises a second field dielectric that is arranged on the second base and the second side wall and that has a thickness (t2) on the second side wall that varies by less than ± 1.1 t2.
23. The semiconductor device of claim 16, wherein the first field plate of the first columnar trenches has a T-shape and the second field plate of the second columnar trenches has a columnar shape.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7, 20 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5, 6 and 21 recite the limitation “the first major surface”. There is insufficient antecedent basis for this limitation in the claim. Claim 7 depends directly on Claim 6 and is therefore rejected.
Claim 20 recites the limitation “the side face”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-18, 20-21, 23 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogura et al. US 11,227,928.
PNG
media_image1.png
495
820
media_image1.png
Greyscale
Ogura et al. US 11,227,928
Regarding claim 16, Ogura et al. Figs. 1A-2 disclose a semiconductor device, comprising:
an active area A col. 4, lines 55-59; and
an edge termination region T col. 4, lines 55-59 laterally surrounding the active area A, Figs. 1A-1B, wherein the active area A comprises a plurality of active transistor cells 110a, 110d, 110e, col. 5, lines 12-27
wherein the edge termination region T comprises one or more first inactive cells 110c and one or more second inactive cells 110b col. 6, line 56-col. 8, line 14, wherein each of the one or more first inactive transistor cells comprises a first columnar trench 150 having a first base and a first side wall and comprises a first field plate 120 and a first field dielectric structure 212 that is arranged on the first base and the first side wall and that surrounds the first field plate 120, wherein each of the one or more second inactive transistor cells comprises a second columnar trench 150 having a second base and a second side wall and comprises a second field plate 120 and a second field dielectric structure 212 that is arranged on the second base and the second side wall and that surrounds the second field plate, wherein the first field dielectric structure 212 of 110c has a different thickness profile than the second field dielectric structure 212 of 110b.
Regarding claim 17, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the active area A and the edge termination region T are formed in a semiconductor substrate 200, and wherein the semiconductor substrate 200 has an edge surrounding a first major surface and the second inactive cells 110b are closer to an edge of the semiconductor substrate than the first inactive transistor cells 110c. It is understood that the edge is the outermost region and the first major surface as the inner most region; 110b is closer to the outermost region than 110c.
Regarding claim 18, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the field dielectric 212 of the first columnar trench 110c has a thickness that is greater on a lower portion of the side wall than on an upper portion of the side wall and the field dielectric 212 of the second columnar trench 110b has a thickness that is substantially uniform.
Regarding claim 20, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the side face of the field plate 120 of the first columnar trenches 150 of 110c comprises a step (annotated above) such that an upper portion of the field plate 120 has a width that is greater than a width of a lower portion of the field plate 120 and such that the field dielectric 212 has a first thickness in the first region of the first columnar trench 150 of 110c and a second thickness different than the first thickness in the second region of the first columnar trench 150 of 110c.
Regarding claim 21, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 20, wherein the first inactive cells further comprise a termination mesa 615a Fig. 6 col. 11, lines 10-30, wherein the termination mesa comprises a drift region of a first conductivity type and a body region of a second conductivity type that opposes the first conductivity type and the body region is arranged on the drift region, wherein the step is located at a depth (d1) from the first major surface of the semiconductor substrate and the pn junction formed between the body region and the drift region has a depth (dpn) from the first major surface of the semiconductor substrate, and wherein d1 > dpn. (annotated above).
Regarding claim 23, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the field plate 120 of the first columnar trenches 150 of 110c has a T-shape and the field plate 120 of the second columnar trenches 150 of 110c has a columnar shape.
Regarding claim 24, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the edge termination region T comprises a transition region 125 that laterally surrounds the active region A and one or more of the first inactive cells 110c are arranged in the transition region 125.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. US 2016/0064547 in view of Ogura et al. US 11,227,928.
PNG
media_image2.png
448
496
media_image2.png
Greyscale
PNG
media_image3.png
500
523
media_image3.png
Greyscale
Siemieniec et al. US 2016/0064547
Regarding claim 1, Siemieniec et al. in Figs. 3A-3B and [0039]-[0090] disclose a semiconductor device, comprising:
an active area 610 [0039]; and
an edge termination region 690 [0047] laterally surrounding the active area 610, wherein the active area 610 comprises a plurality of active transistor cells 160 [0039],
wherein the edge termination region comprises a first plurality of inactive cells 180 [0047], each of the first plurality of inactive cells 180 comprising a columnar trench [0060] e.g. needle-shaped structures and a termination mesa 190 [0053] arranged adjacent to the columnar trench Figs. 3A-3B;
wherein each of the columnar trenches comprises a base, a side wall, a field plate 185 [0048], and a field dielectric 181 [0048] arranged on the base and the side wall and surrounding the field plate,
wherein each of the field dielectrics 181 has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate,
wherein each of the termination mesas comprises a drift region of a first conductivity type and a body region 186 [0054] of a second conductivity type arranged above the drift region 121 [0054].
Siemieniec et al. do not expressly disclose the first thickness in an upper region of the field plate being smaller than the second thickness in the lower region of the field plate.
However, Ogura et al. in Figs. 1A-2 and col. 2, line 45 – col. 8, line 40 teach termination structures for trench gate field effect transistors that prevent breakdown voltage degradation and increases in leakage. The termination structure 110c in termination region T includes a shield dielectric 212 disposed in an upper portion of a field plate 110c having a first thickness and a second thickness in a bottom portion sidewall of the field plate 110c Fig. 2.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Ogura et al. in the semiconductor device of Siemieniec et al. for the purpose of improving the device performance and reliability.
Regarding claim 2, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 1. Siemieniec et al. in Fig. 3A teach wherein the first plurality of inactive transistor cells 180 are directly adjacent to one or more of the plurality of active transistor cells 160.
Regarding claim 3, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 1. Siemieniec et al. in Fig. 3B teach wherein the upper region is contiguous to the body region 186 and the lower region is contiguous to the drift region 190. Siemieniec et al. in view of Ogura et al. do not expressly teach the first thickness (t1) is equal to or smaller than 1.15 times the second thickness (t2) or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 4, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 1. Ogura et al. in Fig. 2 (annotated above) teach wherein the side face of each of the field plates comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate and such that the field dielectric has the first thickness in the upper region and the second thickness in the lower region.
Regarding claim 5, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 4. Ogura et al. in Fig. 2 (annotated above) teach the step is located at a first depth from the first major surface of the semiconductor substrate and a p n junction is formed between the body region and the drift region at a second depth from the first major surface of the semiconductor substrate, and wherein the first depth is greater than the second depth.
Regarding claim 6, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 1. Ogura et al. in Fig. 2 (annotated above) teach wherein the first plurality of inactive transistor cells are disposed in a transition region of the edge termination region that laterally surrounds the active region, wherein the edge termination region further comprises an inner termination region that laterally surrounds the transition region, wherein the inner termination region comprises a second plurality of inactive cells, each inactive cell of the second plurality of inactive cells comprising a second columnar trench having a base and a side wall and comprising a field plate and a second termination mesa comprising a drift region of a first conductivity type and no body region of the second conductivity type, and wherein the drift region extends to the first major surface; wherein each field dielectric of the second columnar trenches has the first thickness adjacent an upper region of the field plate and the second thickness adjacent a lower region of the field plate.
Regarding claim 7, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 6. Ogura et al. in Fig. 2 (annotated above) teach wherein the edge termination region further comprises an intermediate termination region that laterally surrounds the inner termination region, wherein the intermediate termination region comprises a third plurality of inactive cells, each of the third plurality of inactive cell comprising a third columnar trench having a base and a side wall and comprising a field plate and a third termination mesa comprising a drift region of a first conductivity type and no body region of the second conductivity type, wherein the drift region extends to the first major surface, and wherein the third columnar trench comprises a field dielectric that is arranged on the base and the side wall.
Siemieniec et al. in view of Ogura et al. do not expressly teach the field dielectric that has a thickness (t2) on the side wall that varies by less than ± 1.1 t2.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 10, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 1. Siemieniec et al. in Fig. 3B teach each active transistor cell comprises a mesa 170 [0044] and a columnar trench 160 [0044], and wherein the mesa comprises the drift region 121 [0045], the body region 115 [0046] arranged on the drift region 121, a source region 110 [0046] of the first conductivity type arranged on the body region 115, and a gate trench comprising a gate electrode 150 [0046].
Regarding claim 11, Siemieniec et al. in view of Ogura et al. teach the semiconductor device of claim 10. Siemieniec et al. in Fig. 3B teach wherein the columnar trench of each active transistor cell comprises a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate, and wherein the field dielectric has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate. Siemieniec et al. do not expressly teach the first thickness being smaller than the second thickness.
Ogura et al. in Fig. 2 teach wherein the field dielectric has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate.
Claim(s) 19 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogura et al. US 11,227,928.
Regarding claim 19, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the field dielectric of the first columnar trench has a thickness (t1) in an upper region of the side wall and a thickness (t2) in a lower region of the side wall, but do not expressly disclose wherein t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 22, Ogura et al. Figs. 1A-2 disclose the semiconductor device of claim 16, wherein the second inactive cells each comprises a field dielectric that is arranged on the base and the side wall but do not expressly disclose a thickness (t2) on the side wall that varies by less than ± 1.1 t2.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims: the edge termination region further comprises a continuous ring of the second conductivity type that laterally surrounds the plurality of inactive cells. Claim 9 depends directly from Claim 8 and is therefore allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
Prosecution Insights