DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 19 objected to because of the following informalities:
Claim 19 recites the limitation “The method device of Claim 16, the second plug is formed by pouring a molten metal into a first concave portion formed in the first insulator”. It appears that the applicant intended to recite “The method device of Claim 16, wherein the second plug is formed by pouring a molten metal into a first concave portion formed in the first insulator”.
The objection can be overcome by correcting the limitation to “The method device of Claim 16, wherein the second plug is formed by pouring a molten metal into a first concave portion formed in the first insulator”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM et al. (US 20230061301 A1) hereinafter referred to as "KIM".
Regarding claim 1, KIM discloses a semiconductor device comprising: a first substrate (Fig. 1, element 3; ¶:[0049-0050]); a memory cell array including a plurality of first electrode layers (Fig. 1, element 140; ¶:[0051]) that are provided above the first substrate, and are spaced from each other in a first direction (vertical), a columnar portion (Fig 2A; Fig. 1, element A; ¶:[0051]) that is provided in the plurality of first electrode layers, extends in the first direction, and includes a charge storage layer (Fig. 2A, element 118; ¶:[0074]) and a semiconductor layer (Fig. 2A, element 126; ¶:[0068]), and a first metal layer (Fig. 1, element 189a; ¶:[0051]) that is provided above the plurality of first electrode layers, and is electrically connected to an end of the semiconductor layer; a first plug (Fig. 1, element 150i; ¶:[0059]) provided above the first substrate; and a first interconnect layer (Fig. 1, element 198; ¶:[0066]) provided above the first plug, and electrically connected to the first plug through the first metal layer.
Regarding claim 2, KIM discloses a first insulator (Fig. 1, element 192; ¶:[0051]) provided between the first metal layer and the first interconnect layer.
Regarding claim 3, KIM discloses the first interconnect layer (Fig. 4, element 198; ¶:[0066]) being electrically connected to the first plug through a second plug (Fig. 4, element 198_v2; ¶:[0066]) provided in the first insulator.
Regarding claim 6, KIM discloses the first metal layer including: a first portion (Fig. 1, element 189a; ¶:[0051]) provided above the plurality of first electrode layers, and electrically connected to the end of the semiconductor layer, and a second portion (Fig. 1, element 189b; ¶:[0058-0059]) separated from the first portion, and electrically connected to the first plug and the first interconnect layer.
Regarding claim 7, KIM discloses the first portion being a source line (Fig. 40, element 4205; ¶:[0312]).
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Claim(s) 14-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshida et al. (US 20240015959 A1) hereinafter referred to as "Yoshida".
Regarding claim 14, Yoshida discloses a method of manufacturing a semiconductor device, comprising: forming a memory cell array including a plurality of first electrode layers (Fig. 26, element 46; ¶: [0166]) that are provided above a first substrate (Fig. 19, element 9; ¶: [0113]), are spaced from each other in a first direction, a columnar portion (Fig. 26, element 78; ¶: [0176]) that is provided in the plurality of first electrode layers, extends in the first direction, and including a charge storage layer (Fig. 26, element 50; ¶: [0146]) and a semiconductor layer (Fig. 26, element 60; ¶: [0146]), and a first metal layer (Fig. 26, element 146; ¶: [0166]) that is provided above the plurality of first electrode layers, and electrically connected to an end of the semiconductor layer; forming a first plug (Fig. 26, element 84; ¶: [0179]) above the first substrate; and forming a first interconnect layer (Fig. 26, element 628B; ¶: [0197]) provided above the first plug, and electrically connected to the first plug through the first metal layer.
Regarding claim 15, Yoshida discloses forming a first insulator (Fig. 26, element 132; ¶: [0130]) on the first metal layer, wherein the first interconnect layer is formed on the first insulator.
Regarding claim 16, Yoshida discloses the first interconnect layer (Fig. 26, element 628B; ¶: [0198]) being electrically connected to the first plug through a second plug provided in the first insulator.
Regarding claim 17, Yoshida discloses the first interconnect layer and the second plug being simultaneously formed (Fig. 26 element 628B; ¶: [0199]).
Regarding claim 18, Yoshida discloses the first interconnect layer being formed after the second plug is formed (Fig. 24-26, element 628B; ¶: [0197, 0198]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Yoshida.
Regarding claim 4, KIM teaches the device of claim 3, but does not teach a barrier metal layer, and an interconnect material layer provided on the barrier metal layer, and the barrier metal layer and the interconnect material layer are also included in the second plug.
Yoshida teaches a barrier metal layer (Fig. 26, element 622B; ¶:[0199]), and an interconnect material layer (Fig. 26, element 624B; ¶:[0199]) provided on the barrier metal layer, and the barrier metal layer and the interconnect material layer are also included in the second plug (Fig. 26, element 628B; ¶:[0199]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the interconnect layer in the second plug in order to create contact with the metal layer (¶:[0198]).
Regarding claim 5, KIM teaches the device of claim 3, but does not teach a barrier metal layer, and an interconnect material layer provided on the barrier metal layer, and neither the barrier metal layer nor the interconnect material layer is included in the second plug.
Yoshida teaches a barrier metal layer (Fig. 26, element 622A; ¶:[0199]), and an interconnect material layer (Fig. 26, element 622A; ¶:[0199]) provided on the barrier metal layer, and neither the barrier metal layer nor the interconnect material layer is included in the second plug (Fig. 26, element 628A; ¶:[0199]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to not include the interconnect layer in the second plug In order to physically contact a semiconductor layer while still being electrically connected to the metal layer (¶:[0198]).
Regarding claim 11, KIM teaches the device of claim 1, but does not teach the first interconnected layer including a bonding pad.
Yoshida teaches the first interconnected layer including a bonding pad (Fig. 26, element 628; ¶:[0197]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a bonding pad so that the interconnect layer can be connected to at least one via structure through the metal plate (¶:[0198]).
Regarding claim 12, KIM teaches the device of claim 6, but does not teach the first interconnect layer including a third portion electrically connected to the second portion at a plurality of places.
Yoshida teaches the first interconnect layer including a third portion (Fig. 26, element 628b; ¶:[0198]) electrically connected to the second portion at a plurality of places.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect at a plurality of places so as to have a stronger connection to a metal of high conductivity (¶:[0197]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Nakatsuka et al. (US 20230320107 A1) hereinafter referred to as “Nakatsuka”.
Regarding claim 8, KIM teaches the device of claim 6, but does not teach the first portion being provided on the semiconductor layer to be in contact with the semiconductor layer.
Nakatsuka teaches the first portion being provided on the semiconductor layer to be in contact with the semiconductor layer (Fig. 7, element 30, 41; ¶:[0097]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have contact between a portion of the metal layer and the semiconductor layer in order to have the tunnel current flow from the source line to the channel (¶:[0125]).
Regarding claim 9, KIM in view of Nakatsuka teach the device of claim 8. KIM does not teach the first portion being electrically connected to the semiconductor layer by Schottky barrier junction.
Nakatsuka further teaches the first portion being electrically connected to the semiconductor layer by Schottky barrier junction (Fig. 7, element 30, 41; ¶:[0097]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply a reverse bias and improve the performance of a read operation in the memory device (¶:[0144]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Nakatsuka and Hwang et al. (US 20110151667 A1) hereinafter referred to as "Hwang".
Regarding claim 10, KIM in view of Nakatsuka teaches the device of claim 8, but does not teach the first portion being electrically connected to the semiconductor layer including impurity atoms by non-Schottky barrier junction.
Hwang teaches the first portion being electrically connected to the semiconductor layer including impurity atoms by non-Schottky barrier junction (Fig 2B, element 150, 157; ¶:[0051]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to do so in order to create ohmic contact between the metal layer and semiconductor layer (¶:[0051]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Lu et al. (US 20190081069 A1) hereinafter referred to as "Lu".
Regarding claim 13, KIM teaches the device of claim 6 , but does not teach the first interconnect layer further including a fourth portion electrically connected to the first portion.
Lu teaches the first interconnect layer further including a fourth portion (Fig 2, element 253, 254; ¶:[0072]) electrically connected to the first portion.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to do so in order for the interconnect layer to have the ability to transfer electrical signals (¶:[0072]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kim et al. (US 20230422523 A1) hereinafter referred to as "Kim".
Regarding claim 20, Yoshida teaches the method of claim 14, but does not teach the plurality of first electrode layers and the columnar portion being formed above a second substrate, the second substrate bonded to the first substrate to cause the plurality of first electrode layers and the columnar portion to be disposed above the first substrate, and is removed after bonded to the first substrate, and the first metal layer is formed above the plurality of first electrode layers after the second substrate is removed.
Kim teaches the plurality of first electrode layers and the columnar portion being formed above a second substrate (Fig 5A, element 100; ¶:[0131,0136]), the second substrate bonded to the first substrate to cause the plurality of first electrode layers and the columnar portion to be disposed above the first substrate, and is removed after bonded to the first substrate, and the first metal layer is formed above the plurality of first electrode layers after the second substrate is removed.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second substrate bonded to the first substrate so that bonding pads belonging to the structures in which the first and second substrate belong may be fused once coupled together (¶:[0130]).
Allowable Subject Matter
Claim 19 would be allowable if rewritten to overcome the objection set forth in this Office Action and to include all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 19, Yoshida (US 20240015959 A1) is cited as teaching certain elements of the claimed invention including an electrical connection of the interconnect layer to a first plug through a second plug provided in the insulator.
However, the prior art, when taken alone or in combination, cannot be construed as teaching or suggesting the second plug being formed by pouring a molten metal into a first concave portion formed in the first insulator.
Conclusion
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/I.H./Examiner, Art Unit 2899
/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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