DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amended Claim 7 with respect to being rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention has been fully considered and are persuasive. The rejection of Claim 7 under 35 U.S.C. 112 has been withdrawn.
Applicant's arguments filed 01/12/2026 has been fully considered and the amended claims are clarified with a secondary reference Rifani et al. (US 7,386,749 B2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8-13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petrov et al. (US 8,773,184 B1), in view of Rifani et al. (US 7,386,749 B2).
Regarding Claim 1, Petrov et al. teaches in Figure 4 a method comprising:
coupling a voltage generator to a capacitor to charge the capacitor during a first time period (when phy1 is closed; when phy2 is closed);
isolating the voltage generator from the capacitor and from an operational amplifier during a second time period (when phy1 is open; when phy2 is open); and
supplying a voltage from the capacitor to the operational amplifier during the second time period (when phy1 is open, capacitor connected to phy1 supplies a voltage to OA 235; when phy2 is open, capacitor connected to phy2 supplies a voltage to OA 235),
wherein the first time period is when a signal is inactive and the second time period is when the signal is active (based on switch control of phy1, phy2);
but does not explicitly teach the first time period is when a bus is inactive and the second time period is when the bus is active.
Rifani et al. teaches in Col. 3 “a reference clock signal, such as a bus clock” illustrates a reference clock signals and a bus clock are considered equivalent structures by one of ordinary skill in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a bus clock, as taught in Rifani et al., to generate the reference clock signals of Petrov et al. for the purpose of using art-recognized equivalent structures.
Regarding Claim 3, Petrov et al. further teaches the method further comprising:
using the operational amplifier to generate a control signal for an oscillator (OA 235 generates a control signal to VCO through 236 and 238); and
supplying a clock signal for the bus based on an output of the oscillator (wherein OA 235 is within the phase locked loop of Figure 1, Figure 2).
Regarding Claim 4, Petrov et al. further teaches the method wherein the bus is determined to be active responsive to a bus control signal being asserted (based on control signals received by circuitry in order to activate circuitry).
Regarding Claim 6, Petrov et al. further teaches the method wherein the voltage supplied to the operational amplifier is a common mode voltage (Col. 10, lines 25-27).
Regarding Claim 8, Petrov et al. teaches in Figure 4 an apparatus comprising:
an operational amplifier (235);
a voltage generator coupled to the operational amplifier during a first time period (when phy1 is closed; when phy2 is closed);
a capacitor coupled to a node between the voltage generator and the operational amplifier (capacitor coupled to either phy1 or phy2), the capacitor coupled to the voltage generator during the first time period and configured to store a sampled voltage (when phy1 is closed; when phy2 is closed); and
wherein the sampled voltage is supplied to the operational amplifier during a second time period (when phy1 is open; when phy2 is open); and
wherein the first time period is when a signal is inactive and the second time period is when the signal is active (based on switch control of phy1, phy2);
but does not explicitly teach the first time period is when a bus is inactive and the second time period is when the bus is active.
Rifani et al. teaches in Col. 3 “a reference clock signal, such as a bus clock” illustrates a reference clock signals and a bus clock are considered equivalent structures by one of ordinary skill in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a bus clock, as taught in Rifani et al., to generate the reference clock signals of Petrov et al. for the purpose of using art-recognized equivalent structures.
Regarding Claim 11, Petrov et al. further teaches the apparatus further comprising:
an oscillator having a control signal coupled to an output of the operational amplifier (OA 235 generates a control signal to VCO through 236 and 238); and
wherein a clock signal for the bus is coupled to an output of the oscillator (VCO of Figure 1, Figure 2 generates a clock signal).
Regarding Claim 12, Petrov et al. further teaches the apparatus further comprising a phase-locked loop including the oscillator and the operational amplifier (where Figure 1 and Figure 2 each depict a phase-locked loop including the VCO and 235, as further detailed in Figure 4).
Regarding Claim 13, Petrov et al. further teaches the apparatus wherein the bus is determined to be active responsive to a bus control signal being asserted (based on control signals received by circuitry in order to activate circuitry).
Regarding Claim 16, Petrov et al. further teaches the apparatus wherein the voltage is a common mode voltage (Col. 10, lines 25-27).
Claim(s) 5, 14, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petrov et al. (US 8,773,184 B1) and Rifani et al. (US 7,386,749 B2), as a whole and as applied to claims 1 and 8 above, and further in view of Neubarth et al. (US 7,889,477 B2).
Regarding Claim 5, Petrov et al. and Rifani et al., as a whole, teach all the limitations of the present invention, wherein Petrov et al. further teaches the method further comprising:
turning on a first transistor during the first time period to couple the voltage generator to the capacitor and to an input of the operational amplifier (closing the switch controlled by phy1, phy2); and
turning off the transistor during the second time period to isolate the voltage generator from the capacitor and from the input of the operational amplifier (opening the switch controlled by phy1, phy2);
but does not explicitly teach that the switches are transistors.
Neubarth et al. teaches in Col 5, lines 20-30 npn bipolar transistors are known to “one of ordinary skill in the art having the benefit of the herein disclosure would readily recognize that any suitable switch element may be employed, such as a [bipolar NPN transistor], MOSFET, JFET, IGBT, MCT, thyristor, opto-isolator or equivalent switch element." Col. 5, lines 25-30. Thus, Neubarth et al. shows that a transistor is an equivalent structure known in the art of a switch.
Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute a switch of Petrov et al. and Rifani et al., as a whole, for an equivalent transistor. Neubarth et al.: Col. 5, lines 25-30.
Regarding Claim 14, Petrov et al. and Rifani et al., as a whole, teach all the limitations of the present invention, wherein Petrov et al. further teaches the apparatus further comprising:
a first transistor coupled between the voltage generator and the capacitor to couple the voltage generator to the capacitor during the first time period (phy1, phy2);
wherein the first transistor is turned on responsive to the bus being inactive to allow the capacitor charge (when phy1 is closed; when phy2 is closed); and
wherein the first transistor is turned off responsive to the bus being active to isolate the capacitor from the voltage generator and to cause the sampled voltage to be supplied to the operational amplifier (when phy1 is open; when phy2 is open);
but does not explicitly teach that the switches are transistors.
Neubarth et al. teaches in Col 5, lines 20-30 npn bipolar transistors are known to “one of ordinary skill in the art having the benefit of the herein disclosure would readily recognize that any suitable switch element may be employed, such as a [bipolar NPN transistor], MOSFET, JFET, IGBT, MCT, thyristor, opto-isolator or equivalent switch element." Col. 5, lines 25-30. Thus, Neubarth et al. shows that a transistor is an equivalent structure known in the art of a switch.
Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute a switch of Petrov et al. and Rifani et al., as a whole, for an equivalent transistor. Neubarth et al.: Col. 5, lines 25-30.
Regarding Claim 18, Petrov et al. teaches in Figure 4, an apparatus comprising:
an operational amplifier (235);
a voltage generator coupled to the operational amplifier during a first time period (as connected to 235 by phy1, phy2);
a transistor coupled between the voltage generator and the operational amplifier (phy1, phy2);
a capacitor having a first terminal coupled to a node between the first transistor and the operational amplifier and a second terminal coupled to ground (capacitors as connected to phy1, phy2 and 235), the capacitor to sample a voltage supplied to the capacitor through the transistor during the first time period and store a sampled voltage (when phy1 is closed; when phy2 is closed);
wherein the transistor turns on responsive to the bus being inactive to allow the capacitor to charge (when phy1 is closed; when phy2 is closed); and
wherein the transistor turns off responsive to the bus being active to cause the sampled voltage to be supplied to the operational amplifier and to cause the capacitor and operational amplifier to be decoupled from the voltage generator (when phy1 is open; when phy2 is open);
but does not explicitly teach that
the bus being inactive corresponding to the first time period; and
the switches are transistors.
Rifani et al. teaches in Col. 3 “a reference clock signal, such as a bus clock” illustrates a reference clock signals and a bus clock are considered equivalent structures by one of ordinary skill in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a bus clock, as taught in Rifani et al., to generate the reference clock signals of Petrov et al. for the purpose of using art-recognized equivalent structures.
The combined teachings of Petrov and Rifani et al., as a whole, teach all the limitations of the present invention, but does not explicitly teach the switches are transistors.
Neubarth et al. teaches in Col 5, lines 20-30 npn bipolar transistors are known to “one of ordinary skill in the art having the benefit of the herein disclosure would readily recognize that any suitable switch element may be employed, such as a [bipolar NPN transistor], MOSFET, JFET, IGBT, MCT, thyristor, opto-isolator or equivalent switch element." Col. 5, lines 25-30. Thus, Neubarth et al. shows that a transistor is an equivalent structure known in the art of a switch.
Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute a switch of Petrov et al. for an equivalent transistor. Neubarth et al.: Col. 5, lines 25-30.
Rifani et al. teaches in Col. 3 “a reference clock signal, such as a bus clock” illustrates a reference clock signals and a bus clock are considered equivalent structures by one of ordinary skill in the art.
Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute a switch of Petrov et al. and Rifani et al., as a whole, for an equivalent transistor. Neubarth et al.: Col. 5, lines 25-30.
Regarding Claim 19, Petrov et al., Rifani et al., and Neubarth et al., as a whole, teach all the limitations of the present invention, wherein Petrov et al. further teaches the apparatus wherein the bus is determined to be active responsive to a bus control signal being asserted and to be inactive responsive to the bus control signal being deasserted (based on control signals received by circuitry in order to activate circuitry).
Regarding Claim 20, Petrov et al., Rifani et al., and Neubarth et al., as a whole, teach all the limitations of the present invention, wherein Petrov et al. further teaches the apparatus further comprising a phase-locked loop (PLL), the PLL including the operational amplifier and the PLL being used to generate a clock signal for the bus (where Figure 1 and Figure 2 each depict a phase-locked loop including the VCO, which outputs a clock signal; and 235, as further detailed in Figure 4).
Allowable Subject Matter
Claims 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 15, the prior art does not disclose, teach or suggest the apparatus further comprising:
a second transistor coupled in series with the first transistor and disposed between the voltage generator and the first transistor and having its source and drains shorted together;
a third transistor coupled in series with the first transistor and disposed between the first transistor and the capacitor and having its source and drain shorted together; and
wherein the second transistor and the third transistor turn on responsive to the bus being active and turn off responsive to the bus being inactive;
in combination with all the other claimed limitations.
Regarding Claim 17, the prior art does not disclose, teach or suggest the apparatus further comprising
a second capacitor having a first terminal coupled to a node between the voltage generator and the first transistor and a second terminal coupled to ground;
in combination with all the other claimed limitations.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIANA J. CHENG/ Primary Examiner, Art Unit 2849