Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9 and 17 are objected to because of the following informalities:
In Claim 9 subsequent recitation of “an artificial intelligence chip” (see lines 2-3, 4, 5, 6-7) and “an artificial intelligence accelerator” (see line 6) should be: the artificial intelligence chip, and the artificial intelligence accelerator, respectively.
In Claim 17 subsequent recitation of “an artificial intelligence chip” (see lines 4, 5-6) should be: the artificial intelligence chip.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “according to a mapping rule”. It is unclear in the claim as to what this would entail and therefore also as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The same rejection is made for Claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-13, 17-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ditty, US 2019/0258251 A1.
Regarding Claim 1, Ditty teaches:
A method for adjusting an artificial intelligence chip, comprising: determining state information indicating that an artificial intelligence accelerator on an artificial intelligence chip is in a preset state; and adjusting a working state of the artificial intelligence chip based on the state information (Fig. 8; paragraph 181: “As self-driving functionality requires a supercomputer able to perform numerous distinct functions rapidly, accurately, safely, and efficiently, no single processor can provide Level 3-5 autonomous vehicle functionality. Rather, an Advanced Platform and SoC for performing the technology preferably has multiple types of processors, providing the “right tool for the job” as well as processing diversity for functional safety. For example, GPUs are well-suited to higher precision tasks. Hardware accelerators, on the other hand, can be optimized to perform a more specific set of functions. By providing a blend of multiple processors, an Advanced Platform and SoC includes a complete set of tools able to perform the complex functions associated with Level 3-5 autonomous vehicles quickly, reliably, and efficiently”. And, paragraph 267: “the accelerators (401), (402) together perform functions (e.g., detection of imminent collision, lane departure warning, pedestrian detection) that when combined with the autonomous driving functions performed by GPU complex (300), together provides to provide ASIL D level functional safety. Furthermore, in the event of a failure of one of the accelerators (401) or (402), combination of the functioning accelerator and the GPU complex (300) together ensures safe operation. In the event of the failure of both accelerator (401) and (402), the system returns a fault message that service is required, notifies the driver, and executes a transition routine that returns control to the driver”. That is, as collectively described, several AI or ML accelerators that is part of an AI System-on-a-Chip (Soc) is used for control of autonomous vehicles, and depending on the state/failure of an accelerator an adjustment can be made for using other accelerators that is part of the SoC, thereby reflecting an adjustment of the working state of the chip based on the failed accelerators).
Regarding Claim 2, Ditty further teaches:
The method according to claim 1, wherein the adjusting a working state of the artificial intelligence chip based on the state information comprises: determining, based on the state information, a quantity of times for which the artificial intelligence accelerator is in the preset state (paragraph 426: “The diagnostics and monitoring are structured to detect any kind of failure within a fault time tolerance interval (e.g., every 100 ms)”; And, paragraph 429: “Diagnostics that will be requested dynamically in response to event occurrence, e.g., memory diagnostic after single bit error reporting exceeds a pre-set threshold, a certain number of frames are dropped in a certain amount of time, etc.”);
and in response to that the quantity of times meets a preset condition, adjusting the working state of the artificial intelligence chip from a current operating state to a target state (paragraph 267: “the accelerators (401), (402) together perform functions (e.g., detection of imminent collision, lane departure warning, pedestrian detection) that when combined with the autonomous driving functions performed by GPU complex (300), together provides to provide ASIL D level functional safety. Furthermore, in the event of a failure of one of the accelerators (401) or (402), combination of the functioning accelerator and the GPU complex (300) together ensures safe operation. In the event of the failure of both accelerator (401) and (402), the system returns a fault message that service is required, notifies the driver, and executes a transition routine that returns control to the driver”).
Regarding Claim 3, Ditty further teaches:
The method according to claim 1, wherein the determining state information indicating that an artificial intelligence accelerator on an artificial intelligence chip is in a preset state comprises: processing a to-be-processed image by using the artificial intelligence accelerator, to obtain a processing result (paragraph 171: “deep-learning infrastructure preferably receives periodic updates from Vehicle (50) including a sequence of images and the objects that the Vehicle (50) located (via computer vision or other machine learning object classification techniques) in that sequence of images”);
determining a state determining indicator corresponding to the artificial intelligence accelerator based on the processing result; and determining, based on the state determining indicator, the state information indicating that the artificial intelligence accelerator is in the preset state (paragraph 171: “Deep-learning infrastructure runs its own neural network to identify the objects and compare them with the objects identified by Vehicle (50); if the results do not match and the infrastructure concludes that the AI in the Vehicle (50) is malfunctioning, it can send a signal to Vehicle (50) instructing the fail-safe computer to assume control”).
Regarding Claim 4, Ditty further teaches:
The method according to claim 3, wherein the determining a state determining indicator corresponding to the artificial intelligence accelerator based on the processing result comprises: determining, based on the processing result, confidence of the processing result and uncertainty of an algorithm model corresponding to algorithm model instructions executed by the artificial intelligence accelerator; and determining the state determining indicator based on the confidence of the processing result and the uncertainty (paragraph 225: “The DLA may be used to run any type of network to enhance control and driving safety, including for example, a neural network that outputs a measure of confidence for each object detection. Such a confidence value may be interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. This confidence value enables the system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections”; And, “The DLA can run a neural network for regressing the confidence value”).
Regarding Claim 5, Ditty further teaches:
The method according to claim 3, wherein the adjusting a working state of the artificial intelligence chip based on the state information comprises: determining, based on the state information, a quantity of times for which the artificial intelligence accelerator is in the preset state; and in response to that the quantity of times is greater than a threshold of times, adjusting the working state of the artificial intelligence chip from a current operating state to a functional degradation state (paragraph 426: “The diagnostics and monitoring are structured to detect any kind of failure within a fault time tolerance interval (e.g., every 100 ms)”; And, paragraph 429: “Diagnostics that will be requested dynamically in response to event occurrence, e.g., memory diagnostic after single bit error reporting exceeds a pre-set threshold, a certain number of frames are dropped in a certain amount of time, etc.”).
Regarding Claim 7, Ditty further teaches:
The method according to claim 1, wherein the determining state information indicating that an artificial intelligence accelerator on an artificial intelligence chip is in a preset state comprises: determining a test vector corresponding to the artificial intelligence accelerator; testing the artificial intelligence accelerator based on the test vector, to obtain a test result; and determining, based on the test result, the state information indicating that the artificial intelligence accelerator is in the preset state (paragraph 426: “the safety watchdog monitor 5010 reports to a first level (“L1SS”) safety supervisor 5012(1) operating within its own independent virtual machine/partition 5014 on the same processor 5050 (core CPU complex or CCPLEX) that executes the application process virtual machine/partition. This first safety level L1SS safety supervisor 5012(1) may further include its own testing capabilities such as diagnostics 5016 and utilities 5018 to perform its own testing. Such diagnostics 5016 can be used for example to test hardware functionality. In some example embodiments, the L1SS safety supervisor 5012(1) also has the ability to request virtual machines/partitions 4002 to run a particular diagnostic and report results back, and to make sure that diagnostics that should be run are in fact being run. The diagnostics 5016 may be run at an appropriate rate to ensure testing is performed at sufficient frequency to guarantee that the safety supervisor 5012(1) is able to detect improper operation(s) in a timely manner”; And, paragraph 428: “Periodic Diagnostics—Diagnostics that are executed on a regular basis (usually within a Diagnostic-test Time Interval, e.g., checking critical device-configuration against golden-reference/checksums)”).
Regarding Claim 8, Ditty further teaches:
The method according to claim 1, wherein the adjusting a working state of the artificial intelligence chip based on the state information comprises: determining, based on the state information, quantities of times for which a plurality of artificial intelligence accelerators are respectively in the preset state; and in response to that a quantity of artificial intelligence accelerators, for which the quantities of times are greater than a threshold of times, exceeds a threshold of quantity, adjusting the working state of the artificial intelligence chip from a current operating state to a functional degradation state (paragraph 426: “The diagnostics and monitoring are structured to detect any kind of failure within a fault time tolerance interval (e.g., every 100 ms)”; And, paragraph 429: “Diagnostics that will be requested dynamically in response to event occurrence, e.g., memory diagnostic after single bit error reporting exceeds a pre-set threshold, a certain number of frames are dropped in a certain amount of time, etc.”. And, paragraph 267: “the accelerators (401), (402) together perform functions (e.g., detection of imminent collision, lane departure warning, pedestrian detection) that when combined with the autonomous driving functions performed by GPU complex (300), together provides to provide ASIL D level functional safety. Furthermore, in the event of a failure of one of the accelerators (401) or (402), combination of the functioning accelerator and the GPU complex (300) together ensures safe operation. In the event of the failure of both accelerator (401) and (402), the system returns a fault message that service is required, notifies the driver, and executes a transition routine that returns control to the driver”).
Claims 6 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 9-13, 15-16 are similar to Claims 1-5, 7-8 respectively and are rejected under the same rationale as stated above for those claims.
Claims 17-20 are similar to Claims 1-4 respectively and are rejected under the same rationale as stated above for those claims.
Examiner's Note:
The Examiner cites particular pages, sections, columns, line numbers, and/or paragraphs in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner and the additional related prior arts made of record that are considered pertinent to applicant's disclosure to further show the general state of the art. The Examiner's interpretations in parenthesis are provided with the cited references to assist the applicants to better understand how the examiner interprets the prior art to read on the claims. Such comments are entirely consistent with the intent and spirit of compact prosecution.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for the relevant prior art where for example Lee, US 2021/0373944 A1, teaches operating a scheduler to perform scheduling on models to be executed in an accelerator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE MISIR whose telephone number is (571)272-5243. The examiner can normally be reached M-R 8-5 pm, F some hours.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abdullah Al Kawsar can be reached at 5712703169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVE MISIR/Primary Examiner, Art Unit 2127
