DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
2. The disclosure is objected to because of the following informalities.
¶[0012] recites “FIG. 7 depicts an embodiment of a structure wherein sixteen bitlines are coupled diagonally to form a ring oscillator structure.”
¶[0029] recites in the last sentence, “FIG. 7 depicts an embodiment of a structure wherein a discharge pulse oscillates across 16 bitlines as described above.”
However, FIG. 7 illustrates a matrix of 10 word lines and 10 bit lines, with the assumed cells at the intersections each have a value of zero. It is unclear to Examiner how such a matrix can depict a structure wherein sixteen bit lines are coupled diagonally to form a ring oscillator structure.
Appropriate correction is required.
Claim Objections
3. Claim 6 is objected to because of the following informalities.
Lines 4-5 recites, “a a bitline sense signal,” which Examiner believes should recite, “[[a]] a bitline sense signal.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the discharge of a bitline” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] discharge of a bitline.” Claims 2-8 depend on claim 1.
Claim 8 recites the limitation “delay introduced by the peripheral logic” in line 3, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 7 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “the delay of the peripheral logic.”
Claim 8 recites the limitation “a delay of the peripheral logic” in lines 4-5, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 7 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[a]] the delay of the peripheral logic.”
Claim 8 recites the limitation “the delay of discharge of the bit-storing cells” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “the cumulative delay of discharge of the bit-storing cells,” which finds antecedent basis in lines 2-3.
Claim 9 recites the limitation “the discharge of a bitline” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] discharge of a bitline.” Claims 10-15 and 19-20 depend on claim 9.
Claim 11 recites the limitation “delay introduced by the peripheral logic” in line 3, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 10 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “the delay of the peripheral logic.”
Claim 11 recites the limitation “a delay of the peripheral logic” in lines 4-5, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 10 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[a]] the delay of the peripheral logic.”
Claim 11 recites the limitation “the delay of discharge of the bit-storing cells” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “the cumulative delay of discharge of the bit-storing cells,” which finds antecedent basis in lines 2-3.
Claim 16 recites the limitation “forming on the silicon wafer” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “forming on [[the]] a silicon wafer,” which shall provide antecedent basis for “the silicon wafer” in line 6. Claim 18 depends on claim 16 (see comment on claim 18 following).
Claim 16 recites the limitation “the discharge of a bitline” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] discharge of a bitline.”
Claim 16 recites the limitation “a bitline of the stage” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “a bitline of [[the]] a stage.”
Claim 17 recites the limitation “The silicon wafer manufacturing process of claim 10” in line 1. There is insufficient antecedent basis for this limitation in the claim. “The silicon wafer manufacturing process” may refer to claim 16; however, because the claim also references “the calibration logic,” which does not appear in claim 16, Examiner believes the following is intended: “The silicon wafer of claim 10.”
Claim 17 recites the limitation “delay introduced by the peripheral logic” in line 3, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 10 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “the delay of the peripheral logic.”
Claim 17 recites the limitation “a delay of the peripheral logic” in lines 4-5, which Examiner believes is the same delay as “a delay of peripheral logic” in claim 10 and is therefore indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[a]] the delay of the peripheral logic.”
Claim 17 recites the limitation “the delay of discharge of the bit-storing cells” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “the cumulative delay of discharge of the bit-storing cells,” which finds antecedent basis in lines 2-3.
Claim 18 recites the limitation “The silicon wafer manufacturing process of claim 9” in line 1. There is insufficient antecedent basis for this limitation in the claim. Because the claim also references “each stage,” which may find antecedent basis in claim 16, Examiner believes the following is intended: “The silicon wafer manufacturing process of claim [[9]] 16.”
Allowable Subject Matter
6. Claims 1-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
7. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline. Claims 2-8 depend on claim 1.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline. Claims 10-15 and 19-20 depend on claim 9. Claims 17-18 may depend on claim 9 (see related 112(b) rejection).
Regarding claim 16, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the discharge of a bitline of the stage triggers charging of a bitline of a first adjacent stage and discharging of a bitline of a second adjacent stage. Claims 17-18 may depend on claim 16 (see related 112(b) rejection).
Citation of Relevant Art
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Monzel, et al (US 20040061561 A1) teaches a circuit comprising a frequency monitor (FIG. 3, counter 302; ¶[0030] teaches “An integrated circuit where the actual count is a less than the expected count may be presumed to be operating slower than the intended design” and therefore the counter functions as a frequency monitor) coupled to a ring oscillator (FIG. 3, 300); and the ring oscillator comprising a plurality of bit-storing cells (FIG. 4, SRAM cells in dashed boxes; ¶[0043]). However, Monzel does not teach the ring oscillator is configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline.
Ecker (US 20170365332 A1) teaches a circuit (FIG. 1) comprising a frequency monitor (FIG. 1, 44; ¶[0065]) coupled to a ring oscillator, the ring oscillator comprising a plurality of bit-storing cells (FIG. 1, 36; Abstract teaches “interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells”). Ecker also teaches in FIG. 3A SRAM cells may be 8T. However, Ecker does not teach the ring oscillator is configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline.
Jungmann, et al (US 20150015274 A1) teaches a circuit (FIG. 1) comprising a frequency monitor (FIG. 1, 28; ¶[0020]) coupled to a ring oscillator (FIG. 1, 22), the ring oscillator comprising a plurality of bit-storing cells (FIG. 1, each delay stage 12 (¶[0020]) is detailed in FIG. 2 as comprising an SRAM Cell 32). Jungmann also teaches in FIG. 2 SRAM cells may be 6T. However, Jungmann does not teach the ring oscillator is configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
