DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The Specification is objected because of the following reason(s) and appropriate correction is required.
-On page 1, par. [0001]), it is unclear what application number the limitations “xx/xxx,xxx” indicate.
-On page 1, par. [0001]), missing information are required to be provided in the blanks “___”.
Claim Objections
Claims 9-17 are objected to because of the following reason(s) and appropriate correction is required.
-Claim 9, lines 6-7, recites the limitation “the control voltage”. It appears that the limitation should be changed to --the control signal—, otherwise, the limitation is lack of antecedent basis.
-Claims, depended on claim 9, are therefore also objected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 9, 10, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Upadhyaya et al (2016/0322979).
-Regarding claim 1, Upadhyaya et al teaches a method for fractional-N frequency synthesis (“wideband, low jitter fractional synthesis”, [0020]), the method (see figure 4) comprising:
generating, via (306-1), a charge-pump current (being a composite current generated in a charge-pump (“charge-pump 304”, [0036]) transferred from a circuit join node (Vx) to a current sink (Idown) through a transistor (M1), wherein the generation uses a bias signal (outputted from a differential amplifier ((402), figure 4)), generated, via the amplifier, based on a control voltage( (Vctrl (ERR)) of a voltage-controlled oscillator (“oscillator 204”, [0024]) of a phase-locked loop (“PLL 108”, [0023]) and a frequency divider value (“frequency multiplier “N.F”””, [0024]) of a frequency divider (“frequency divider 208”, [0023]) in the phase-locked loop,
in a manner that the charge-pump current, as a composite current, theorically consists of the bias signal provided to the circuit join node from the amplifier and a bias current provided to the circuit join node from a current source (Iup) of through a drain node of a transistor (M3), wherein the bias signal is generated , via the amplifier, based on the control voltage, and wherein the bias current is generated, via the transistor (M3), based on a control signal (Pup) outputted from the from a phase frequency detector (“PFD detector”, [0039]), the control signal which in turn, is generated based on an output signal of the voltage-controlled oscillator being divided by the frequency divider value of the frequency divider and being outputted from the frequency divider to the phase frequency detector, (see [0023, 0024, 0027, 0034, 0035, 0037-0041]).
-Regarding claim 2, as for claim 1, Upadhyaya et al teaches that the bias signal is generated, via the amplifier, based on the control voltage; and the bias signal is generated, also based on the frequency divider value of the phase-locked loop, in the manner that the control voltage is generated, based on a control signal (Pup , Pdn) outputted from the from the phase frequency detector (“PFD detector”, [0039]), the control signal which in turn, is generated based on an output signal of the voltage-controlled oscillator being divided by the frequency divider value of the frequency divider and being outputted from the frequency divider to the phase frequency detector, (see [0023, 0024, 0027, 0034, 0035, 0037-0041]).
-Regarding claim 4, Upadhyaya et al teaches that the method comprises: generating a second bias signal (Vnbias) for the charge pump, the bias signal corresponding, via (402, M4), to a current source (Iup) of the charge pump and the second bias signal provided from, or namely corresponding to, a current sink (Idown_rep) of the charge pump (see figure 4 and [0039, 0040, 0043]).
-Regarding claim 6, Upadhyaya et al teaches that the method comprises: generating the control voltage based on the charge-pump current and using a loop filter capacitance and a selected loop filter resistance, in a manner that the control voltage is generated as an output of a loop filter (308) comprising a loop filter capacitance of capacitors (Cp, Cz) and a selected loop filter resistance (Rz) (see figure 4, [0034]), and the control voltage is generated by being also based on the charge-pump current in the manner that the control voltage is generated, also based on the current source (Iup) of the charge-pump current (see figure 4, and [0023, 0034, 0038, 0039]).
-Regarding claim 9, Upadhyaya et al teaches a fractional-N frequency synthesizer for a synthesis (referred to (“wideband, low jitter fractional synthesis”, [0020]) comprising:
a phase-locked loop (“PLL 108”, [0023]) comprising:
a charge pump (“charge-pump 304”, [0036]) comprising: a current generation circuit (306-1), figure 4) responsive to a bias signal (being a composite current transferred from a circuit join node (Vx) to a current sink (Idown) through a transistor (M1) ; and
a voltage-controlled oscillator (“oscillator 204”, [0024]) responsive to a control signal ((Vctrl (ERR)), figure 4) ; and
a bias signal generator (comprising the circuit join node) configured to generate the bias signal based on the control signal and a frequency divider value (“frequency multiplier “N.F”””, [0024]) of a frequency divider (“frequency divider 208”, [0023]) , in a manner that the bias signal, as a composite current, theorically consists of an input signal provided from differential amplifier ((402), figure 4)) to the circuit join node and another input signal provided to the circuit join node from a drain node of a transistor (M3), wherein the input signal is generated , via the amplifier, based on the control signal, and wherein the other input signal is generated, via the transistor (M3), based on a control signal (Pup) outputted from the from a phase frequency detector (“PFD detector”, [0039]), the control signal which in turn, is generated based on an output signal of the voltage-controlled oscillator being divided by the frequency divider value of the frequency divider and being outputted from the frequency divider to the phase frequency detector,
(see figure 4 and [0023, 0024, 0027, 0034, 0035, 0037-0041]).
-Regarding claim 10, Upadhyaya et al teaches that the phase-locked loop further comprises: a loop filter (308) configured to generate the control signal, wherein the loop filter comprises: a loop filter capacitance ((Cp) and/or (Cz)); and a selectable loop filter resistance (Rz) selected for connection as shown in figure 4 (see figure 4).
-Regarding claim 16, Upadhyaya et al teaches that the bias signal generator comprises a circuit (being the amplifier) configured to generate a current (outputted from the amplifier) based on the control signal and further based on a scaling factor (=1) (referred to “unity gain buffer”, [0039]) of the amplifier (see [0039]).
-Regarding claim 17, Upadhyaya et al teaches that the charge pump comprises a digital-to-analog converter having a plurality of 2 current generation cells (M3, M1) and (M4, M2), each current generation cell of the plurality of current generation cells being responsive to the bias signal (as shown in figure 4 and [0039]) and responsive to a corresponding selection control signal (Pup) and/or (Pdn), (see figure 4 and [0037-0039]).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 3, 5, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-15 would be allowable if rewritten to overcome the objection(s), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG M PHU whose telephone number is (571)272-3009. The examiner can normally be reached 8:00-16:00.
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/PHUONG PHU/
Primary Examiner
Art Unit 2632