DETAILED ACTION
This office action is in response to the application filed on 05/07/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/07/2024, 06/03/2024, 11/11/2024 and 12/27/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claim 1. Therefore, the “a threshold value” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Figures 1-2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 10 and 15-18 are objected to because of the following informalities: Claims 1 and 10 “the reference voltage” this should be “a reference voltage”. Claims 1 and 10 line 33 “an amplified and compensated error signal” this should be “an amplified and compensated error signal”. Claim 1 “generating the first and second control signals” this should be “generating first and second control signals”. Claims 15-18 recite “the threshold value” this should be “a threshold value”. Claim Appropriate correction is required.
Claim Interpretation
In re to claims 11-17, method claims 11-17 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang US 20150229225 in view of Wu et al. Resonant Converter With Resonant-Voltage-Multiplier Rectifier and Constant-Frequency Phase-Shift Control For Isolated Buck–Boost Power Conversion.
Regarding claim 1, Jang teaches (Figures 2-3 and 8) an isolated resonant converter (Fig. 8), comprising: a transformer (Tr); a set of resonant components (Lr and Cr); a primary side full bridge circuit (sp1-sp4) having a first leg and a second leg electrically coupling an input terminal (Vin) to the transformer through the resonant component(Lr and Cr); a secondary side full bridge circuit (ss1-ss4) having a third leg and a fourth leg electrically coupling the transformer (Tr) to an output terminal (at Vo); and a control circuit (250) electrically coupled to the primary side full bridge circuit and the secondary side full bridge circuit, wherein the control circuit is configured to: detect an input voltage at the input terminal (with 205) and an output voltage at the output terminal (with 201), determine control signals for the first, second, third, and fourth legs, wherein the control signals (sp1-sp4) comprise duty ratios for at least one of the first, second, third, and fourth legs, and transmit the control signals to the primary side full bridge circuit and the secondary side full bridge circuit (see Fig. 8); wherein the control circuit (250) comprises: a sensing and scaling circuit (201 and 205) configured to receive the input and output voltages and to convert the input and output voltages into scaled input and output voltages (Vinscld and Voscld); a subtractor circuit (at 250) configured to receive the scaled output voltage (Vo) and to generate an error signal (Ve) by subtracting the scaled output voltage from the reference voltage; an error amplifier (202) configured to receive the error signal and to generate an amplified and compensated error signal (Vea); and a processor circuit (203-204 and 206-208) configured to receive the scaled input voltage and the amplified and compensated error signal (Vinscld and Vea), and to generate the control signals for the primary and secondary side full bridge circuits based on both the scaled input voltage and the amplified and compensated error signal. (For Example: Par. 35-39 and 42)
Jang does not teach determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal; wherein the isolated resonant converter is a buck converter when the amplified and compensated error signal is below a threshold value; and wherein the isolated resonant converter is a boost converter when the amplified and compensated error signal is above the threshold value.
Wu teaches (Figures 3-14) determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal (see fig. 14 the DSP generated the control signal with the phase shift modulator and the subtractor), wherein the isolated resonant converter is a buck converter (see fig. 12 and 14, buck mode) when the amplified and compensated error signal is below a threshold value (Fig. 14, Vctrl below Vm1); and wherein the isolated resonant converter is a boost converter (See fig. 12 and 14, boost mode) when the amplified and compensated error signal is above the threshold value (See fig. 14, Vctrl above Vm1). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal; wherein the isolated resonant converter is a buck converter when the amplified and compensated error signal is below a threshold value; and wherein the isolated resonant converter is a boost converter when the amplified and compensated error signal is above the threshold value, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 2, Jang teaches (Figures 2-3 and 8) the circuit.
Jang does not teach wherein the duty ratio for one of the third and fourth legs of the secondary side full bridge circuit is greater than the duty ratio for a corresponding one of the first and second legs of the primary side full bridge circuit.
Wu teaches (Figures 3-14) wherein the duty ratio for one of the third and fourth legs of the secondary side full bridge circuit (dφS) is greater (fig. 14, when in boost mode) than the duty ratio for a corresponding one of the first and second legs of the primary side full bridge circuit (dφP). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include wherein the duty ratio for one of the third and fourth legs of the secondary side full bridge circuit is greater than the duty ratio for a corresponding one of the first and second legs of the primary side full bridge circuit, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 3, Jang teaches (Figures 2-3 and 8) the circuit.
Jang does not teach wherein the duty ratios increase monotonously as the amplified and compensated error signal increases.
Wu teaches (Figures 3-14) wherein the duty ratios increase monotonously as the amplified and compensated error signal increases (see fig. 14 Vctrl signal increasing and the Duty for the buck or boost increases). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include wherein the duty ratios increase monotonously as the amplified and compensated error signal increases, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 4, Jang teaches (Figures 2-3 and 8) the circuit.
Jang does not teach wherein the duty ratios increase linearly as the amplified and compensated error signal increases.
Wu teaches (Figures 3-14) wherein the duty ratios increase (See fig. 12 and 14) linearly (duty ratio) as the amplified and compensated error signal increases (Vctrl). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include wherein the duty ratios increase linearly as the amplified and compensated error signal increases, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 5, Jang teaches (Figures 2-3 and 8) wherein the duty ratio for the other one of the third and fourth legs of the secondary side full bridge circuit is defined with respect to a turning off instant (with the delay time) of the other corresponding one of the first and second legs of the primary side full bridge circuit. (For Example: Par. 35-39 and 42)
Regarding claim 6, Jang teaches (Figures 2-3 and 8) the circuit.
Jang does not teach wherein when the amplified and compensated error signal is below the threshold value, the duty ratio for the first leg between 0.0 to 0.5 and the duty ratio for the second leg is 0.0.
Wu teaches (Figures 3-14) wherein when the amplified and compensated error signal is below the threshold value (Vctrl), the duty ratio for the first leg between 0.0 to 0.5 and the duty ratio for the second leg is 0.0 (Fig. 12 bottom left corner). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include wherein when the amplified and compensated error signal is below the threshold value, the duty ratio for the first leg between 0.0 to 0.5 and the duty ratio for the second leg is 0.0., as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 7, Jang teaches (Figures 2-3 and 8) the circuit.
Jang does not teach wherein when the amplified and compensated error signal is below the threshold value, the duty ratio for the first leg is 0.5 and the duty ratio for the second leg is between 0 and 0.5.
Wu teaches (Figures 3-14) wherein when the amplified and compensated error signal (Vctrl) is below the threshold value (Vm1), the duty ratio for the first leg is 0.5 and the duty ratio for the second leg is between 0 and 0.5 (See fig. 12 in buck mode when both are 0.5). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include wherein when the amplified and compensated error signal is below the threshold value, the duty ratio for the first leg is 0.5 and the duty ratio for the second leg is between 0 and 0.5, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Regarding claim 10, Jang teaches (Figures 2-3 and 8) a method for controlling an isolated resonant converter (Fig. 8) having one or more phases, wherein each phase comprises a transformer (TR), a set of resonant components (Cr and Lr), a primary side full bridge circuit (sp1-sp4) having a first leg and a second leg electrically coupling an input terminal (at vin) to the transformer through the resonant component (Cr and Lr), and a secondary side full bridge circuit (ss1-ss2) having a third leg and a fourth leg electrically coupling the transformer to an output terminal (at vout), the method comprising: detecting an input voltage (205) at the input terminal of the isolated resonant converter and an output voltage (Vout with 201) at the output terminal of the isolated resonant converter; determining control signals (sp1-ss4) for the first, second, third, and fourth legs, wherein the control signals comprise duty ratios for at least one of the first, second, third, and fourth legs (Sp1-ss4); transmitting the control signals to the primary side full bridge circuit and the secondary side full bridge circuit; receiving the input and output voltages and converting the input and output voltages into scaled input and output voltages (with 201 and 204); receiving the scaled output voltage and generating an error signal (Ve) by subtracting the scaled output voltage from the reference voltage (by subtractor); receiving the error signal and generating an amplified and compensated error signal (Vea); and receiving the scaled input voltage and the amplified and compensated error signal (Vin and Vo scld), and generating the first and second control signals for the primary and secondary side full bridge circuits based on both the scaled input voltage and the amplified and compensated error signal (see fig. 2-3). (For Example: Par. 35-39 and 42)
Jang does not teach determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal.
Wu teaches (Figures 3-14) determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal (see fig. 14 the DSP generated the control signal with the phase shift modulator and the subtractor). (For Example: See Section III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Jang to include determining control signals for the first, second, third, and fourth legs, based on an amplified and compensated error signal, as taught by Wu to provide zero-voltage switching for all of the active switches and reduce conduction loss.
Allowable Subject Matter
Claim 8-9 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 8; prior art of record fails to disclose either by itself or in combination: “…wherein when the amplified and compensated error signal is above the threshold value, the duty ratios for the first and second legs are 0.5, the duty ratio for the third leg is between 0.5 to 1.0 and the duty ratio for the fourth leg is 0.5.”.
Claim 9; prior art of record fails to disclose either by itself or in combination: “…wherein when the amplified and compensated error signal is above the threshold value, the duty ratios for the first and second legs are 0.5, the duty ratio for the third leg is 1.0, and the duty ratio for the fourth leg is between 0.5 to 1.0. “
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838