Prosecution Insights
Last updated: October 01, 2026
Application No. 18/657,505

OUT-OF-SPECIFICATION DETECTION

Non-Final OA §102
Filed
May 07, 2024
Priority
Dec 27, 2019 — continuation of 12/007,863
Examiner
DESTA, ELIAS
Art Unit
2857
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
908 granted / 1081 resolved
+16.0% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
26 currently pending
Career history
1105
Total Applications
across all art units

Statute-Specific Performance

§101
21.8%
-18.2% vs TC avg
§103
30.2%
-9.8% vs TC avg
§102
20.2%
-19.8% vs TC avg
§112
19.4%
-20.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1081 resolved cases

Office Action

§102
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawing The drawing filed on May 7, 2024, is accepted by the Examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim rejection – 25 U.S.C. §102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kurts et al. (U.S. Patent No. 7,222,254, hereon Kurts). In reference to claim 1: Kurts discloses a system (see Kurts, Abstract) comprising: a processor configured to have an operational frequency (see Kurts, Fig. 2, power states at high, low and shut down frequency rates); and a system condition engine configured to monitor the processor for a condition indicative of an overclocked processor, and to change a state of a fuse (see Kurts, Fig. 5, fuses to control the processor’s clock rate setting) responsive to the condition indicative of the overclocked processor (see Kurts, Fig. 3, processor 300 of detecting over-clocking). Regarding claim 2: Kurts further discloses that the operational frequency of the processor is configured to be set by a user because the processor for detecting whether or not it is over-clocked by comparing the configured clock rate setting (by the user) to the clock rate setting that is fed back from the peripheral set (see Kurts, column 2, lines 55-60). Regarding claim 3: Kurts further discloses that the operational frequency exceeds a specification because when that happens, the processor completely shuts down (see Kurts, column 5, lines 11-20). Regarding claim 4: Kurts further discloses that the system condition engine comprises circuitry (see Kurts, Fig 1, includes chipset, controller etc..). Regarding claim 5: Kurts further discloses that the circuitry comprises firmware (see Kurts, column 6, lines 58-64, are micro codes that are machine executable instruction to communicate and how to boot up and operate during execution). Regarding claim 6: Kurts further discloses that the condition indicative of the overclocked processor is a condition other than a frequency of the processor (see Kurts, column 2, lines 55-60, such as clock rate for instance). Regarding claim 7: Kurts further discloses that the fuse is a one-time writable non-volatile memory element (see Kurts, column 4, lines 12-24). Regarding claim 8: Kurts further discloses that the processor and the system condition engine are in a desktop computer (see Kurts, column 2, lines 1-20, are part of well-known components and devices). Regarding claim 9: Kurts further discloses that the processor and the system condition engine are in a laptop computer (see Kurts, column 6, line 58 to column 7, line 6, exact illustration of what a typical laptop or computer would be represented). In reference to claim 10: Kurts discloses a system (see Kurts, abstract) comprising: a processor configured to have an operational frequency (see Kurts, Fig. 2, power states at high, low and shut down frequency rates); and circuitry configured to monitor the processor for a condition indicative of an overclocked processor, and to change the state of a fuse responsive to the condition indicative of the overclocked processor (see Kurts, Fig. 5, fuses to control the processor’s clock rate setting, Fig. 3, processor 300 of detecting over-clocking). Regarding claim 11: Kurts further discloses that the operational frequency of the processor is configured to be set by a user because the processor for detecting whether or not it is over-clocked by comparing the configured clock rate setting (by the user) to the clock rate setting that is fed back from the peripheral set (see Kurts, column 2, lines 55-60). Regarding claim 12: Kurts further discloses that the operational frequency exceeds a specification because when that happens, the processor completely shut down (see Kurts, column 5, lines 11-20). Regarding claim 13: Kurts further discloses that the condition indicative of the overclocked processor is a condition other than a frequency of the processor (see Kurts, column 2, lines 55-60, such as clock rate for instance). Regarding claim 14: Kurts further discloses that the circuitry comprises firmware (see Kurts, column 6, lines 58-64, are micro codes that are machine executable instruction to communicate and how to boot up and operate during execution). Regarding claim 15: Kurts further discloses that the processor is in a desktop computer (see Kurts, column 2, lines 1-20, are part of well-known components and devices). Regarding claim 16: Kurts further discloses that the processor and the circuitry configured to monitor the processor are both located in a desktop computer (see Kurts, Figs. 1 and 2). Regarding claim 17: Kurts further discloses that in the processor is in a laptop computer (see Kurts, column 6, line 58 to column 7, line 6, exact illustration of what a typical laptop or computer would be represented). Regarding claim 18: Kurts further discloses that the processor and the circuitry configured to monitor the processor are both located in a laptop computer (see Kurts, Figs. 1 and 2). In reference to claim 19: Kurts discloses a method (see Kurts, abstract and Fig. 1) comprising: monitoring a system for a condition indicative of an overclocked processor (see Kurts, Fig. 5, fuses to control the processor’s clock rate setting, Fig. 3, processor 300 of detecting over-clocking); and changing the state of a fuse responsive to the condition indicative of the overclocked processor (see Kurts, Fig. 5, fuses to control the processor’s clock rate setting, Fig. 3, processor 300 of detecting over-clocking). Regarding claim 20: Kurts further discloses that the condition indicative of the overclocked processor is a condition other than frequency of the processor (see Kurts, column 2, lines 55-60, such as clock rate for instance). Regarding claim 21: Kurts further discloses that the method comprising receiving an input from a user indicative of an operation frequency of the processor because the processor for detecting whether or not it is over-clocked by comparing the configured clock rate setting (by the user) to the clock rate setting that is fed back from the peripheral set (see Kurts, column 2, lines 55-60). Regarding claim 22: Kurts further discloses that the input from the user is indicative of an operational frequency exceeding a specification (see Kurts, column 6, lines 24-31). Regarding claim 23: Kurts further discloses that a system condition engine is configured to monitor the processor for the condition indicative of an overclocked processor (see Kurts, column 6, lines 40-47). Regarding claim 24: Kurts further discloses that the system condition engine is configured to change the state of a fuse (see Kurts, column 5, lines 11-20). Regarding claim 25: Kurts further discloses that the processor and the fuse are in same electronic device (see Kurts, Fig. 2, includes fuse and processor). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al. (U.S. Patent No. 6,995,601) discloses a fuse state detection circuit has a reference circuit part and a fuse detection circuit part, the reference circuit part having a fuse identical to a fuse under detection. A reference voltage is between a voltage of a blown fuse under detection and a voltage of an un-blown fuse under detection, thus distinguishing a blown state of the fuse under detection from an un-blown state of the fuse under detection. Naso et al. (U.S. Patent No. 7,738,310) discloses methods, devices, and systems for operating memory devices having fuse circuits. Further, the method includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS DESTA whose telephone number is (571)272-2214. The examiner can normally be reached M-F: 8:30 to 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew M Schechter can be reached at 571-272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS DESTA/ Primary Examiner, Art Unit 2857
Read full office action

Prosecution Timeline

May 07, 2024
Application Filed
Sep 18, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.0%)
2y 9m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1081 resolved cases by this examiner. Grant probability derived from career allowance rate.

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