DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 12/17/2025. Claim 1-6 and 8-15 have been amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOFLEMING et al. [US 2022/0283948 A1] in view of RANGARAJAN et al. [US 2020/0133862 A1] and in further view of MATHEWSON et al. [US 2021/0103493 A1].
Claim 1 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “A computing apparatus comprising:” as “In Example 1, an apparatus for cache management,” [¶0064]
“a main memory;” as “Memory subsystem 620 represents the main memory of system 600” [¶0058]
“a memory controller coupled to the main memory and the system cache,” as [Fig. 5, element 523]
“the memory controller being configured to: initiate a read operation to a first cache line of the plurality of cache lines to access a first data;” as “The cache management receives a cache tag for reading data from the cache memory.” [¶0015]
“retrieve a plurality of ATs from the main memory, in response to determining that the first AT is absent in the tag cache portion of the first cache line, the plurality of ATs comprising the first AT;” as “in case of a cache miss, when data is not found in the cache, search status 560 generates a cache replacement request. In one example, in response to cache replacement request, primary tag selection 565 selects the primary lookup tag with the least number of collisions with primary tags stored in primary tag memory 580. Cache management 510 writes the selected primary lookup tag in primary tag memory 580 and the corresponding hash index in hash index memory 575.” [¶0049]
“store the plurality of ATs in a second cache line of the plurality of cache lines; and” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
CHOFLEMING does not explicitly teach a system cache comprising a plurality of cache lines, each cache line comprising a data cache portion and a tag cache portion; and
retrieve the first data from the main memory, in response to determining that the first data is absent in the data cache portion of the first cache line;
initiate a read operation to the first cache line to obtain a first allocation tag (AT) associated with the first data, the first AT configured to protect access of a memory location of the main memory for storing the first data using memory tagging;
align the first AT and the first data in a third cache line of the plurality of cache lines.
However, RANGARAJAN teaches “a system cache comprising a plurality of cache lines, each cache line comprising a data cache portion and a tag cache portion; and” as “tag cache 200 is used as a tag cache (e.g., for a data cache) that includes 4 memory banks shown as Bank 0 through Bank 3, though the cache 200 may include a different number of memory banks.” [¶0027]
“retrieve the first data from the main memory, in response to determining that the first data is absent in the data cache portion of the first cache line;” as “the data should be copied to a higher level cache or main memory before invalidating.” [¶0029]
“initiate a read operation to the first cache line to obtain a first allocation tag (AT) associated with the first data,” as “in order to perform the flush, all entries (e.g., cache lines) of the tag cache need to be read to determine the values of tag information, in order to identify which entries of the cache to flush.” [¶0007]
CHOFLEMING and RANGARAJAN are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING and RANGARAJAN before him/her, to modify the teachings of CHOFLEMING to include the teachings of RANGARAJAN with the motivation of the design depicted in FIG. 3 provides several benefits including one or more of faster access, reduced power consumption, simplified processing, etc., since the address 320 is not unnecessarily accessed. [RANGARAJAN, ¶0032]
The combination of CHOFLEMING and RANGARAJAN does not explicitly teach the first AT configured to protect access of a memory location of the main memory for storing the first data using memory tagging;
align the first AT and the first data in a third cache line of the plurality of cache lines.
However, MATHEWSON teaches “the first AT configured to protect access of a memory location of the main memory for storing the first data using memory tagging;” as “One approach for protecting against the types of memory usage errors as discussed above may be to provide allocation tags which are stored in the memory system in association with corresponding blocks of addresses.” [¶0045]
“align the first AT and the first data in a third cache line of the plurality of cache lines.” as “each Tag associated with an aligned 16 bytes of data.” [¶0118]
CHOFLEMING, RANGARAJAN and MATHEWSON are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING, RANGARAJAN and MATHEWSON before him/her, to modify the teachings of combination of CHOFLEMING and RANGARAJAN to include the teachings of MATHEWSON with the motivation of when the passed allocation tag is clean, then although it may benefit other requesters to allocate the clean allocation tag into the downstream cache, it is not essential for the entity controlling the downstream cache to do so, as the allocation tag is clean and so can be discarded without risk of losing the most up to date value of the allocation tag available in the system as a whole. [MATHEWSON, ¶0059]
Claim 2 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “initiate a read operation to the system cache to access a second data;” as “The cache management receives a cache tag for reading data from the cache memory. ” [¶0015]
“retrieve the second data from the main memory, in response to determining that the second data is absent in the system cache;” as “when all primary tags in primary tag memory 165 are compared against primary lookup tags 140 without any match, the cache management initiates cache replacement 199 processes. ” [¶0026]
“retrieve a second AT associated with a memory location of the main memory for storing the second data from the plurality of ATs stored in the second cache line of the system cache;” as “in case of a cache miss, when data is not found in the cache, search status 560 generates a cache replacement request. In one example, in response to cache replacement request, primary tag selection 565 selects the primary lookup tag with the least number of collisions with primary tags stored in primary tag memory 580. Cache management 510 writes the selected primary lookup tag in primary tag memory 580 and the corresponding hash index in hash index memory 575.” [¶0049]
“store the second AT and the second data in a fourth cache line of the system cache.” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
The combination of CHOFLEMING and RANGARAJAN does not explicitly teach align the second AT and the second data; and
However, MATHEWSON teaches “align the second AT and the second data; and” as “each Tag associated with an aligned 16 bytes of data.” [¶0118]
Claim 3 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “initiate a read operation to the system cache to access a third data;” as “The cache management receives a cache tag for reading data from the cache memory. ” [¶0015]
“retrieve a third AT associated with a memory location of the main memory for storing the third data from the plurality of ATs stored in the second cache line of the system cache; and” as “when all primary tags in primary tag memory 165 are compared against primary lookup tags 140 without any match, the cache management initiates cache replacement 199 processes. ” [¶0026]
“store the third AT and the third data in a fourth cache line of the system cache.” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
Claim 4 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “retrieve, in a single read operation, the first AT and the first data from the third cache line of the system cache.” as “a primary tag memory to store primary tags computed from a first portion of cache tags, where the first portion is less than all bits of a cache tag; and circuitry coupled to the primary tag memory to receive a cache tag for data to be read from a cache memory” [¶0064]
Claim 5 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “initiate a write operation to access a fourth data in the system cache, the write operation comprising:” as “in response to a replacement request, the circuitry is to select a first hash function of the group of hash functions used to compute the primary lookup tag with the least number of hits with the contents of the primary tag memory” [¶0066]
“updating the fourth data in a fifth cache line of the system cache; and” as “ write the primary lookup tag in the primary tag memory,” [¶0066]
“updating a fourth AT associated with a memory location of the main memory for storing the fourth data, the fourth AT stored alongside the fourth data in the fifth cache line.” as “ write the hash index associated with the first hash function in the hash index memory.” [¶0066]
Claim 6 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “initiate an evict operation to evict a sixth cache line of the system cache, the sixth cache line comprising a sixth data and a sixth AT associated with a memory location of the main memory for storing the sixth data, the evict operation comprising: writing the sixth data back to the main memory; and” as “In one example, in case of a cache miss, when data is not found in the cache, search status 560 generates a cache replacement request. In one example, in response to cache replacement request, primary tag selection 565 selects the primary lookup tag with the least number of collisions with primary tags stored in primary tag memory 580.” [¶0049]
“writing the sixth AT to the first cache line of the system cache for future memory tagging use with the sixth data.” [¶0049]
Claim 7 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “coalesce a plurality of AT write operations including the sixth AT; and write the sixth AT back to the main memory.” as “Cache write is called cache replacement when the cache memory is full and new data is going to replace some of the existing data in the cache memory.” [¶0028]
Claim 8 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 1.
Claim 9 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 2.
Claim 10 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 3.
Claim 11 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 4.
Claim 12 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 5.
Claim 13 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON under the same rationale of rejection of claim 6.
Claim 14 is rejected over CHOFLEMING, RANGARAJAN and MATHEWSON.
CHOFLEMING teaches “A computing apparatus comprising: a main memory configured to store a first data;” as “tag and metadata bits stored in SRAM are the primary tags, and the SRAM can be referred to as the primary tag memory. The tag and metadata bits stored in the DRAM are the secondary tags, and the DRAM can be referred to as the secondary tag memory.” [¶0016]
“a memory controller coupled to the main memory and the system cache,” as [Fig. 5, element 523]
“the memory controller configured to: store the first data in the data cache portion of a first cache line of the plurality of cache lines;” as “The cache management receives a cache tag for reading data from the cache memory. ” [¶0015]
“store a first allocation tag (AT) associated with the first MT data, in the tag cache portion of the first cache line,” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
“store a plurality of second ATs in a second cache line of the plurality of cache lines.” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
CHOFLEMING does not explicitly teach a system cache comprising a plurality of cache lines, each cache line comprising a data cache portion and a tag cache portion; and
the first AT configured to protect a memory location of the main memory for storing the first data; and
However, RANGARAJAN teaches “a system cache comprising a plurality of cache lines, each cache line comprising a data cache portion and a tag cache portion; and” as “tag cache 200 is used as a tag cache (e.g., for a data cache) that includes 4 memory banks shown as Bank 0 through Bank 3, though the cache 200 may include a different number of memory banks.” [¶0027]
CHOFLEMING and RANGARAJAN are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING and RANGARAJAN before him/her, to modify the teachings of CHOFLEMING to include the teachings of RANGARAJAN with the motivation of the design depicted in FIG. 3 provides several benefits including one or more of faster access, reduced power consumption, simplified processing, etc., since the address 320 is not unnecessarily accessed. [RANGARAJAN, ¶0032]
The combination of CHOFLEMING and RANGARAJAN does not explicitly teach the first AT configured to protect a memory location of the main memory for storing the first data; and
However, MATHEWSON teaches “the AT configured to protect access of the main memory and the system cache using memory tagging; and” as “One approach for protecting against the types of memory usage errors as discussed above may be to provide allocation tags which are stored in the memory system in association with corresponding blocks of addresses.” [¶0045]
CHOFLEMING, RANGARAJAN and MATHEWSON are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING, RANGARAJAN and MATHEWSON before him/her, to modify the teachings of combination of CHOFLEMING and RANGARAJAN to include the teachings of MATHEWSON with the motivation of when the passed allocation tag is clean, then although it may benefit other requesters to allocate the clean allocation tag into the downstream cache, it is not essential for the entity controlling the downstream cache to do so, as the allocation tag is clean and so can be discarded without risk of losing the most up to date value of the allocation tag available in the system as a whole. [MATHEWSON, ¶0059]
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOFLEMING et al. [US 2022/0283948 A1] in view of RANGARAJAN et al. [US 2020/0133862 A1] in further view of MATHEWSON et al. [US 2021/0103493 A1] and yet in further view of Durham et al. [US 2020/0379902 A1].
Claim 15 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Durham.
The combination of CHOFLEMING, RANGARAJAN and MATHEWSON does not explicitly teach a sub-cache portion configured to cache the plurality of second ATs in a single prefetch operation of the main memory.
However, Durham teaches “a sub-cache portion configured to cache the plurality of second ATs in a single prefetch operation of the main memory.” as “the processor can cache one tag/bounds per allocation, making caching far more effective and reducing memory lookups to fetch metadata form the midpoint of the allocation's power of two bounding box.” [¶0015]
CHOFLEMING, RANGARAJAN, MATHEWSON and Durham are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING, RANGARAJAN, MATHEWSON and Durham before him/her, to modify the teachings of combination of CHOFLEMING, RANGARAJAN and MATHEWSON to include the teachings of Durham with the motivation of architecture supports Scale-Index-Base (SIB)+displacement memory operand, which allows us to avoid branches (which can be slow) when emulating the systems and methods described above in a compiler. [Durham, ¶0049]
Claim 16 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Durham.
CHOFLEMING teaches “a cache controller configured to control access of the system cache; and” as “In response to receiving a cache access signal, controller 523 selects a cache line from cache memory 570.” [¶0048]
“a memory tagging unit (MTU) configured to implement memory tagging functions in cooperation with the cache controller using the tag cache portion, the data cache portion, and the sub-cache portion.” as “Based on the hash index stored in hash index memory 575 of the selected cache line, controller 523 selects a computed primary lookup tag to be primary lookup tag 535.” [¶0048]
Claim 17 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Durham.
The combination of CHOFLEMING, RANGARAJAN and MATHEWSON does not explicitly teach wherein the memory controller is further configured to change a size of the tag cache portion in response to caching operations of the tag cache portion.
However, Durham teaches “wherein the memory controller is further configured to change a size of the tag cache portion in response to caching operations of the tag cache portion.” as “When allocating memory, MALLOC( )/NEW will simply account for the metadata in the middle of the memory allocation, increasing the allocation size (e.g. by one byte, or two bytes, or more depending on the size of the power of two bounding box and associated metadata size), and setting the tag value in the middle of the memory allocation's power of two bounding box.” [¶0016]
Claim 18 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Durham.
CHOFLEMING teaches “retrieve the plurality of the second ATs from the second cache line, in response to a cache miss of the tag cache portion; and” as “ If the selected primary lookup tag and primary tag 166 do not match, it is a tag miss indicating that it is not possible that the selected cache line contains the data associated with memory address 105 and the cache management triggers cache miss 195.” [¶0026]
The combination of CHOFLEMING, RANGARAJAN and MATHEWSON does not explicitly teach allocate one or more of the plurality of second ATs in the tag cache portion, each second AT being allocated in a same cache line with a corresponding data.
However, Durham teaches “allocate one or more of the plurality of second ATs in the tag cache portion, each second AT being allocated in a same cache line with a corresponding data.” as “perform a memory allocation operation based on the memory allocation request to obtain a memory allocation; increase a requested memory allocation size based on the memory allocation request by at least one byte; assign tag data to memory allocated based on the memory allocation request; determine a mid-point address of the memory allocation; store the tag data and metadata at the mid-point address of the memory allocation; and communicate the tag data to the processor circuitry.” [¶0017]
Claim 19 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Durham.
CHOFLEMING teaches “retrieve the plurality of second ATs from the main memory in a single fetch operation; and” as “when all primary tags in primary tag memory 165 are compared against primary lookup tags 140 without any match, the cache management initiates cache replacement 199 processes. ” [¶0026]
“store the plurality of second ATs in the second cache line for later allocation in the tag cache portion.” as “If the cache management searched all cache lines 158 without any secondary tag hit, it starts cache replacement 199.” [¶0027]
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOFLEMING et al. [US 2022/0283948 A1] in view of RANGARAJAN et al. [US 2020/0133862 A1] in further view of MATHEWSON et al. [US 2021/0103493 A1] and yet in further view of Granovsky et al. [US 2022/0365881 A1].
Claim 20 is rejected over CHOFLEMING, RANGARAJAN, MATHEWSON and Granovsky.
The combination of CHOFLEMING, RANGARAJAN and MATHEWSON does not explicitly teach merge a plurality of AT write operations into a single operation at the system cache; or merge a plurality of AT evict operations into a single operation at the system cache.
However, Granovsky teaches “merge a plurality of AT write operations into a single operation at the system cache; or merge a plurality of AT evict operations into a single operation at the system cache.” as “ cache controller circuit 101 performs a read-modify-write operation to merge the modified second sub-portion of portion 120a with values from memory 145.” [¶0052]
CHOFLEMING, RANGARAJAN, MATHEWSON and Granovsky are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of CHOFLEMING, RANGARAJAN, MATHEWSON and Granovsky before him/her, to modify the teachings of combination of CHOFLEMING, RANGARAJAN and MATHEWSON to include the teachings of Granovsky with the motivation of a scalable solution enabling use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be beneficial. [Granovsky, ¶0096]
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MASUD K KHAN/Primary Examiner, Art Unit 2132