Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments provided on 02/05/2026 have been fully considered and are not found to place the application in a condition for allowance.
The applicant asserts that Ahn in view of Kim does not teach the amended claim 32. The Office respectfully disagrees. Ahn teaches that VGL is a fixed voltage, accordingly Kim is not relied upon to teach such a limitation. Furthermore, Ahn teaches that a first gate terminal is shorted to the node because according to Table 1 of Ahn, TA operates in a “wire mode” which provides a “shorted” connection between Q2 and Q, thereby meeting the “shorted” claim language as claimed.
As noted previously, Ahn does not teach that the fixed voltage “VGL” is greater than the power supply voltage. However, as taught by Kim, such a voltage may be varied “with the passage of driving time” in order to “reduce degradation” by applying a voltage greater than VGL. Note, however, that Kim clearly teaches that “The first and second variable high-potential voltages VDDo(t) and VDDe(t) are selectively applied to the QBo node and the QBe node after they are adjusted to gradually increase in proportion to degradation of the first and second pull-down transistors Tpdo and Tpde.” In other words, the voltage experienced by the driver within a driving frame is a constant voltage as clearly illustrated in fig. 11. Accordingly, one would have been motivated to modify the teachings of Ahn in view of Kim in order to apply a voltage greater than VGL to T4 in order to “reduce degradation of the pull-down transistor”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 32, 34, 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al., US 2023/0215381 A1, hereinafter “Ahn”, in view of Kim, US 2014/0085285 A1, hereinafter “Kim”.
Regarding claim 32, Ahn teaches a gate driver circuit comprising: a first transistor (fig. 6, T1) having a drain terminal coupled to a first power supply line on which a power supply voltage is provided (VGL), a source terminal coupled to an output port (Output) of the gate driver circuit, and a gate terminal, wherein a gate output signal is generated at the output port and is conveyed to a row of display pixels (¶ 67 and ¶ 91, note that in fig. 6, the “Output” port provides the scan signal for a row of pixels); a second transistor (fig. 6, T2) having a drain terminal coupled to the output port, a source terminal coupled to a second power supply line (VGH) different than the first power supply line, and a gate terminal; a third transistor (fig. 6, TA) having a first source-drain terminal coupled to the gate terminal of the first transistor, a gate terminal coupled to the first power supply line (¶ 124), and a second source-drain terminal shorted to a node (Q2); and a semiconducting oxide transistor (T4, note that per ¶ 136, T4 is an oxide TFT) having a source terminal configured to receive a fixed bias voltage (VGL is considered to be such a fixed bias voltage), a drain terminal coupled to the gate terminal of the second transistor (see configuration of T4), and a first gate terminal shorted to the node (note that per table 1, ¶ 124-125, the gate of TA is connected VGL which permanently turns TA on and places it in a “wiring mode”. In other words, based on the VGL connection, the TA transistor acts like a wire which means the first gate terminal of the semiconducting oxide terminal is shorted to the node).
Ahn does not specifically teach that the bias voltage is greater than the power supply voltage.
Kim teaches that a voltage sent to the QB node may be applied at a level lower than the maximum level in order to “reduce degradation” of the transistors (¶ 40).
Note that the QB node of Ahn controls a p-type transistor while the QB node of Kim controls an n-type transistor. P-type transistors are turned on by low level voltages while N-type transistors are turned on by high level voltages. Accordingly, applying the teachings of Kim to a p-type transistor similar to those of Ahn would require that a voltage greater than VGL be applied to T4 which turns on T2 by controlling the QB node.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Ahn in view of Kim. The references teach gate driving circuits and Kim further teaches details regarding the voltages applied to the QB node. One would have been motivated to make such a combination because Kim clearly teaches that such a technique can reduce degradation of the transistor being controlled by the QB node.
Regarding claim 34, Ahn teaches that the first and second transistors comprise p-type silicon transistors (fig. 6, see the symbols for the transistors, also see ¶ 135).
Regarding claim 37, Ahn teaches a fourth transistor (fig. 6, T5) having a drain terminal shorted to the gate terminal of the second transistor, a source terminal coupled to the second power supply line, and a gate terminal shorted to the node (fig. 6, see configuration of T5).
Regarding claim 38, Ahn teaches a fifth transistor (fig. 6, T3) having a first source-drain terminal shorted to the node (Q2), a second source-drain terminal configured to receive a gate output signal (GVST) from an additional gate driver circuit of a different pixel row (¶ 116; also see figs. 1-2 wherein the GVST signal is provided from a gate output signal from an additional gate driver circuit of a different pixel row; note that G1, G2, … correspond to different pixel rows), and a gate terminal configured to receive a clock signal (GCLK, ¶ 122).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn, in view of Kim, as applied above, and further in view of In.
Regarding claim 33, Ahn and Kim do not teach the semiconducting oxide transistor having a second gate terminal shorted to its source terminal.
In, however, clearly teaches that any/all transistor(s) in a stage of a gate driving circuit may include a back gate terminal shorted to its source terminal (fig. 4B, col. 27, lines 2-17).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Ahn in view of In. The references teach gate driving circuits and In further teaches that the transistors in such circuits may includes back gate terminals connected to their source electrodes. One would have been motivated to make such a combination because In clearly teaches that according to such a configuration “an operation characteristic of the transistor Tb may be stabilized” (see col. 27, lines 13-15).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn, in view of Kim, as applied above, and further in view of Um.
Regarding claim 35, Ahn teaches a first capacitor (fig. 6, CQ) having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to the output port (see fig. 6).
Ahn and Kim do not specifically teach a second capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal coupled to the second power supply line.
Um, however, teaches a second capacitor (fig. 7, CQB) having a first terminal coupled to the gate terminal of the second transistor (T8) and having a second terminal coupled to the second power supply line (VEH).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Ahn, Yu and In, as applied above, further in view of Um. The references teach gate driving circuits and Um teaches a circuit very similar to Ahn. Um further teaches including a second capacitor as claimed. One would have been motivated to make such a combination because Um clearly teaches the incorporation of such a capacitor “to stabilize the voltage of the node QB” (¶ 73).
Conclusion
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/SEPEHR AZARI/Primary Examiner, Art Unit 2621
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