Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-3, 5-13, 15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (WO 2020/177437; US 2021/0397559 is cited for English translation; hereinafter Chen) in view of Agarwal (US 2020/0012604, hereinafter Agarwal).
Regarding claim 1, Chen discloses
A method, comprising (fig. 1-8):
receiving, by a network interface card of a computing device, a data processing request (paragraph [0067]: The network interface card of the transmit-end server sends the data to a network interface card of the receive-end server) comprising first execution information of to-be-processed data (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … );
obtaining, by the network interface card and from the data processing request, the first execution information (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … );
converting, by the network interface card, the first execution information into second execution information (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor);
sending, by the network interface card and to … the computing device, the second execution information (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor);
invoking, … , a processor of the computing device to process the second execution information; and processing, by the processor and based on the second execution information, the to-be-processed data (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor. The information about the QP may be stored in the memory of the processor or in the buffer of the network interface card of the receive-end server; paragraph [0134]: the processor 801 may be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits configured to control program execution in the solutions of this application).
Chen does not disclose sending, by the network interface card and to a processor scheduling engine of the computing device, the second execution information; invoking, by the processor scheduling engine, a processor of the computing device to process the second execution information. Agarwal discloses sending, by the network interface card and to a processor scheduling engine of the computing device, the second execution information; invoking, by the processor scheduling engine, a processor of the computing device to process the second execution information; and processing, by the processor and based on the second execution information, the to-be-processed data (paragraph [0017]: device 105 may be an accelerator or processor device coupled to host processor 145 via an interconnect 189; paragraph [0026]: In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device; paragraph [0027]: In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block 240 where the write request can be directly sent to the device for writing into the device memory; paragraph [0028]: otherwise if it is determined that the address is not in device memory, control passes to diamond 250 to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s sending, from RDMA NIC, command including an address and a pointer of an RQ based on the information about the QP included in a data header to processor by Agarwal’s sending, by coherence circuitry, allocating or non-allocating command including cache memory address into a cache memory of the host processor or a command to another processor device if the destination address is matched after receiving a request from RDMA NIC. The motivation would have been to improve performance by having automatic selection of destination of incoming RDMA transactions (Agarwal paragraph [0031]).
Regarding claim 7 referring to claim 1, Chen discloses A network interface card, comprising: a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions to: … (Fig. 7).
Regarding claim 10, Chen discloses
A computing device, comprising (fig. 1-8):
a network interface card configured to: receive a data processing request (paragraph [0067]: The network interface card of the transmit-end server sends the data to a network interface card of the receive-end server) comprising first execution information of to-be-processed data (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … );
obtain, from the data processing request, the first execution information (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … );
convert the first execution information into second execution information (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor);
send the second execution information (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor);
a processor … coupled to the network interface card and configured to: receive, from the network interface card, the second execution information, wherein the second execution information instructs … to schedule (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor. The information about the QP may be stored in the memory of the processor or in the buffer of the network interface card of the receive-end server; paragraph [0134]: the processor 801 may be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits configured to control program execution in the solutions of this application).
Chen does not disclose a processor scheduling engine coupled to the network interface card and configured to: receive, from the network interface card, the second execution information, wherein the second execution information instructs the processor scheduling engine to schedule a second processor; and schedule, based on the second execution information, the second processor to process the to-be-processed data; and the second processor coupled to the processor scheduling engine and configured to process, based on being scheduled by the processor scheduling engine, the to-be-processed data. Agarwal discloses a processor scheduling engine coupled to the network interface card and configured to: receive, from the network interface card, the second execution information, wherein the second execution information instructs the processor scheduling engine to schedule a second processor; and schedule, based on the second execution information, the second processor to process the to-be-processed data; and the second processor coupled to the processor scheduling engine and configured to process, based on being scheduled by the processor scheduling engine, the to-be-processed data (paragraph [0017]: device 105 may be an accelerator or processor device coupled to host processor 145 via an interconnect 189; paragraph [0026]: In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device; paragraph [0027]: In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block 240 where the write request can be directly sent to the device for writing into the device memory; paragraph [0028]: otherwise if it is determined that the address is not in device memory, control passes to diamond 250 to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s sending, from RDMA NIC, command including an address and a pointer of an RQ based on the information about the QP included in a data header to processor by Agarwal’s sending, by coherence circuitry, allocating or non-allocating command including cache memory address into a cache memory of the host processor or a command to another processor device if the destination address is matched after receiving a request from RDMA NIC. The motivation would have been to improve performance by having automatic selection of destination of incoming RDMA transactions (Agarwal paragraph [0031]).
Regarding claims 2 and 13, Chen discloses
wherein the to-be-processed data is to-be-executed code, wherein the first execution information comprises a first storage address of the to-be-executed code, and wherein processing the to-be-processed data comprises: obtaining, by the processor and based on the first storage address, the to-be-executed code; and executing, by the processor, the to-be-executed code (paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor. The information about the QP may be stored in the memory of the processor or in the buffer of the network interface card of the receive-end server; paragraph [0134]: the processor 801 may be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits configured to control program execution in the solutions of this application).
Regarding claim 3, Chen does not disclose wherein obtaining the to-be-executed code comprises obtaining, by the processor, from another computing device connected to the computing device, and based on the first storage address, the to-be-executed code. Agarwal discloses wherein obtaining the to-be-executed code comprises obtaining, by the processor, from another computing device connected to the computing device, and based on the first storage address, the to-be-executed code (paragraph [0017]: device 105 may be an accelerator or processor device coupled to host processor 145 via an interconnect 189; paragraph [0026]: In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device; paragraph [0027]: In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block 240 where the write request can be directly sent to the device for writing into the device memory; paragraph [0028]: otherwise if it is determined that the address is not in device memory, control passes to diamond 250 to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s sending, from RDMA NIC, command including an address and a pointer of an RQ based on the information about the QP included in a data header to processor by Agarwal’s sending, by coherence circuitry, a command to another processor device if the destination address is matched after receiving a request from RDMA NIC. The motivation would have been to improve performance by having automatic selection of destination of incoming RDMA transactions (Agarwal paragraph [0031]).
Regarding claim 5, Chen discloses
wherein the data processing request is carried in an execution command in a remote direct memory access (RDMA) protocol (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … ).
Regarding claim 6, Chen discloses
wherein the execution command is defined in a custom field of a transport layer in the RDMA protocol (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … ; paragraph [0035]: the protocol stack may include an application layer, a transport layer, a network layer, a link layer, and a physical layer. A function of the application layer may be implemented at the software layer. Functions of the transport layer, the network layer, the link layer, and the physical layer may be implemented in the network interface card).
Regarding claims 8 and 11, Chen discloses
wherein the data processing request is carried in an execution command in a remote direct memory access (RDMA) protocol, and wherein the execution command instructs the network interface card to process the data processing request (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … ).
Regarding claims 9 and 12, Chen discloses
wherein the execution command is defined in a custom field of a transport layer in the RDMA protocol (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … ; paragraph [0035]: the protocol stack may include an application layer, a transport layer, a network layer, a link layer, and a physical layer. A function of the application layer may be implemented at the software layer. Functions of the transport layer, the network layer, the link layer, and the physical layer may be implemented in the network interface card).
Regarding claim 15, Chen does not disclose wherein the computing device further comprises a host connected to the network interface card, and wherein the host comprises the second processor and the processor scheduling engine. Agarwal discloses wherein the computing device further comprises a host connected to the network interface card, and wherein the host comprises the second processor and the processor scheduling engine (paragraph [0017]: device 105 may be an accelerator or processor device coupled to host processor 145 via an interconnect 189; paragraph [0026]: In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device; paragraph [0027]: In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block 240 where the write request can be directly sent to the device for writing into the device memory; paragraph [0028]: otherwise if it is determined that the address is not in device memory, control passes to diamond 250 to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s sending, from RDMA NIC, command including an address and a pointer of an RQ based on the information about the QP included in a data header to processor by Agarwal’s sending, by coherence circuitry, allocating or non-allocating command including cache memory address into a cache memory of the host processor after receiving a request from RDMA NIC. The motivation would have been to improve performance by having automatic selection of destination of incoming RDMA transactions (Agarwal paragraph [0031]).
Regarding claim 17, Chen does not disclose wherein the computing device is configured to connect to another computing device for storage of the to-be-processed data. Agarwal discloses wherein the computing device is configured to connect to another computing device for storage of the to-be-processed data (paragraph [0017]: device 105 may be an accelerator or processor device coupled to host processor 145 via an interconnect 189; paragraph [0026]: In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device; paragraph [0027]: In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block 240 where the write request can be directly sent to the device for writing into the device memory; paragraph [0028]: otherwise if it is determined that the address is not in device memory, control passes to diamond 250 to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s sending, from RDMA NIC, command including an address and a pointer of an RQ based on the information about the QP included in a data header to processor by Agarwal’s sending, by coherence circuitry, a command to another processor device if the destination address is matched after receiving a request from RDMA NIC. The motivation would have been to improve performance by having automatic selection of destination of incoming RDMA transactions (Agarwal paragraph [0031]).
Regarding claim 18, Chen discloses
wherein the network interface card is configured to obtain the first execution information by parsing the data processing request (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0057] After receiving the ith PCIe packet sent by the processor of the transmit-end server, the network interface card of the transmit-end server parses the ith PCIe packet to obtain the jth instruction segment and the first address segment; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header … ).
Regarding claim 19, Chen discloses
wherein the network interface card is configured to convert the first execution information into the second execution information by encapsulating the first execution information. (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor; qp number in a data header is inherently encapsulated (or added) by the relevant information such as qp context (or QP), address and a pointer of the RQ to be sent to the memory of processor to access the specific region of the memory).
Regarding claim 20, Chen discloses
wherein the second execution information comprises a descriptor (paragraph [0033]: The network interface card may be a network interface card that supports the RDMA technology; paragraph [0070]: After receiving the data, the network interface card of the receive-end server may read a qp number in a data header, and then read information (which may also be referred to as qp context) about a corresponding QP based on the qp number, obtain an address and a pointer of an RQ based on the information about the QP, and then read the RQE from a memory of a processor).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Agarwal as applied to claim 10, and further in view of Ben-Ishay et al. (US 2023/0010150, hereinafter Ben-Ishay).
Regarding claim 16, Chen in view Agarwal does not disclose wherein the computing device comprises a data processing unit (DPU). Ben-Ishay discloses wherein the computing device comprises a data processing unit (DPU) (paragraph [0019]: the DPU processor exposes to the host, over the PCIe bus, a dedicated PCIe device that emulates the NVMe protocol.; paragraph [0020]: the NIC in the DPU transfers the data of the NVMe and NVMe-over-TCP transactions directly between the remote storage device and a memory of the host, using zero-copy transfer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chen in view Agarwal by implementing DPU of Ben-Ishay. The motivation would have been to reduce latency and improving throughput. (Ben-Ishay paragraph [0022]).
Allowable Subject Matter
Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Chen et al. (US 2023/0038051) discloses “the first coprocessor may include a task scheduling engine (TSE). The task scheduling engine stores program code. When determining, based on the mapping relationship, the first storage address used to store the first data, the first coprocessor may run the program code stored in the task scheduling engine to determine, based on the mapping relationship, the first storage address of the first storage space used to store the first data” (paragraph [0011]) and “the first coprocessor may run the program code in the task scheduling engine to determine, based on the mapping relationship, the second storage address used to store the second data” (paragraph [0018]).
Jung et al. (US 2023/0007080) discloses “The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card” (abstract).
Frishman et al. (US 10,846,242) discloses “operating modes 308 can include a table or other data structure indexed by transaction or protocol type which may define a base value and size value for each protocol type and packet type combination. For example, protocol type RDMA can include context and descriptor packets” (col. 4, lines 55-60).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 8/17/2026
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