Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first-inventor-to-file provisions of the AIA .
DETAILED ACTION
2. This Office action is in response to the application filed May 8, 2024. Claims 1–20 are pending and are examined on the merits herein.
Status of the Claims
3. Claims 1–20 are pending. Claims 1–20 are rejected. No claim is presently allowed. The rejections are set forth below.
Priority / Benefit of Prior-Filed Application
4. Applicant’s claim for the benefit of prior-filed Provisional Application No. 63/469,843, filed May 31, 2023, under 35 U.S.C. 119(e) is acknowledged.
However, claims 1–20 are not entitled to the benefit of the May 31, 2023 provisional filing date because Provisional Application No. 63/469,843 does not provide adequate written-description support under 35 U.S.C. 112(a) for the complete subject matter now claimed. Although the provisional application generally discloses a switched-capacitor input providing galvanic isolation and depicts switches and capacitors in Figure 1, it does not describe synchronously operating high-voltage-domain and low-voltage-domain switch groups at a frequency as recited in independent claim 1; a controller synchronously operating the switch groups at a frequency to charge respective capacitors and transfer a differential voltage signal component from a high-voltage domain to a low-voltage domain as recited in independent claim 10; or a controller synchronously operating the switch groups at a frequency to provide galvanic isolation and transfer the differential voltage signal component between the voltage domains as recited in independent claim 13. Because claims 2-9, 11-12, and 14-20 depend directly or indirectly from independent claims 1, 10, or 13, respectively, the effective filing date of the present nonprovisional application. Gammie (US 2022/0376666 A1) was published November 24, 2022, more than one year before the May 8, 2024 effective filing date. The exception under 35 U.S.C. 102(b)(1)(A) therefore does not apply, and Gammie qualifies as prior art under 35 U.S.C. 102(a)(1) notwithstanding the common inventor and common assignee. The common-ownership exception under 35 U.S.C. 102(b)(2)(C) does not apply because Gammie is relied upon as a printed publication under 35 U.S.C. 102(a)(1).
Claim Rejections — 35 U.S.C. 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7, 9, 10, 12, 19, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Regarding claims 9 and 20:
Claim 9 recites that positive and negative output signals indicate a direction of current, but neither claim 9 nor parent claim 1 introduces the current whose direction is indicated. Claim 20 contains the same ambiguity relative to parent claim 13. It is therefore unclear what current is referenced and what relationship must exist between that current and the claimed output signal.
Regarding claim 10:
The claim recites “the plurality of input switches” and “the plurality of output switches”. There is insufficient antecedent basis for these limitations in the claim.
Claim 10 previously introduces “a plurality of high voltage domain switches” and “a plurality of low voltage domain switches,” rather than a plurality of input switches and a plurality of output switches. Therefore, it is unclear whether the claimed input and output switches refer to the previously recited high- and low-voltage-domain switches or to different switches.
Regarding claims 7, 12, and 19:
Claim 7 recites “a plurality of low voltage domain switches” although claim 1 previously introduced such switches, leaving ambiguity as to whether the same or an additional plurality is intended. Claims 7, 12, and 19 also recite that a switch “is” the common-mode voltage when OFF. A switch itself cannot be a voltage, and the claims do not identify which gate, source, terminal, or node is intended to be at the common-mode voltage. The scope of the claimed OFF/ON voltage relationship is therefore unclear.
Claim Rejections — 35 U.S.C. 102
6. The following is a quotation of 35 U.S.C. 102(a)(1):
A person shall be entitled to a patent unless—(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Gammie (US 2022/0376666 A1, hereinafter “Gammie”).
Regarding claim 1:
Gammie discloses a method comprising: providing an operative coupling comprising an input stage and an output stage between an analog input and an analog output (operative coupling 106/200/400 between the voltage input across resistor 102/414 and differential amplification circuit 104/300; ¶¶ 30–36 and 43–49; FIGS. 1–4); synchronously operating a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the plurality of switches of the input stage and a plurality of output plates respectively connected to the plurality of switches of the output stage (second switches 216/412 on the V1/V2 capacitor side and first switches 214/410 on the VCCM/amplifier side are synchronously operated by control signals from logic circuit 416 at substantially 200 MHz or higher; ¶¶ 35–42 and 45–56; FIGS. 2 and 4); supplying an analog input signal to the input stage (voltages V1 and V2 across resistor 102/414; ¶¶ 30–31 and 48; FIGS. 1 and 4); transferring a differential voltage signal component within a range of a common mode voltage signal component from the high voltage domain of the input stage to the low voltage domain of the output stage (the V1/V2 capacitor side constitutes the high voltage domain and the VCCM/amplifier side constitutes the low voltage domain, and the worked example transfers a 10 mV differential component centered near 60 V to a 20 mV differential component centered near 2 V while isolating the DC common-mode component; ¶¶ 42, 55–56, and 58; FIGS. 5 and 6); differentially amplifying the low voltage domain differential voltage signal component (differential amplification circuit 300; ¶¶ 43–44; FIG. 3); and outputting an analog output signal (output of differential amplification circuit 300; ¶ 44; FIG. 3). Thus, Gammie discloses every limitation of claim 1.
Regarding claim 2:
Claim 2 further recites that “the frequency is greater than or equal to 100 MHz.” Gammie discloses switching at substantially 200 MHz or higher, which is greater than or equal to 100 MHz (¶ 40).
Regarding claim 6:
Claim 6 further recites that “synchronously operating comprises charging the plurality of capacitors.” Gammie discloses that capacitors 204/206 and C1–C4 are charged during complementary integration and transfer phases produced by the coordinated switching operation (¶¶ 38–40 and 50–55; FIGS. 4 and 5).
Regarding claim 8:
Claim 8 further recites that “the analog input signal comprises a voltage.” Gammie discloses that the analog input comprises voltages V1 and V2 representing the voltage across resistor 102/414 (¶¶ 30–31 and 48; FIGS. 1 and 4).
Claim Rejections — 35 U.S.C. 103
7. The following is a quotation of 35 U.S.C. 103:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains.
Claims 4, 5, 10, 11, 13, 14, 16, 17, and 18 — Gammie in view of Wynne
Claims 4, 5, 10, 11, 13, 14, 16, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Wynne et al. (US 7,288,940 B2, hereinafter “Wynne”).
Regarding claim 4:
Claim 4 further recites that “the common mode voltage signal component is +/-100 volts.” Gammie discloses operation at a 60 V common-mode voltage but does not expressly disclose a common-mode voltage signal component of +/-100 V.
Wynne teaches a galvanically isolated analog signal-conditioning/current-sensing system in which the common-mode voltage may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40).
It would have been obvious to configure Gammie’s switched-capacitor coupling for a common-mode voltage signal component of +/-100 V because Wynne teaches that bipolar common-mode operation in the hundreds-of-volts range is useful for isolated differential sensing. Selecting +/-100 V within Wynne’s taught operating range would predictably extend Gammie to higher-voltage current-sensing applications.
Regarding claim 5:
Claim 5 further recites that “the range of a common mode voltage signal component is +/-100 volts.” Gammie discloses operation at a 60 V common-mode voltage but does not expressly disclose the claimed +/-100 V common-mode range.
Wynne teaches a galvanically isolated analog signal-conditioning/current-sensing system in which the common-mode voltage may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40).
It would have been obvious to configure Gammie’s switched-capacitor coupling to operate within the claimed +/-100 V common-mode range because Wynne teaches bipolar common-mode operation over a range of several hundred volts or higher for isolated differential sensing. Selecting the claimed +/-100 V range would have been a predictable use of Wynne’s taught operating range in Gammie’s current-sensing circuit.
Regarding claim 10:
Gammie discloses input terminals to receive an analog input signal (voltages V1 and V2 across resistor 102/414; ¶¶ 30–31 and 48; FIGS. 1 and 4); an operative coupling comprising an input stage coupled to the input terminals and comprising a plurality of high voltage domain switches, and an output stage comprising a plurality of low voltage domain switches and a voltage common mode power source (second switches 216/412 on the V1/V2 side, first switches 214/410 on the VCCM/amplifier side, and controlled common-mode voltage source 208/420; ¶¶ 35–40 and 45–49; FIGS. 2 and 4); a plurality of capacitors having input plates respectively connected to the high voltage domain switches and output plates respectively connected to the low voltage domain switches (capacitors 204/206 and C1–C4 coupled between switches 216/412 and 214/410; ¶¶ 35–37 and 45–49; FIGS. 2 and 4); and a controller to synchronously operate the input and output switches at a frequency to charge respective capacitors (logic circuit 416 generates coordinated control signals for complementary integration and transfer at substantially 200 MHz or higher; ¶¶ 39–40, 46, and 50–55; FIG. 4).
Gammie further discloses that the operative coupling transfers a differential voltage signal component from a high voltage domain to a low voltage domain (the V1/V2 capacitor side transfers Vdiff to nodes 406 and 408 on the VCCM/amplifier side; ¶¶ 31–32, 38, 42, 50–58; FIGS. 4–6); a differential amplification circuit coupled to the output stage to amplify the transferred differential voltage signal component (differential amplification circuit 104/300; ¶¶ 30–32 and 43–44; FIGS. 1 and 3); and output terminals coupled to the differential amplification circuit to output an analog output signal (¶ 44; FIG. 3). Gammie does not expressly disclose that the complete circuit is a monolithic integrated circuit.
Wynne teaches implementing the signal-conditioning circuit and MEMS switching device on one and the same integrated-circuit chip using semiconductor processes (col. 2, ll. 47–63).
It would have been obvious to implement Gammie’s complete switched-capacitor circuit on one integrated-circuit chip as taught by Wynne to obtain the expressly identified benefits of a small, compact, less expensive device with reduced external interconnections.
Regarding claim 13:
Gammie discloses input terminals to receive an analog input signal (voltages V1 and V2 across resistor 102/414; ¶¶ 30–31 and 48; FIGS. 1 and 4); an operative coupling comprising an input stage coupled to the input terminals and comprising a plurality of high voltage domain switches, and an output stage comprising a plurality of low voltage domain switches and a voltage common mode power source (second switches 216/412 on the V1/V2 side, first switches 214/410 on the VCCM/amplifier side, and controlled common-mode voltage source 208/420; ¶¶ 35–40 and 45–49; FIGS. 2 and 4); and a plurality of capacitors having input plates respectively connected to the high voltage domain switches and output plates respectively connected to the low voltage domain switches (capacitors 204/206 and C1–C4; ¶¶ 35–37 and 45–49; FIGS. 2 and 4).
Gammie further discloses a controller to synchronously operate the high and low voltage domain switches at a frequency to galvanically isolate the input stage from the output stage and transfer a differential voltage signal component within a range of a common mode voltage signal component from the high voltage domain to the low voltage domain (logic circuit 416 synchronously controls the switches at substantially 200 MHz or higher to transfer Vdiff from the V1/V2 capacitor side to nodes 406 and 408 on the VCCM/amplifier side while capacitively isolating the DC common-mode component; ¶¶ 39–42, 46, and 50–58; FIGS. 4–6); a differential amplification circuit coupled to the output stage (differential amplification circuit 104/300; ¶¶ 30–32 and 43–44; FIGS. 1 and 3); and output terminals coupled to the differential amplification circuit to output an analog output signal (¶ 44; FIG. 3).
Gammie does not expressly disclose that the complete circuit is a monolithic integrated circuit.
Wynne teaches implementing the signal-conditioning circuit and MEMS switching device on one and the same integrated-circuit chip using semiconductor processes (col. 2, ll. 47–63).
It would have been obvious to implement Gammie’s complete switched-capacitor circuit on one integrated-circuit chip as taught by Wynne to obtain the expressly identified benefits of a small, compact, less expensive device with reduced external interconnections.
Regarding claim 11
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 10 for the reasons discussed above. Claim 11 further recites that “the frequency is greater than or equal to 100 MHz.” Gammie discloses synchronously operating the switches at substantially 200 MHz or higher, which is greater than or equal to 100 MHz (¶ 40). Accordingly, the Gammie–Wynne combination teaches each limitation of claim 11.
Regarding claim 14:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Claim 14 further recites that “the frequency is greater than or equal to 100 MHz.” Gammie discloses synchronously operating the switches at substantially 200 MHz or higher, which is greater than or equal to 100 MHz (¶ 40). Accordingly, the Gammie–Wynne combination teaches each limitation of claim 14.
Regarding claim 18:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Claim 18 further recites that “the controller is to charge the plurality of capacitors.” Gammie discloses logic circuit 416 controlling switches S1–S16 so that capacitors C1–C4 alternately integrate and transfer charge during complementary phases (¶¶ 46 and 50–55; FIG. 4). Accordingly, the Gammie–Wynne combination teaches each limitation of claim 18.
Regarding claim 16:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Claim 16 further recites that “the common mode voltage signal component is +/-100 volts.” Gammie discloses operation at a 60 V common-mode voltage but does not expressly disclose a common-mode voltage signal component of +/-100 V.
Wynne teaches that the common-mode voltage in its galvanically isolated analog signal-conditioning/current-sensing system may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40).
It would have been obvious to configure the Gammie–Wynne circuit for a common-mode voltage signal component of +/-100 V because Wynne teaches bipolar common-mode operation in the hundreds-of-volts range for isolated differential sensing. Selecting +/-100 V within Wynne’s taught operating range would predictably extend the circuit to higher-voltage current-sensing applications.
Regarding claim 17:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Claim 17 further recites that “the range of a common mode voltage signal component is +/-100 volts.” Gammie discloses operation at a 60 V common-mode voltage but does not expressly disclose the claimed +/-100 V common-mode range.
Wynne teaches that the common-mode voltage may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40).
It would have been obvious to configure the Gammie–Wynne circuit to operate within the claimed +/-100 V common-mode range because Wynne teaches bipolar common-mode operation over a range of several hundred volts or higher for isolated differential sensing. Selecting the claimed +/-100 V range would have been a predictable use of Wynne’s taught operating range in the monolithic Gammie–Wynne current-sensing circuit.
Claims 3 and 15 — Gammie in view of Wynne and Dong
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Wynne and further in view of Dong et al. (US 8,198,951 B2, hereinafter “Dong”).
Regarding claim 3:
Claim 3 further recites that “the common mode voltage signal component is +/-1000 volts.” Gammie discloses the switched-capacitor differential-sensing architecture and operation at a 60 V common-mode voltage but does not expressly disclose a common-mode voltage signal component of +/-1000 V.
Wynne teaches that the common-mode voltage in a galvanically isolated analog sensing system may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40). Dong further teaches an on-chip capacitive isolation structure capable of providing 2,500–5,000 V of isolation, including approximately 2,500 V across each capacitive interface (col. 9, ll. 10–23; FIG. 11).
It would have been obvious to configure the Gammie–Wynne analog isolation circuit for a common-mode voltage signal component of +/-1000 V because Wynne teaches positive and negative common-mode operation at several hundred volts or higher, and Dong demonstrates that an on-chip capacitive barrier can provide an isolation-withstand capability exceeding 1000 V. Selecting +/-1000 V and using Dong’s higher-voltage capacitive isolation structure would predictably provide sufficient isolation margin for higher-voltage current-sensing applications while retaining Gammie’s differential-signal transfer.
Regarding claim 15:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Claim 15 further recites that “the common mode voltage signal component is +/-1000 volts.” Gammie discloses operation at a 60 V common-mode voltage but does not expressly disclose a common-mode voltage signal component of +/-1000 V.
Wynne teaches that the common-mode voltage in a galvanically isolated analog sensing system may be several hundred volts or higher and may be positive or negative relative to ground (col. 1, ll. 25–40). Dong further teaches an on-chip capacitive isolation structure capable of providing 2,500–5,000 V of isolation, including approximately 2,500 V across each capacitive interface (col. 9, ll. 10–23; FIG. 11).
It would have been obvious to configure the monolithic Gammie–Wynne circuit for a common-mode voltage signal component of +/-1000 V because Wynne teaches positive and negative common-mode operation at several hundred volts or higher, and Dong demonstrates that an on-chip capacitive barrier can provide an isolation-withstand capability exceeding 1000 V. Selecting +/-1000 V and using Dong’s higher-voltage capacitive isolation structure would predictably provide sufficient isolation margin for higher-voltage current-sensing applications while retaining Gammie’s differential-signal transfer.
Claim 7 — Gammie in view of Troutman
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Troutman et al. (US 6,300,796 B1, hereinafter “Troutman”). For purposes of examination under the prior art, the limitation requiring a switch to be “the common mode voltage when OFF and at least three volts lower than the common mode voltage when ON” is interpreted as referring to the gate/control voltage of the switch. This interpretation is made solely for purposes of applying the prior art and does not withdraw the rejection under 35 U.S.C. 112(b).
Gammie discloses coordinated operation of the high-voltage-domain and low-voltage-domain switch groups but does not expressly disclose the claimed OFF/ON gate-control-voltage relationship.
Troutman teaches a high-voltage PMOS level shifter referenced to a 16–20 V high rail (col. 3, ll. 53–67). Troutman further teaches that the PMOS devices are OFF when their gate voltage is at the 20 V high rail (col. 5, ll. 5–14) and ON when their gate voltage is pulled to 0 V while their source/substrate remains at 20 V (col. 4, ll. 1–13 and 60–67). Thus, Troutman teaches an ON gate voltage that is at least three volts below its high-side reference rail.
It would have been obvious to use Troutman’s high-voltage PMOS level shifter to drive Gammie’s high-voltage-domain switches, with Troutman’s high-side reference rail referenced to the floating common-mode potential of Gammie’s high-voltage domain. This would cause the gate/control voltage to equal the high-side common-mode rail when OFF and to be driven at least three volts below that rail when ON, thereby providing reliable switch control without exceeding device voltage limits.
Claims 12 and 19 — Gammie in view of Wynne and Troutman
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Wynne and further in view of Troutman.
Regarding claim 12:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 10 for the reasons discussed above. Claim 12 further recites that the controller synchronously operates the high-voltage-domain and low-voltage-domain switches so that a respective switch is “the common mode voltage when OFF and at least three volts lower than the common mode voltage when ON.”
For purposes of examination under the prior art, this limitation is interpreted as referring to the gate/control voltage of the respective switch. This interpretation is made solely for purposes of applying the prior art and does not withdraw the rejection under 35 U.S.C. 112(b).
Troutman teaches a high-voltage PMOS level shifter referenced to a 16–20 V high rail (col. 3, ll. 53–67). Troutman further teaches that the PMOS devices are OFF when their gate voltage is at the 20 V high rail (col. 5, ll. 5–14) and ON when their gate voltage is pulled to 0 V while their source/substrate remains at 20 V (col. 4, ll. 1–13 and 60–67). Thus, Troutman teaches an ON gate voltage that is at least three volts below its high-side reference rail.
It would have been obvious to incorporate Troutman’s level-shifted PMOS gate drive into the monolithic Gammie–Wynne circuit, with Troutman’s high-side reference rail referenced to the floating common-mode potential of Gammie’s high-voltage domain. This would cause the gate/control voltage to equal the high-side common-mode rail when OFF and to be driven at least three volts below that rail when ON, thereby providing reliable switch control without exceeding device voltage limits.
Regarding claim 19:
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Gammie additionally teaches the capacitor-charging limitation of claim 18, from which claim 19 depends (¶¶ 46 and 50–55; FIG. 4). Claim 19 further recites that a respective switch is “the common mode voltage when OFF and at least three volts lower than the common mode voltage when ON.” For purposes of examination under the prior art, this limitation is interpreted as referring to the gate/control voltage of the respective switch. This interpretation is made solely for purposes of applying the prior art and does not withdraw the rejection under 35 U.S.C. 112(b).
Troutman teaches a high-voltage PMOS level shifter referenced to a 16–20 V high rail (col. 3, ll. 53–67). Troutman further teaches that the PMOS devices are OFF when their gate voltage is at the 20 V high rail (col. 5, ll. 5–14) and ON when their gate voltage is pulled to 0 V while their source/substrate remains at 20 V (col. 4, ll. 1–13 and 60–67). Thus, Troutman teaches an ON gate voltage that is at least three volts below its high-side reference rail.
It would have been obvious to incorporate Troutman’s level-shifted PMOS gate drive into the monolithic Gammie–Wynne circuit, with Troutman’s high-side reference rail referenced to the floating common-mode potential of Gammie’s high-voltage domain. This would cause the gate/control voltage to equal the high-side common-mode rail when OFF and to be driven at least three volts below that rail when ON, thereby providing reliable switch control without exceeding device voltage limits.
Claim 9 — Gammie in view of Chao
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Chao et al. (US 9,213,351 B2, hereinafter “Chao”). For purposes of examination under the prior art, “current” is interpreted as the sensed current associated with Gammie’s current-sensing application, and the positive and negative output signals are interpreted relative to the claimed reference signal, corresponding to Gammie’s pedestal voltage. This interpretation is made solely for purposes of applying the prior art and does not withdraw the rejection under 35 U.S.C. 112(b).
Gammie discloses an output referenced to a pedestal voltage and applies its circuit to current sensing (¶¶ 44 and 59–61), but does not expressly disclose that positive and negative output signals relative to the reference signal indicate the direction of the sensed current. Chao teaches a bidirectional current sensor having a voltage output with a voltage sign indicative of the sign of the load current and a magnitude proportional to that current (col. 6, ll. 55–65).
It would have been obvious to configure Gammie’s pedestal-referenced output in accordance with Chao so that positive and negative output signals relative to the pedestal reference indicate respective directions of the sensed current, because doing so would provide bidirectional current information using the same differential-sensing output.
Claim 20 — Gammie in view of Wynne and Chao
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gammie in view of Wynne and further in view of Chao. For purposes of examination under the prior art, “current” is interpreted as the sensed current associated with the current-sensing application, and the positive and negative output signals are interpreted relative to the claimed reference signal, corresponding to Gammie’s pedestal voltage. This interpretation is made solely for purposes of applying the prior art and does not withdraw the rejection under 35 U.S.C. 112(b).
The Gammie–Wynne combination teaches the monolithic integrated circuit of parent claim 13 for the reasons discussed above. Gammie discloses an output referenced to a pedestal voltage and applies its circuit to current sensing (¶¶ 44 and 59–61), but does not expressly disclose that positive and negative output signals relative to the reference signal indicate the direction of the sensed current. Chao teaches a bidirectional current sensor having a voltage output with a voltage sign indicative of the sign of the load current and a magnitude proportional to that current (col. 6, ll. 55–65).
It would have been obvious to apply Chao’s bidirectional polarity indication to the pedestal-referenced output of the monolithic Gammie–Wynne circuit so that positive and negative output signals relative to the pedestal reference indicate respective directions of the sensed current. Doing so would provide bidirectional current information using the same differential-sensing output.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Qui, US 5,361,037 — switched-capacitor isolation amplifier that converts a differential input signal to charge, transfers that charge across a capacitive isolation barrier using gated switches, and detects the transferred signal with a differential amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIAM SADMAN whose telephone number is (571)270-0921. The examiner can normally be reached on Monday through Thursday from 8:00 am to 4:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han, can be reached at telephone number 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.S./ Examiner, Art Unit 2843
/JOHN W POOS/Primary Examiner, Art Unit 2843
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