DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 05/08/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 5 is objected to because of the following informalities:
Regarding independent claim 5, in L22, Applicant claims, “the second power supply unit”, lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1, 3, 5, 7, 9, 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boris Zaretsky et al. (“Borris”, US Pat 6462926).
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Above annotated Fig. 3 is from Boris Zaretsky et al. (“Borris”, US Pat 6462926)
Table I: Related excerpt and taught matching elements of Boris Zaretsky et al. (“Borris”, US Pat 6462926)
(Fig. 3; col. 3 L47-col. 4 L29 and col. 5 L25-col. 6 L30)
Excerpt from Boris:
Case of Normal Operation
If an input feed is connected and its input voltage is higher in absolute value than the output voltage it is said that the conditions for operation are normal and the comparator turns on the MOSFET transistor allowing the current flow through. In the state of normal operation, the input voltage is higher than the output (and in the present case for telecommunication circuit, the input is more negative than the output) due to the voltage drop across the parallel diode--transistor network developed by the passing through current.
Case of Shorted to Ground Input
If the short circuit occurs at the input, the input voltage will be lower in absolute value (or in our case more positive) than the output (the output still gets power from the other, not shorted to ground, input). This condition is said to be abnormal and the comparator shunts the gate-to-source junction, thus turning off the MOSFET transistor of the shorted to ground input. The Schottky and transistor body diodes will not conduct since they both are set reverse-biased in this condition. Therefore, the input shorted to the ground is disconnected preventing the current back-flow from the other input.
Case of Disconnected Input
The high value resistors between input terminal and the ground allows low voltage to develop across the disconnected input due to a small leakage current of the circuit and reverse leakage current of the Schottky diode. This voltage is set to be lower in absolute value (or more positive in our case of telecommunication powering scheme) than the output voltage. The resultant effect is the same as in the case above; i.e. the comparator shunts or otherwise disables the gate-to-source junction turning the MOSFET transistor off. This will prevent the current back-flow from the connected input to the disconnected one and prevent the development of high hazardous voltage at the disconnected input.
Since the comparator output shuts down the transistor due to open or short circuit at the diode branch input that comparator output signal may serve as an alarm to indicate abnormalities at the diode branch input. However, a separate input monitor circuit may prove to be more advantageous since one of the transistors in Diode-ORing circuit may be turned off simply due to overly low current yet allowing the load to operate without a problem due to current flow through the other diode branch. This situation may occur when the input voltage potential is different between source A and source B and/or the voltage drop across feeder A is different than that across feeder B.
In Fig. 3, the operation of a multi-branched diode-ORing circuit is described.
First when power is applied to any one diode branch in the circuit the output voltage will be set equal to the input source voltage V1 (or V2) minus the voltage drop across the diode D1 (or D5) in the diode branch circuit. For example:
V.sub.out =V.sub.1 -V.sub.d =50V-0.6V=49.4V (EQ. 5)
This will allow to power control circuit comparators from the voltage source developed across Zener diode D4. Now the input voltage is monitored and compared to the output voltage. The input voltage in Diode Branch 1 is sensed by negative terminal of the comparator via resistor R4. The output voltage is sensed by the positive terminal of the comparator via resistor R5. Similar process occurs in Diode Branch 2 where the input is sensed by negative terminal of the comparator via resistor R10 and the output is sensed by positive terminal of the comparator via resistor R11.
The circuit uses comparators with embedded open collector transistor output. If the voltage at the positive terminal is higher than the voltage at the negative terminal, the comparator output transistor is turned off allowing the voltage to develop across Zener diode D5 via resistor R3 thus, turning on the MOSFET transistor. If the voltage at the positive terminal is less than the voltage at the negative terminal the output open collector transistor is turned on sinking the current from R3. This will shunt Zener diode to the reference point Vee of the comparator that is the same point where the anode of Zener diode is connected, i.e. output voltage of the circuit. In effect, this will turn off the MOSFET transistor.
Initially the input voltage V1 is more negative than the output voltage Vout due to the voltage drop across the diode D1. Therefore, the open collector transistor inside the comparator is turned off. The bias voltage develops across Zener D5 and MOSFET transistor Q1 is turned on conducting the current to the load. The voltage drop across MOSFET reduces overall voltage drop across diode branch due to low R.sub.dson of the MOSFET reducing overall power dissipation across the diode branch. The voltage drop across MOSFET reaches finite value continuously supporting the voltage difference between input and output of the circuit thus continuously supporting the on-state of the MOSFET transistor.
If the input power feeder (V1) is removed or circuit breaker CB1 is turned off the output voltage will be supplied through the other diode branch and practically only depend on the value of source V2. The input voltage at the disconnected branch will be that developed across R1 through the resistor-divider network R5-D3-R4-R1. The voltage sensed across R1 becomes more positive than the output voltage monitored by the positive terminal of the comparator. Therefore, the open collector transistor inside comparator is turned on shunting Zener diode D5 and, thus, removing the bias voltage from the gate of the MOSFET. The MOSFET is turned off and this diode branch stops conducting. The voltage at the input of the diode branch depends on selection of resistive divider network components R5, R4, and R1. These resistors can and should be selected to prevent hazardous voltage development at the input due to the current through divider and leakage current through Schottky diode D1.
The diode D3 across the inputs of the comparator serves to protect the inputs when the voltage difference between the output of the circuit and its input exceeds specified safety margins of the comparator. This is especially important when the input is shorted to ground.
If the input of the diode branch is shorted to ground the voltage at the negative input of the comparator is more positive than the voltage at the positive input of the comparator. This difference is limited by the protection diode D3, thus saving the comparator from failure. The open collector transistor inside the comparator shunts Zener diode D5 and turns off the MOSFET transistor stopping it from conducting the current to the load.
Those skilled in the art will appreciate that a similar operation occurs in diode branch 2.
1st/ Upper Power Supply Unit (PSU) being diode branch I
2nd / Lower Power Supply Unit (PSU) being diode branch II
selectively providing input voltage(s) V1 vs. V2, using respective feed protection circuit breakers CB1 vs. CB2 on respective input terminals ‘IN1, IN2’;
main circuit I being ‘D3 R4-5, embedded comparator in circuit U1A’;
1st ORing field effect transistor (FET) ‘Q1, D1’;
Control/gate terminal of Q1;
driving/control circuit I being ‘D3-5, C1, R1-2, R6’;
detected current I, using Ohm’s law (I=V/R) and ‘R4-5’, which ate two comparing input ends of main circuit I’s comparator in U1A;
detection result I being output of U1A’s embedded comparator;
control signal I combined operational output of ‘D5, R3’ used to turn on gate of 1st ORing FET’s Q1;
a switch I being embedded open collector transistor that is driven by comparator’s output within U1A; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II
selectively providing input voltage(s) V1 vs. V2, using respective feed protection circuit breakers CB1 vs. CB2 on respective input terminals ‘IN1, IN2’;
main circuit II being ‘R10-11, D7, embedded comparator in circuit U1B’;
2nd ORing FET ‘Q2, D2’;
Control/gate terminal of Q2;
driving/control circuit II being ‘D6-7, R7-8, R11, C2’;
detected current II, using Ohm’s law (I=V/R) and ‘R10-11’, which ate two comparing input ends of main circuit II’s comparator in U1B;
detection result II being output of U1B’s embedded comparator;
control signal II combined operational output of ‘D6, R9’ used to turn on gate of 2nd ORing FET’s Q2;
a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II
Regarding independent claim 1, Boris teaches (Fig. 3; col. 3 L47-col. 4 L29 and col. 5 L25-col. 6 L30) a power supply unit (Fig. 3; diode branches I-II), comprising:
an input terminal selectively receiving an input voltage (selectively providing input voltage(s) V1 vs. V2, using respective feed protection circuit breakers CB1 vs. CB2 on respective input terminals ‘IN1, IN2’);
an output terminal (Vout for 105);
a main circuit (diode branch I: main circuit I being ‘D3 R4-5, comparator in circuit U1A’, and diode branch II: main circuit II being ‘R10-11, D7, comparator in circuit U1B’; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L43-55)
electrically connected between the input terminal (IN1, IN2) and the output terminal (Vout),
wherein
after the input voltage (i.e., V1 vs. V2) is received by the main circuit (taught respective main circuit(s) I vs. II),
the input voltage (i.e., V1 vs. V2) is converted into an output voltage (Vout) by the main circuit (taught respective main circuit(s) I vs. II);
an ORing field effect transistor (diode branch I: 1st ORing field effect transistor (FET) ‘Q1, D1’ and diode branch II: 2nd ORing FET ‘Q2, D2’)
electrically connected between the output terminal (Vout) and the main circuit (taught respective main circuit(s) I vs. II);
a driving circuit (diode branch I: driving/control circuit I being ‘D3-5, C1, R1-2, R6’ and diode branch II: driving/control circuit II being ‘D6-7, R7-8, R11, C2’)
electrically connected with a control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
wherein the driving circuit (taught respective driving/control(s) I vs. II)
detects a current (diode branch I: detected current I, using ‘R4-5’, which ate two comparing input ends of main circuit I’s comparator in U1A, and diode branch II: detected current II, using ‘R10-11’, which ate two comparing input ends of main circuit II’s comparator in U1B) from the main circuit (taught respective main circuit(s) I vs. II) and
generates a detection result (diode branch I: detection result I being output of U1A’s embedded comparator and diode branch II: detection result II being output of U1B’s embedded comparator),
wherein
the driving circuit (taught respective driving/control(s) I vs. II)
generates a control signal (diode branch I: control signal I combined operational output of ‘D5, R3’ used to turn on gate of 1st ORing FET’s Q1 and diode branch II: control signal II combined operational output of ‘D6, R9’ used to turn on gate of 2nd ORing FET’s Q2)
according to the detection result (taught respective detection result(s) I vs. II), and
the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)) is controlled according to the control signal (taught respective control signal(s) I vs. II); and
a switch (diode branch I: a switch I being embedded open collector transistor that is driven by comparator’s output within U1A and diode branch II: a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II)
electrically connected between the driving circuit (taught respective driving/control(s) I vs. II) and the control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
wherein
before the power supply unit (i.e., diode branch II connected to receive V2) is plugged into a system bus (105) of a power supply system (Fig. 3; a redundant system of device power feed used for mission critical equipment; col. 1 L12-23) and
electrically connected with another operating power supply unit (i.e., diode branch I connected to receive V1) of the power supply system (Fig. 3) in parallel and
the power supply unit (diode branch II) does not receive the input voltage (V1),
the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II) is bypassed by the switch (diode branch I: a switch I being embedded open collector transistor that is driven by comparator’s output within U1A and diode branch II: a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II), and
the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II) fails be transmitted to the control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
so that the ORing field effect transistor is turned off (taught respective 1st vs. 2nd ORing FET(s) being off, in another word Q1 or Q2 being off, when required).
Regarding independent claim 5, Boris teaches (Fig. 3; col. 3 L47-col. 4 L29 and col. 5 L25-col. 6 L30) a power supply system (Fig. 3; redundant system of device power feed used for mission critical equipment; col. 1 L12-23), comprising:
a system bus (105); and
a plurality of power supply units (i.e., diode branches I-II) operably plugged into the system bus (105),
wherein each of the plurality of power supply units (i.e., diode branches I-II) respectively comprises:
an input terminal selectively receiving an input voltage (selectively providing input voltage(s) V1 vs. V2, using respective feed protection circuit breakers CB1 vs. CB2 on respective input terminals ‘IN1, IN2’);
an output terminal (Vout for 105);
a main circuit (diode branch I: main circuit I being ‘D3 R4-5, comparator in circuit U1A’, and diode branch II: main circuit II being ‘R10-11, D7, comparator in circuit U1B’; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L43-55)
electrically connected between the input terminal (IN1, IN2) and the output terminal (Vout),
wherein
after the input voltage (i.e., V1 vs. V2) is received by the main circuit (taught respective main circuit(s) I vs. II),
the input voltage (i.e., V1 vs. V2) is converted into an output voltage (Vout) by the main circuit (taught respective main circuit(s) I vs. II);
an ORing field effect transistor (diode branch I: 1st ORing field effect transistor (FET) ‘Q1, D1’ and diode branch II: 2nd ORing FET ‘Q2, D2’) electrically connected between the output terminal (Vout) and the main circuit (taught respective main circuit(s) I vs. II);
a driving circuit (diode branch I: driving/control circuit I being ‘D3-5, C1, R1-2, R6’ and diode branch II: driving/control circuit II being ‘D6-7, R7-8, R11, C2’)
electrically connected with a control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
wherein the driving circuit (taught respective driving/control(s) I vs. II)
detects a current from the main circuit (diode branch I: detected current I, using ‘R4-5’, which ate two comparing input ends of main circuit I’s comparator in U1A, and diode branch II: detected current II, using ‘R10-11’, which ate two comparing input ends of main circuit II’s comparator in U1B) and
generates a detection result (diode branch I: detection result I being output of U1A’s embedded comparator and diode branch II: detection result II being output of U1B’s embedded comparator),
wherein the driving circuit (taught respective driving/control(s) I vs. II)
generates a control signal (diode branch I: control signal I combined operational output of ‘D5, R3’ used to turn on gate of 1st ORing FET’s Q1 and diode branch II: control signal II combined operational output of ‘D6, R9’ used to turn on gate of 2nd ORing FET’s Q2)
according to the detection result (taught respective detection result(s) I vs. II), and
the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)) is controlled according to the control signal (taught respective control signal(s) I vs. II); and
a switch (diode branch I: a switch I being embedded open collector transistor that is driven by comparator’s output within U1A and diode branch II: a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II) electrically connected between the driving circuit (taught respective driving/control(s) I vs. II) and the control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
wherein a first power supply unit (diode branch I connected to receive V1) of the plurality of power supply units (i.e., diode branches I-II) is plugged into the system bus (105) and receives an input voltage (V1),
wherein before the second power supply unit (diode branch II connected to receive V2) is plugged into the system bus (105) and electrically connected with the first power supply unit (diode branch I) in parallel and the second power supply unit (diode branch II) does not receive an input voltage (V1),
the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II) of the second power supply unit (diode branch II) is bypassed by the switch (diode branch I: a switch I being embedded open collector transistor that is driven by comparator’s output within U1A and diode branch II: a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II), and
the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II) fails be transmitted to the control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
so that the ORing field effect transistor is turned off (taught respective 1st vs. 2nd ORing FET(s) being off, in another word Q1 or Q2 being off, when required).
Regarding independent claim 9, Boris teaches (Fig. 3; col. 3 L47-col. 4 L29 and col. 5 L25-col. 6 L30) a power supply unit (Fig. 3; diode branches I-II), comprising:
an input terminal (selectively providing input voltage(s) V1 vs. V2, using respective feed protection circuit breakers CB1 vs. CB2 on respective input terminals ‘IN1, IN2’);
an output terminal (Vout for 105);
a main circuit (diode branch I: main circuit I being ‘D3 R4-5, comparator in circuit U1A’, and diode branch II: main circuit II being ‘R10-11, D7, comparator in circuit U1B’; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L43-55),
electrically connected between the input terminal (IN1, IN2) and the output terminal (Vout),
for converting an input voltage (i.e., V1 vs. V2) received from the input terminal (IN1, IN2) to an output voltage (Vout);
an ORing field effect transistor (diode branch I: 1st ORing field effect transistor (FET) ‘Q1, D1’ and diode branch II: 2nd ORing FET ‘Q2, D2’)
electrically connected between the output terminal (Vout) and the main circuit (taught respective main circuit(s) I vs. II);
a driving circuit (diode branch I: driving/control circuit I being ‘D3-5, C1, R1-2, R6’ and diode branch II: driving/control circuit II being ‘D6-7, R7-8, R11, C2’),
electrically connected with a control terminal (i.e., gate terminal of Q1 vs. gate terminal of Q2) of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)),
for controlling a conduction status of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s) being on, in another word Q1 or Q2 being on, when required);
a reference voltage source (Vcc, ground, D3 or D7); and
a switch (diode branch I: a switch I being embedded open collector transistor that is driven by comparator’s output within U1A and diode branch II: a switch II being embedded open collector transistor that is driven by comparator’s output within U1B; wherein note that each circuit U1A & U1B is a combination of respective a comparator and respective embedded open collector transistor; col. 5 L30-55. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II)
comprising
a first end (i.e., taught switch I vs. II (embedded open collector transistor)’s 1st end; and similarly, D4’s 1st end) connected with the control terminal of (i.e., gate terminal of Q1 vs. gate terminal of Q2) the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s)) and
a second end (i.e., taught switch I vs. II (embedded open collector transistor)’s 2nd end; and similarly D4’s 2nd end) connected with the reference voltage source (gnd),
wherein
when the input terminal (IN1 vs. IN2) does not receive (col. 5 L25- col. 6 L30) the input voltage (diode branch I connected to receive V1 vs. diode branch II connected to receive V2),
the reference voltage source (Vcc, ground, D3 or D7)
provides a first voltage (i.e., D3 or D7 being performing shorting to the ground; col. 6 L17-30)
for conducting the switch (i.e., when the switch I ‘embedded open collector transistor’ vs. the switch II ‘embedded open collector transistor’ being on or off, which result having respective 1st vs. 2nd ORing FET(s) being on or off. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II)
so that the ORing field effect transistor is turned off (taught respective 1st vs. 2nd ORing FET(s) being off, in another word Q1 or Q2 being off, when required);
when the input terminal (IN1 vs. IN2) receives (col. 5 L25- col. 6 L30) the input voltage (diode branch I connected to receive V1 and diode branch II connected to receive V3),
the reference voltage source (Vcc, ground, D3 or D7)
provides a second voltage (i.e., by taught driving/control circuit I vs. II performs; col. 5 L43- col. 6 L30)
for not conducting the switch (i.e., when the switch I ‘embedded open collector transistor’ vs. the switch II ‘embedded open collector transistor’ being on or off, which result having respective 1st vs. 2nd ORing FET(s) being on or off; col. 5 L43-67. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II)
so that the driving circuit (taught respective driving/control(s) I vs. II; col. 5 L43-67)
controls the conduction status of the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s) being on, in another word Q1 or Q2 being on, when required).
Regarding claims 3, 7, Boris teaches
wherein when the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II)
is in a high voltage level state (col. 5 L25- col. 6 L30) and
the switch is turned off (i.e., when the switch I ‘embedded open collector transistor’ vs. the switch II ‘embedded open collector transistor’ being on or off, which result having respective 1st vs. 2nd ORing FET(s) being on or off; col. 5 L43-67. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II),
the ORing field effect transistor is turned on (taught respective 1st vs. 2nd ORing FET(s) being on, in another word Q1 or Q2 being on, when required),
wherein when the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II)
is in a low voltage level state (col. 5 L25- col. 6 L30),
the ORing field effect transistor is turned off (taught respective 1st vs. 2nd ORing FET(s) being off, in another word Q1 or Q2 being off, when required).
Regarding claim 11, Boris teaches wherein when the input terminal (IN1 vs. IN2) receives the input voltage (V1 vs. V2), the reference voltage source (Vcc, ground, D3 or D7) provides the second voltage (i.e., by taught driving/control circuit I vs. II performs; col. 5 L43- col. 6 L30) for not conducting the switch (i.e., when the switch I ‘embedded open collector transistor’ vs. the switch II ‘embedded open collector transistor’ being on or off, which result having respective 1st vs. 2nd ORing FET(s) being on or off; col. 5 L43-67. Furthermore, there is also a diode switch D4 & resistor R6 are shared by diode branch I-II),
the control signal (taught respective control signal(s) I vs. II) of the driving circuit (taught respective driving/control(s) I vs. II) is configured to be in a high voltage level state (col. 5 L25- col. 6 L30) to turn on the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s) being on, in another word Q1 or Q2 being on, when required), and
the control signal (taught respective control signal(s) I vs. II) from the driving circuit (taught respective driving/control(s) I vs. II) is configured to be in a low voltage level state (col. 5 L25- col. 6 L30) to turn off the ORing field effect transistor (taught respective 1st vs. 2nd ORing FET(s) being off, in another word Q1 or Q2 being off, when required).
Allowable Subject Matter
Claims 2, 4, 6, 8, 10, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, cited art(s) failed to teach, “wherein the switch comprises a diode, wherein an anode of the diode is electrically connected between the driving circuit and the control terminal of the ORing field effect transistor, a cathode of the diode is electrically connected with a reference voltage source inside the power supply unit, and a supply voltage from the reference voltage source and the input voltage of the power supply unit are in a proportional relation, wherein when the power supply unit does not receive the input voltage, the supply voltage from the reference voltage source is a ground voltage level”.
Regarding claim 4, cited art(s) failed to teach, “wherein the switch comprises a PNP transistor, wherein a base of the PNP transistor is electrically connected with a reference voltage source inside the power supply unit, an emitter of the PNP transistor is electrically connected between the driving circuit and the control terminal of the ORing field effect transistor, and a collector of the PNP transistor is connected with a ground voltage level”.
Regarding claim 6, cited art(s) failed to teach, “the switch comprises a diode, wherein an anode of the diode is electrically connected between the driving circuit and the control terminal of the ORing field effect transistor, a cathode of the diode is electrically connected with a reference voltage source inside each of the plurality of power supply units, and a supply voltage from the reference voltage source and the input voltage of each of the plurality of power supply units are in a proportional relation, wherein when the second power supply unit does not receive the input voltage, the supply voltage from the reference voltage source is a ground voltage level”.
Regarding claim 8, cited art(s) failed to teach, “wherein the switch comprises a PNP transistor, wherein a base of the PNP transistor is electrically connected with a reference voltage source inside each of the plurality of power supply units, an emitter of the PNP transistor is electrically connected between the driving circuit and the control terminal of the ORing field effect transistor, and a collector of the PNP transistor is connected with a ground voltage level”.
Regarding claim 10, cited art(s) failed to teach, “wherein the switch comprises a diode, comprising an anode electrically connected with the control terminal of the ORing field effect transistor, a cathode electrically connected with the reference voltage source; when the input terminal does not receive the input voltage, the reference voltage source provides the first voltage for conducting the diode”.
Regarding claim 12, cited art(s) failed to teach, “wherein the switch comprises a PNP transistor, wherein a base of the PNP transistor is electrically connected with the reference voltage source, an emitter of the PNP transistor is electrically connected with the control terminal of the ORing field effect transistor, and a collector of the PNP transistor is connected with a ground voltage level”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Above Fig. 9 is from Eguchi (US Pub 2020/0295596)
Regarding independent claim 1, Eguchi (US Pub 2020/0295596) teaches a power supply unit (Fig. 9) (Fig. 9-10; AC Vin, 1st/upper power supply unit ‘12, 41’, 2nd/lower power supply unit ‘11, 42’ and system bus load ‘22 of a power supply system 203’. Note that when Applicant use phrase “electrically connected”, as can be seen below, Applicant never claims any direct connection, without any intervening elements. Based on that, under broadest reasonable interpretations (BRI), any elements can be anticipated to be electrically connected with another elements, using loop configuration, which can be performed through other intervening elements. Para 21-23), comprising:
an input terminal selectively receiving an input voltage (AC Vin; Para 21-23);
an output terminal (Vm, Vs; Para 22-23, 27-29);
a main circuit (11, 12; Para 22-23, 27-29) electrically connected between the input terminal (AC Vin) and the output terminal (Vm, Vs), wherein after the input voltage (AC Vin) is received by the main circuit (11, 12), the input voltage (AC Vin) is converted into an output voltage (Vm, Vs) by the main circuit (11, 12);
an ORing field effect transistor (ORing FET 41, ORing FET 42; Para 48 & 50) electrically connected between (ORing FET 41 connected between main circuit 12’s output and output terminal Vm; and ORing FET 42 connected between another main circuit 11’s output and output terminal Vs) the output terminal (Vm, Vs) and the main circuit (11, 12);
a driving circuit (i.e., a driving circuit is combined operation of ‘33, 43, 21 & 35’, which is used for detecting current/voltage/temp/or signal from main circuit ‘11, 12’ on 39 or 32, generating a detection result ‘Isb, S8’ and a control signal S5; wherein using taught driving circuit operation, eventually drives the respective gates of ORing FET(s) ‘41 & 42’; Para 22, 32-33, 53-54 and 63) electrically connected (i.e., electrical connection is established using loop configuration of other intervening elements) with a control terminal (gates) of the ORing field effect transistor (the respective gates of ORing FET(s) ‘41 & 42’),
wherein the driving circuit (taught driving circuit) detects a current (a detection signal/voltage/current/or temp. on 39 or 32) from the main circuit (11, 12) and generates a detection result (detection result ‘Isb, S8’),
wherein the driving circuit (taught driving circuit) generates a control signal (a control signal S5) according to the detection result (detection result ‘Isb, S8’), and the ORing field effect transistor (ORing FET(s) 41-42) is controlled according to the control signal (S5); and
a switch (i.e., a switch being ‘anticipated switch or diodes in 43 and/or diode 34’ connected between taught driving circuit and at least ORing FET42’s gate; wherein taught switch is used to bypass taught driving circuit’s output S5, switching ORing FET(s) 41-42 being on or off; Para 30 and 61-63) electrically connected between the driving circuit (taught driving circuit) and the control terminal of the ORing field effect transistor (direct connection with ORing FET42’s gate and indirect connection to ORing 41’s gate),
wherein before the power supply unit (2nd/lower power supply unit ‘11, 42’) is plugged into a system bus (system bus load ‘22 of 203’) of a power supply system (203) and electrically connected with another operating power supply unit (1st/upper power supply unit ‘12, 41’) of the power supply system (203) … and the power supply unit (2nd/lower power supply unit ‘11, 42’) does receive the input voltage (AC Vin),
the control signal (S5) from the driving circuit (taught driving circuit) is bypassed by the switch (switch being ‘anticipated switch or diodes in 43 and/or diode 34’), and the control signal (S5) from the driving circuit (taught driving circuit) fails be transmitted to the control terminal (gate) of the ORing field effect transistor (ORing FET41-42’s gate), so that the ORing field effect transistor is turned off (taught switch is used to bypass taught driving circuit’s output S5, switching ORing FET(s) 41-42 being on or off).
However, Eguchi fails to teach, “before the power supply unit is plugged into a system bus of a power supply system and electrically connected with another operating power supply unit of the power supply system in parallel and the power supply unit does not receive the input voltage”.
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Above annotated Fig. 7, 10, 19 and excerpt are from Huynh (US Pat 6891425)
Regarding independent claim 5, Huynh (US Pat 6891425) teaches (Fig. 10, 19) a power supply system (Fig. 19), comprising:
a system bus (i.e., anticipated load; abstract); and
a plurality of power supply units (circuits A1-An and/or A1-Am, wherein detail of each unit can be seen in Fig. 7 & 10) operably plugged into the system bus (i.e., anticipated load; abstract),
wherein each of the plurality of power supply units (circuits A1-An and/or A1-Am, wherein detail of each unit can be seen in Fig. 7 & 10) respectively comprises:
an input terminal (each terminal of Vin 1 through Vin n) selectively receiving an input voltage (i.e., corresponding VA(s) for each of Vin 1 through Vin n);
an output terminal (terminals that carries respective output of Vc from each circuit A1-An and/or A1-Am of Vin 1);
a main circuit (Q1, DQ1, D1) electrically connected between the input terminal (each terminal of Vin 1 through Vin n) and the output terminal (terminals that carries respective output of Vc from each circuit A1-An and/or A1-Am of Vin 1), wherein after the input voltage (i.e., corresponding VA(s) for each of Vin 1 through Vin n) is received by the main circuit (‘Q1, DQ1, D1’s respective input voltage, via Rs), the input voltage (i.e., corresponding VA(s) for each of Vin 1 through Vin n) is converted into an output voltage (terminals that carries respective output of Vc from each circuit A1-An and/or A1-Am of Vin 1) by the main circuit (Q1, DQ1, D1);
an ORing field effect transistor (Q2, DQ2) electrically connected between the output terminal (terminals that carries respective output of Vc from each circuit A1-An and/or A1-Am of Vin 1) and the main circuit;
a driving circuit (Rs, U1) electrically connected with a control terminal (Q2’s gate) of the ORing field effect transistor (Q2, DQ2), wherein the driving circuit (Rs, U1) detects a current (via Rs) from the main circuit (Q1, DQ1, D1) and generates a detection result (CS+/-), wherein the driving circuit (Rs, U1) generates a control signal (i.e., gate 2 driving Q2’s gate) according to the detection result (CS+/-), and the ORing field effect transistor (Q2, DQ2) is controlled according to the control signal (i.e., gate 2 driving Q2’s gate); and
a … electrically connected between the driving circuit (Rs, U1) and the control terminal (Q2’s gate) of the ORing field effect transistor (Q2, DQ2),
wherein a first power supply unit (i.e., top A1) of the plurality of power supply units is plugged into the system bus (i.e., anticipated load; abstract) and receives an input voltage (i.e., corresponding VA(s) for Vin 1),
wherein before the second power supply unit (i.e., A2) is plugged into the system bus (i.e., anticipated load; abstract) and electrically connected with the first power supply unit (i.e., A1) in parallel and the second power supply unit (i.e., A2) does not receive an input voltage (Vin 1),
the control signal (i.e., gate 2 driving Q2’s gate) from the driving circuit (Rs, U1) of the second power supply unit (i.e., A2) is bypassed by the …, and the control signal (i.e., gate 2 driving Q2’s gate) from the driving circuit (Rs, U1) fails be transmitted to the control terminal (Q2’s gate) of the ORing field effect transistor (Q2, DQ2), so that the ORing field effect transistor is turned off (Q2, DQ2; Q2=off).
However, Huynh fails to teach “each of the plurality of power supply units respectively comprises:”, “a switch electrically connected between the driving circuit and the control terminal of the ORing field effect transistor” and also having “the control signal from the driving circuit of the second power supply unit is bypassed by the switch” resulting the control signal from the driving circuit failing to be transmitted to the control terminal of the ORing field effect transistor, so that the ORing field effect transistor is turned off.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838