Prosecution Insights
Last updated: July 17, 2026
Application No. 18/658,350

ANTENNA-ON-PACKAGE INTEGRATED CIRCUIT DEVICE

Non-Final OA §103§112
Filed
May 08, 2024
Priority
Feb 08, 2019 — provisional 62/803,168 +1 more
Examiner
KIM, SEOKJIN
Art Unit
2844
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
430 granted / 553 resolved
+9.8% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
19 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
75.3%
+35.3% vs TC avg
§102
13.2%
-26.8% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/04/2026 has been entered. Response to Remarks/Arguments With respect to the amendment of claim 1, Applicant remarked in the “Status of the Claims” section, page 1, of Applicant Arguments/Remarks filed 05/04/2026, the support for the amendments to claim 1 can be found from the provisional application No. 62/803,156. This provisional application was NOT specified in the originally filed Specification. The parent application (16/559,094) does not specify the provisional application either. Instead, both the current and the parent applications claimed the benefit of and priority of 62/803,168, wherein, the support for the amendment to claim 1 can be found. See page 4 of the Appendix of 62/803,168, mentioning “Silicon die is undermount … for minimum routing loss to antennas”. Examiner acknowledges the support for the amendment to claim 1 from the provisional application 62/803,168, not from 62/803,156. With respect to the rejection of claims 1-10 under 35 USC 112(b), Examiner withdraws said rejection due to proper amendments. With respect to the rejection of claim 1 under 35 USC 103, Applicant’s arguments filed 05/04/2026 have been fully considered but are moot in view of new ground rejection. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 20, 21, 24 and 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 20, 21, 24 and 25 claim the limitation “antennas are oriented at 45 degrees relative to an arrangement of the first substrate” or similar. This limitation was not described in the originally filed specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 20-22, and 24-28 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis (US 2018/0331051 A1) in view of Thai (US 2019/0348749 A1). Regarding claim 1, Dogiamis teaches an integrated circuit package (Figs. 1-3) comprising: a first substrate (Fig. 1, substrate 150) including a set of conductor layers including first, second, and third conductor layers (153-155), and a first dielectric layer disposed between the first and second conductor layers and a second dielectric layer disposed between the second and third conductor layers ([0018] dielectric layers 162); antennas disposed in the first conductor layer ([0021] antenna unit 152); a ground plane structure (Fig. 3A, GND plane 355 and the upper conductor layer connected to GND 355, corresponding to 154 in Fig. 1) disposed in the second and third conductor layers (355 and the upper conductor layer), the ground plane structure including a first ground plane, a second ground plane, and a first set of vias (355, 154 and the via in between) a first set of package connectors (Fig. 1, 114, 142); a second substrate (Fig. 1, substrate 120) having a first side coupled to the first substrate via the first set of package connectors; an integrated circuit die (Fig. 1, 110, Fig. 3A, die 310) under-mounted on the first substrate (Fig. 1, 110, 110 is under the first substrate 150 and mounted on 150 via 127, 125 though the substrate 122, note that there is a space between 110 and 120 without any support or connector; Fig. 3A, die 310 is under the first substrate 350 and mounted thereon via 325~328 through substrate 322) disposed between the first and second substrates (between 150 and 120) ; and a second set of package connectors coupled to a second side of the second substrate (Fig. 1, solder balls under the substrate 120). However, Dogiamis does not explicitly teach the integrated circuit package comprising: the first set of vias arranged to define openings below the first conductor layer; and a second set of vias coupled between the antennas and a ground plane. Thai teaches an integrated circuit package comprising: a first set of vias (Fig. 17A, [0061] shield posts 134) arranged to define openings (the opening within 141, 139, 114 in which 104 resides) below a first conductor layer (104); and a second set of vias (Figs. 18-19, feed structure 118) coupled between an antennas (104) and a ground plane (120). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the Faraday cage structure of Thai to the teachings of Dogiamis in order to reduce surface waves that cause undesirable coupling and degrade the impedance bandwidth of the antenna and increase the reflection level during beamforming, improving performance (Thai, [0052]). Regarding claim 2, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Thai further teaches the integrated circuit package, wherein the antennas are respectively disposed in the openings (Fig. 17A, 104). Regarding claim 3, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Thai further teaches the integrated circuit package, wherein the set of conductor layers further includes a fourth conductor layer, and the first substrate further includes a third dielectric layer disposed between the third and fourth conductor layers (Figs. 18-19). Regarding claim 4, all the limitations of claim 2 are taught by Dogiamis in view of Thai. Thai further teaches the integrated circuit package, wherein the first set of vias are configured to form a cavity within the at least the second dielectric layer (Fig. 17, 124). Regarding claim 5, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Dogiamis further teaches the integrated circuit package, wherein the antennas include transmitter antennas and receiver antennas ([0025]). Regarding claims 20, 21, 24 and 25, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Dogiamis in view of Thai teaches the package except that each of the antennas are oriented at 45 degrees relative to an arrangement of the first substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Please note that in the instant application, applicant has not disclosed any criticality for the claimed limitations. Regarding claim 22, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Dogiamis further teaches the integrated circuit package, wherein the antennas (Fig. 1, antenna unit 152) are disposed on a first side of the first substrate (substrate 150), and wherein the integrated circuit die (110) is mounted on a second side of the first substrate (substrate 150) opposite the first side of the first substrate. Regarding claim 26, all the limitations of claim 22 are taught by Dogiamis in view of Thai. Dogiamis further teaches the integrated circuit package, further comprising a bond pad coupled to the second side of the first substrate, wherein the integrated circuit die is under-mounted on the first substrate through the bond pad ([0024] pads of the die 210). Regarding claim 27, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Dogiamis further teaches the integrated circuit package, wherein the integrated circuit die is directly coupled to the third conductor layer in the first substrate (Fig. 1, 126, 127). Regarding claim 28, all the limitations of claim 27 are taught by Dogiamis in view of Thai. Dogiamis further teaches the integrated circuit package, further comprising a bond pad coupled to the second side of the first substrate ([0024] pads of the die 210), wherein the integrated circuit die is under-mounted on the first substrate through the bond pad, and wherein the bond pad is electrically coupled to the third conductor layer (Fig. 1, 126, 127). Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis (US 2018/0331051 A1) in view of Thai (US 2019/0348749 A1) as applied to claim 5 above, and further in view of Sato (US 2018/0226727 A1). Regarding claim 6, all the limitations of claim 5 are taught by Dogiamis in view of Thai. Dogiamis in view of Thai does not explicitly teach the package wherein of the transmitter antennas, a first transmitter antenna is offset from a second transmitter antenna in a first direction and is offset from a third transmitter antenna in a second direction perpendicular to the first direction. Sato teaches an integrated circuit package, wherein a first transmitter antenna of the transmitter antennas is offset from a second transmitter antenna of the transmitter antennas in a first direction (Fig. 2, 4a and 4b, [0043] transmitting antennas 4a to 4d) and is offset from a third transmitter antenna of the transmitter antennas in a second direction perpendicular to the first direction (Fig. 2, 4a and 4d). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the antenna layout of Sato to the teachings of Dogiamis in view of Thai in order to take advantages of the highly accurate controllability of a beam radiation direction of MIMO radar method for automotive applications (Sato, [0002], [0052]). Regarding claim 7, all the limitations of claim 5 are taught by Dogiamis in view of Thai. Dogiamis in view of Thai does not explicitly teach the package wherein, of the receiver antennas, a first receiver antenna is offset from a second receiver antenna in a first direction and is offset from a third receiver antenna in a second direction perpendicular to the first direction. Sato teaches an integrated circuit package wherein a first receiver antenna of the receiver antennas is offset from a second receiver antenna of the receiver antennas in a first direction (Fig. 2, 5a and 5b, [0043] receiving antennas 5a to 5d), and is offset from a third receiver antenna of the receiver antennas in a second direction perpendicular to the first direction (Fig. 2, 5b and 5c). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the antenna layout of Sato to the teachings of Dogiamis in view of Thai in order to take advantages of the highly accurate controllability of a beam radiation direction of MIMO radar method for automotive applications (Sato, [0002], [0052]). Claims 8 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis (US 2018/0331051 A1) in view of Thai (US 2019/0348749 A1) as applied to claim 5 above, and further in view of Nakamura (US 2018/0226727 A1). Regarding claim 8, all the limitations of claim 5 are taught by Dogiamis in view of Thai. Dogiamis in view of Thai does not explicitly teach the package wherein the set of conductor layers further includes an electromagnetic band gap structure, a portion of which is formed in the first conductor layer and disposed between at least one transmitter antenna of the transmitter antennas and the receiver antennas. Nakamura teaches an integrated circuit package wherein: the antenna comprising a transmitter antenna (Fig. 2(a), 2, [0022] 2 is a transmitting antenna) formed by a first conductor layer (Fig. 2(b), 2, 11, 3), a receiver antenna (Fig. 2(a), 3, [0022] 3 is a receiving antenna) formed by the first conductor layer (Fig. 2(b), 2, 11, 3); and an electromagnetic bandgap structure (Fig. 2, 10, [0022] isolation structure 10) is formed in part by the first, second and third conductor layers (Fig. 2, 10, Fig. 5, 20, [0031] another example of the isolation structure 20, a first to third conductor layers 21, 11, 4), a portion of the electromagnetic bandgap structure that is formed by the first conductor layer being disposed between the transmitter antenna and the receiver antenna (Fig. 2, 10, [0022] the isolation structure 10 is interposed between 2 and 3). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to integrate the electromagnetic bandgap structures of Nakamura with the antennas of Dogiamis in view of Thai in order to provide an antenna device with an isolation structure capable of effectively improving isolation (Nakamura [0002]). Regarding claim 23, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 23 is rejected under the same rationale as claim 8 above. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis (US 2018/0331051 A1) in view of Thai (US 2019/0348749 A1) and Nakamura (US 2018/0226727 A1), as applied to claim 8 above, and further in view of Lukyanov (US 2022/0131571 A1). Regarding claim 9, all the limitations of claim 8 are taught by Dogiamis in view of Thai and Nakamura. Dogiamis in view of Thai and Nakamura does not explicitly teach the package wherein the electromagnetic band gap structure includes a plurality of cells arranged in a two-dimensional grid. Lukyanov teaches a package wherein an electromagnetic band gap structure includes a plurality of cells arranged in a two-dimensional grid (Figs. 23A-23E, [0081] a two-dimensional period lattice). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the two-dimensional EBG structure of Lukyanov to the teachings of Dogiamis in view of Thai and Nakamura in order to increase the versatility with the high efficiency in blocking the leakage of waves at desired frequencies from wireless channel to the external space ( Lukyanov, [0083]-[0086]). Regarding claim 10, all the limitations of claim 9 are taught by Dogiamis in view of Thai, Nakamura and Lukyanov. Lukyanov further teaches the package, wherein each cell of the plurality of cells includes: a first conductive portion of the first conductor layer of the set of conductor layers ([0098], Fig. 23B); a second conductive portion of the second conductor layer of the set of conductor layers, the second conductive portion coupled to the first conductive portion by a first via ([0098], Fig. 23B); and a third conductive portion of the third conductor layer of the set of conductor layers, the third conductive portion coupled to the second conductive portion by a second via ([0098], Fig. 23C). Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis (US 2018/0331051 A1) in view of Thai (US 2019/0348749 A1) as applied to claim 1 above, and further in view of Liu (US 2017/0033062 A1). Regarding claim 29, all the limitations of claim 1 are taught by Dogiamis in view of Thai. Dogiamis in view of Thai does not explicitly teach the package, further comprising a layer of mold compound arranged between the integrated circuit die and the second substrate. Liu teaches a package, comprising a layer of mold compound arranged between an integrated circuit die and a substrate (Fig. 3d, [0046] 190). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the molding of Liu to the teachings of Dogiamis in view of Thai in order to protect the integrated circuit from environmental degradation (Liu, [0046]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEOKJIN KIM/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

May 08, 2024
Application Filed
Jul 31, 2025
Non-Final Rejection mailed — §103, §112
Oct 31, 2025
Response Filed
Feb 05, 2026
Final Rejection mailed — §103, §112
May 04, 2026
Request for Continued Examination
May 06, 2026
Response after Non-Final Action
May 28, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+13.8%)
2y 3m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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