Prosecution Insights
Last updated: August 18, 2026
Application No. 18/658,572

DISTRIBUTED DYNAMIC TEMPERATURE COMPENSATION FOR SHUNTS

Final Rejection §103
Filed
May 08, 2024
Examiner
ALMO, KHAREEM E
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
626 granted / 717 resolved
+19.3% vs TC avg
Moderate +5% lift
Without
With
+5.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
749
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
37.0%
-3.0% vs TC avg
§102
55.3%
+15.3% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 4, 7-15 and 17-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ruppert (20220381806). With respect to claim 1, figs 1-4 of Ruppert (20220381806) discloses a system comprising: a power switch (power switches S1-S6) configured to carry an electrical current (one of currents Iu-Iw); a gate-driver circuit (8 see [0045] “the driver circuit 8 serves for applying a control voltage or a gate-source voltage U.sub.G1-U.sub.G6 to the switching elements S.sub.1-S.sub.6. “) configured to control the power switch (S1-S6) and measure the electrical current through the power switch the gate driver circuit comprising (see [0046] “the switching elements S.sub.1-S.sub.6 each include a switchable portion, across which a current flows when the switching element is turned on. The switchable portions of the switching elements S.sub.1-S.sub.6 are respectively the drain-source sections through which a load current flows when the corresponding switching element has been made conductive by the driver circuit 8, especially to generate the phase currents I.sub.U, I.sub.V and/or I.sub.W in a clocked operation.”, here thus by operation of the switching the driver is able to measure the phase current): a temperature sensor (9) configured to measure (See [0047], “This switchable portion is associated with the temperature sensor 9, by which the temperature of the switchable portion or a junction temperature of the switching element can be measured.”) a temperature signal indicative of a temperature of the power switch (per [0047] “the switching element S.sub.1 is associated with a temperature sensor 9” per [0051] “S.sub.2-S.sub.6 there are present and correspondingly arranged a temperature sensor 9”); a voltage sensor (10, per [0053] “voltage sensor 10 which are associated with the other switching elements S.sub.2 to S.sub.5”) configured to measure a voltage signal indicative of a voltage across the power switch that is proportional to the electrical current; and a second digital filter (additional non-disclosed filter used within the circuit see [0027] “[0027] The temperature sensor and the voltage sensor may also each include at least one preamplifier connected in front of the analog-digital converter, at least one filter and/or at least one integrator, or be connected to such components. In particular, a preamplifier, a filter and an integrator are placed at the analog side of the analog-digital converter, so that the correspondingly processed measurement signals of the temperature sensor and the voltage sensor can be relayed to the computing device” as there are multiple a/d components there are multiple filters ) configured to estimate a second temperature change of the power switch for a second set of time constants based on the voltage signal (See [0027]“a filter and an integrator are placed at the analog side of the analog-digital converter, so that the correspondingly processed measurement signals of the temperature sensor and the voltage sensor can be relayed to the computing device.”), wherein the time constants of the second set of time constants are less than or equal to 10 milliseconds (ms) (Here, time constants as such are inherent in the calculation of the temperature changes and the value can be controlled to be within the range of greater than 10ms.); and a micro-controller (7 with filter ) connected to the gate driver (8) via a communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) and configured to control operation of the gate driver circuit (8), the micro-controller (7 with filter) comprising: a first digital filter (Filter connected to 7 see [0029] “The analog-digital converters, as well as the other components present, the preamplifiers, filters, integrators and/or transmitter units, can be arranged on a driver board, which is connected to the computing device,”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). configured to estimate a first temperature change of the power switch for a first set of time constants based on the voltage signal, wherein the first set of time constants include time constants having values that are greater than or equal to 10 milliseconds (ms). With respect to claim 4, Ruppert produces the device of claim 1 wherein the power switch (S1-S6) comprises at least one of a metal oxide semiconductor field effect transistor, an insulated-gate bipolar transistor, a gallium nitride transistor, or a bipolar junction transistor (See. [0033], “the switching element which are used are metal oxide semiconductor field effect transistors (MOSFETs), especially those based on silicon carbide. In the case of a switching element designed as a mosfet, the switchable portion is accordingly the drain-source section of the transistor”) With respect to claim 7, Ruppert produces the system of claim 1, wherein the first digital filter operates independently from the second digital filter, wherein the second filter comprises a digital filter (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). With respect to claim 8, Ruppert produces the device system of claim 1, wherein the second set of time constants of the second digital filter are configured to compensate for short-term load changes carried by the power switch. (Here, the set time constants are within the scope of the invention and the manipulation of such would be obvious expedient to one of ordinary skill in the art.) With respect to claim 9, Ruppert produces the device system of claim 1, wherein the first digital filter is configured to output the first estimated temperature change to the electrical gate- driver (8) circuit via the communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) , and wherein the electrical gate-driver circuit (8) is configured to add the first estimated temperature change to the second estimated temperature change from the second digital filter (filter associated with the controller and See figure 4 or 2, showing summation of the temperature changes to the motor 4). . With respect to claim 10, Ruppert produces the device system of claim 1, wherein the first digital filter (filter) is configured to dynamically modify filter coefficients for the second digital filter (filter) via the communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). With respect to claim 11, Ruppert produces the device system of claim 1, wherein the first digital filter is implemented in software, and wherein the second digital filter is implemented in hardware. (Here, the choice of filter type used as first or second filter is obvious expedient to one of ordinary skill in the art.) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). With respect to claim 12, the circuit above produces a system comprising: a micro-controller (7) circuit connected to a gate-driver circuit (8) via a communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) and configured to control operation of the gate-driver circuit, the micro-controller circuit comprising a first digital filter (Filter connected to 7 see [0029] “The analog-digital converters, as well as the other components present, the preamplifiers, filters, integrators and/or transmitter units, can be arranged on a driver board, which is connected to the computing device,”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device).; and the gate-driver circuit comprising a second filter (Filter connected to 8 see [0027] “The temperature sensor and the voltage sensor may also each include at least one preamplifier connected in front of the analog-digital converter, at least one filter and/or at least one integrator, or be connected to such components. In particular, a preamplifier, a filter and an integrator are placed at the analog side of the analog-digital converter, so that the correspondingly processed measurement signals of the temperature sensor and the voltage sensor can be relayed to the computing device.”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device).,wherein the gate-driver circuit is configured to control operation of a power switch (S1-S6), wherein the first digital filter is configured to model temperature compensation of the power switch for a first set of time constants having values that are greater than or equal to 10 milliseconds (ms), and wherein the second digital filter is configured to model temperature compensation of the switch for a second set of time constants having values that are less than or equal to 10 milliseconds (ms), and wherein each time constant in the second set of time constants is less than or equal to time constants in the first set of time constants (Here, manipulation of the time constants to achieve a desired resist is deemed obvious expedient to one skilled in in the art and thus within the scope of the invention). With respect to claim 13, Ruppert produces the system of claim 12, further comprising a power supply (i.e. HV+ or HV-) configured to apply power to a load (4) via the power switch (S1--S6). With respect to claim 14, Ruppert produces the system of claim 12, wherein the second set of time constants of the second digital filter (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device) are configured to compensate for short-term load changes(load 4) carried by the power switch (S1-S6). (The filters would meet this criteria of compensation) With respect to claim 15, the circuit above produces the system of claim 12, further comprising a temperature sensing circuit (temperature sensors 9), wherein the gate-driver circuit (8) is configured to receive a first signal output (i.e. at 11) from the temperature sensing circuit (9) indicating a temperature of the system, wherein the gate-driver circuit is further configured to receive a second signal output (at 12) from the power switch (S1-S6) indicating a drain-source voltage (VDS) of the power switch, and wherein the gate-driver circuitry comprises a temperature compensation loop (loop associated with power switch) that operates based on the first signal output and the second signal output. With respect to claim 17, the circuit above produces the system of 15 wherein the first digital filter (Filter connected to 7 see [0029] “The analog-digital converters, as well as the other components present, the preamplifiers, filters, integrators and/or transmitter units, can be arranged on a driver board, which is connected to the computing device,”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device).; is configured to output updates to the gate-driver circuit (8) via the communication bus(buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) , and wherein the gate-driver circuit (8) adds the updates from the first digital filter to the temperature compensation loop (via controller 7). With respect to claim 18, the circuit above produces the system of claim 12, wherein the first digital filter is configured to dynamically modify filter coefficients for the second digital filter via the communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) . With respect to claim 19, the circuit above produces a method comprising :controlling operation of a gate-driver circuit (8), by a micro-controller circuit (7) connected to the gate driver circuit via a communication bus (buses shown in fig. 3 connecting fig. 7 and 8 and buses would also connect the gate driver to the gates of the power switches as control) , wherein the micro-controller circuit comprises a first digital filter (Filter connected to 7 see [0029] “The analog-digital converters, as well as the other components present, the preamplifiers, filters, integrators and/or transmitter units, can be arranged on a driver board, which is connected to the computing device,”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). wherein the first digital filter is configured to model a first temperature compensation of a power switch (S1-S6) for a first set of time constants having values that are greater than or equal to 10 milliseconds (ms);measure, by the gate-driver circuit(8), a voltage across the power switch (HV+ and HV- across S1-S6), wherein the gate- driver circuit comprises a second digital filter (Filter connected to 8 see [0027] “The temperature sensor and the voltage sensor may also each include at least one preamplifier connected in front of the analog-digital converter, at least one filter and/or at least one integrator, or be connected to such components. In particular, a preamplifier, a filter and an integrator are placed at the analog side of the analog-digital converter, so that the correspondingly processed measurement signals of the temperature sensor and the voltage sensor can be relayed to the computing device.”) (Here, although the filters are analog it is obvious for the filters to be digital and placed on the digital side to convey information to the computing device). configured to model a second temperature compensation of the power switch for a second set of time constants having values that are less than or equal to 10 milliseconds (ms); and modeling, by the micro-controller (7) executing the first digital filter, the first temperature compensation of the power switch for the first set of time constants, wherein each time constant in the second set of time constants is less than or equal to time constants in the first set of time constants. (Here, manipulation of the time constants to achieve a desired resist is deemed obvious expedient to one skilled in in the art and thus within the scope of the invention). With respect to claim 20, the circuit above produces the method of claim 19,wherein the second digital filter is implemented in software, and wherein the first digital filter is implemented in hardware. (Here, the choice of implementing components in software or hardware is deemed obvious expedient to one skilled in in the art and thus within the scope of the invention). With respect to claim 21, Ruppert produces the system of claim 1, wherein the power switch is part of a shunt (see [0011], “The electrical resistance of the switchable portion can be viewed here as a shunt…”). Response to Arguments Applicant's arguments filed 4/14/2026 have been fully considered but they are not persuasive With respect to the filter, although it is not an digital filter it is deemed obvious to use a digital filter to cooperate with the digital computing system of 7. These measures systems are still based on the temperature reading at which the computer system manipulates the output. With respect to controlling the power switch, S1-S6 are deemed (power switches and would read on the claim language. With respect to the specific time constants, because the time constants are inherent in the structure it is within the scope of one skilled in the art to manipulate the time constants to achieve a specific result and deemed obvious to do so. With respect to the communication bus, as can be seen in figure 3, 7 and 8 are connected via a communication bus (wires) and also the switches are connected via the gates to the bus for control With respect to the filters, no distributed thermal modeling architecture different from Ruppert is claimed. The second and first digital filters are exhibited by the filters associated with the Rupert architecture and are capable of carrying out the functionality described in the claim language. With respect to claim 9, because the gate driver adds the estimated temperature changes to produce the signal output to the load this is not deemed distinguishable over the cited prior art. With respect to claim 10, the digital filter is deemed to modify the signal to the load based on the temperature changes analyzed by the microcontroller. As such this claim is not distinguishable over the cited prior art. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am -5:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAREEM E ALMO/Examiner, Art Unit 2836 /Menatoallah Youssef/SPE, Art Unit 2836
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Prosecution Timeline

May 08, 2024
Application Filed
Jan 14, 2026
Non-Final Rejection mailed — §103
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 07, 2026
Examiner Interview Summary
Apr 14, 2026
Response Filed
Jul 02, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.3%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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