DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 03/30/2026, for application number 18/658,600 has been received and entered into record. Claims 1, 10, 12 and 16 are amended. Claims 2, 11 and 17 are cancelled. Thus, claims 1, 3-10, 12-16 and 18-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. (US 2011/0296211 A1) in view of Riccio et al. (US 2007/0200536 A1).
Regarding claim 1, Ramaraju teaches a method comprising:
outputting, using a voltage regulator, a regulated output cache voltage to a cache via a cache power rail (“Processor 10 includes global voltage regulator 22 and local voltage regulators 20 and 24.” Par 0017 and “In voltage regulator 24, transistor 38 has a first current electrode coupled to cache memory 18 at power supply terminal VVVSS2,” par 0019 and “cache 18 is connected to power supply terminal VVVSS 2.” Par 0020 and “predetermined voltages are provided using voltage regulators… to provide the first predetermined voltage above ground to the cache memory.” par 0012 Figure 1) [the power supply terminals correspond to the power rails; the voltage regulators provide voltages to cache memory];
producing, by a cache controller, a cache activity signal, based on the cache being accessed (“if cache 18 should be accessed…If the answer is YES, the YES path is taken to step 74… At step 74, local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and “In voltage regulator 24, transistor 38 has … a control electrode for receiving control signal DISABLE 3 from power management unit 19,” par 0019 and Figure 3) [the power management unit corresponds to the cache controller, which produces a signal (disable 3) when it determines cache needs to be accessed]; and
controlling, using the cache activity signal, a shunt current circuit coupled between the cache power rail and a ground potential to selectively shunt current from the voltage regulator (“local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and “In voltage regulator 24, transistor 38 has a first current electrode coupled to cache memory 18 at power supply terminal VVVSS2 … and a second current electrode coupled to VVSS.” Par 0019) [the shunt current circuit corresponds to the transistor 38; the activity signal is used to activate transistor branch that shunts the cache power rail (VVVSS 2) directly to ground (VVSS), see Figure 1]; and
wherein the cache controller sends the cache activity signal directly to a control input of the transistor switch to turn off the transistor switch and remove the shunt current from the voltage regulator when the cache is being accessed (“In voltage regulator 24, transistor 38 has a first current electrode coupled to cache memory 18 at power supply terminal VVVSS2, a control electrode for receiving control signal DISABLE 3 from power management unit 19,” par 0019 and “If the answer is YES, the YES path is taken to step 74. The power supply voltage at cache 18 must be increased to the normal voltage before cache 18 can be reliably accessed during, for example, a read operation. At step 74, local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and Figure 3) [the PMU corresponds to the controller that sends the activity signal directly to the transistor’s control input (see Figure 1, the disable 3 signal travels from the PMU directly to transistor 38’s input) to disable the shunting path and restore full voltage when the cache needs to be accessed].
However, Ramaraju does not explicitly teach wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground potential.
In the analogous art, Riccio teaches wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground potential (“the field effect transistor operates purely as a switch.” Par 0029 and “additional nonreactive resistors … can be connected in series with the load paths of the transistors.” Par 0026 and “the load path of the transistor being connected between the potential of the output voltage to be regulated and ground.” Par 0004 and Figures 2-4) [the FET corresponds to the transistor switch; the shunt resistor corresponds to the nonreactive resistors connected in series between the rail and ground; since the resistors are connected in series with the load path and that entire path is connected to ground to dissipate excess current, the resistors function as shunt resistors].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju and Riccio before him before the effective filing date of the claimed invention, to have modified Ramaraju to incorporate the teachings of Riccio to have the transistor switch coupled between the cache power rail and the shunt resistor coupled to ground to limit the current to ensure that the load and control loops of the shunt regulator are not impaired by excessively high current.
Claim 10 corresponds to claim 1 and is rejected accordingly.
Regarding claim 3, Ramaraju and Riccio teach the method of claim 1. Ramaraju further teaches further comprises resetting the cache activity signal, by the cache controller, following the cache being accessed, wherein the shunt current circuit provides shunt current from the voltage regulator based on resetting the cache activity signal (“After step 76, the cache access is completed. At step 78, the low power mode is reentered by enabling voltage regulator 24.” Par 0032 and “The terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively.” Par 0016) [once the cache access concludes, the PMU reenables the voltage regulator by resetting (negating) the activity signal, which restores the regulator’s shunting function to maintain low power state].
Regarding claim 16, Ramaraju teaches an on-chip voltage regulator comprising:
a cache power rail configured to output a regulated cache output voltage to a cache (“cache 18 is connected to power supply terminal VVVSS 2.” Par 0020 and “The first and second predetermined voltages are provided using voltage regulators… to provide the first predetermined voltage above ground to the cache memory.” par 0012) [the power supply terminal (rail) outputs voltage from voltage regulator to cache memory],
a shunt current circuit configured to receive the cache output voltage and provide a shunt current (“In voltage regulator 24, transistor 38 has a first current electrode coupled to cache memory 18 at power supply terminal VVVSS2 … and a second current electrode coupled to VVSS.” Par 0019 and “The first and second predetermined voltages are provided using voltage regulators… to provide the first predetermined voltage above ground to the cache memory.” par 0012) [the voltage regulator corresponds to the shunt current circuit coupled to power rail VVVSS 2 tor regulator voltage by providing controlled current path to ground];
a cache controller having activity logic configured to produce a cache activity signal, based on the cache being accessed, and to send the cache activity signal to a control input of the transistor switch (“it is determined if cache 18 should be accessed… If the answer is YES, the YES path is taken to step 74… At step 74, local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and “transistor 38 has … a control electrode for receiving control signal DISABLE 3 from power management unit 19,” par 0019) [the PMU (controller) monitors cache access signal and generates disable 3 that is sent directly to the control input of the transistor, see Figure 1]; and
wherein the transistor switch is configured to directly receive at the control input the cache activity signal from the cache controller of the cache based on the cache being accessed [Figure 1, the disable 3 signal is being sent directly to the input of the transistor 38 from the PMU 19], wherein the cache activity signal turns off the transistor switch to remove the shunt current from the on-chip voltage regulator when the cache is being accessed (“In voltage regulator 24, transistor 38 has a first current electrode coupled to cache memory 18 at power supply terminal VVVSS2, a control electrode for receiving control signal DISABLE 3 from power management unit 19,” par 0019 and “If the answer is YES, the YES path is taken to step 74. The power supply voltage at cache 18 must be increased to the normal voltage before cache 18 can be reliably accessed during, for example, a read operation. At step 74, local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and Figure 3) [the PMU corresponds to the controller that sends the activity signal directly to the transistor’s control input (see Figure 1, the disable 3 signal travels from the PMU directly to transistor 38’s input) to disable the shunting path and restore full voltage when the cache needs to be accessed].
However, Ramaraju does not explicitly teach wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground.
In the analogous art, Riccio teaches wherein the shunt current circuit comprises a transistor switch coupled between the cache power rail and a shunt resistor coupled to ground (“the field effect transistor operates purely as a switch.” Par 0029 and “additional nonreactive resistors … can be connected in series with the load paths of the transistors.” Par 0026 and “the load path of the transistor being connected between the potential of the output voltage to be regulated and ground.” Par 0004 and Figures 2-4) [the FET corresponds to the transistor switch; the shunt resistor corresponds to the nonreactive resistors connected in series between the rail and ground; since the resistors are connected in series with the load path and that entire path is connected to ground to dissipate excess current, the resistors function as shunt resistors].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju and Riccio before him before the effective filing date of the claimed invention, to have modified Ramaraju to incorporate the teachings of Riccio to have the transistor switch coupled between the cache power rail and the shunt resistor coupled to ground to limit the current to ensure that the load and control loops of the shunt regulator are not impaired by excessively high current.
Claims 4-6, 13, 14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Riccio in view of Gruber et al. (US 2022/0103142 A1).
Regarding claim 4, Ramaraju and Riccio teach the method of claim 1. However, Ramaraju and Riccio do not explicitly teach wherein the voltage regulator further comprises a two-stage on-chip regulator having a first regulator stage receiving a reference voltage at a first input, and the regulated output cache voltage at a second feedback input, and providing its output coupled to a second regulator stage, the second regulator stage receiving the regulated output cache voltage and providing a gate control signal at its output.
In the analogous art, Gruber teaches wherein the voltage regulator further comprises a two-stage on-chip regulator having a first regulator stage receiving a reference voltage at a first input, and the regulated output cache voltage at a second feedback input, and providing its output coupled to a second regulator stage, the second regulator stage receiving the regulated output cache voltage and providing a gate control signal at its output (“The gate terminal of transistor 525 is coupled to the output voltage terminal Vout (the inverting input terminal of the operational amplifier), the gate terminal of transistor 526 is coupled to the reference voltage terminal Vref (the non-inverting input terminal of the operational amplifier)… The second terminal of transistor 524 and the first terminal of transistor 528 are coupled to a first terminal of capacitance CD and to an output terminal of the operational amplifier 520, providing the bias voltage VB. ” Par 0076 and “The LDO/buffered FVF of FIG. 5h further comprises super source follower 530, implementing the buffer (circuit) of the buffered FVF… The gate terminal of transistor 534 is the input terminal of the buffer (circuit) and is coupled to node VX.” Par 0080 and Figure 5G) [the two-stage architecture where Vout and Vref feed into first stage (op amp 520), whose output (Vb) controls the second stage (530/buffer), provides gate drive signal to the main pass transistor].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Riccio and Gruber before him before the effective filing date of the claimed invention, to have modified Ramaraju and Riccio to incorporate the teachings of Gruber to include a two-stage regulator by adding the feed-forward compensation circuit to increase phase margin of the circuit and thus improve stability of the circuit at higher bandwidths. (Gruber, paragraph 53)
Claims 13 and 19 correspond to claim 4 and are rejected accordingly.
Regarding claim 5, Ramaraju, Riccio and Gruber teach the method of claim 4. Gruber further teaches wherein the two-stage on-chip regulator comprises an output transistor receiving the gate control signal coupled to its control input, and receiving a reference voltage coupled to its source, and its drain providing the regulated output cache voltage connected to the cache power rail (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “The gate terminal of the first transistor MP is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit −gmf.” Par 0052) [Mp is the pass device whose gate terminal (control input) receives signal from gate driver; in the context of a pass transistor in a LDO, the supply voltage is the input being regulated down to output voltage, correspondsing to an upstream reference point for the pass device].
Regarding claim 6, Ramaraju, Riccio and Gruber teach the method of claim 5. Gruber further teaches wherein the output transistor comprises an output p-type field effect transistor (PFET) receiving the gate control signal coupled to its gate, the reference voltage coupled to its source, and its drain providing the regulated output cache voltage connected to the cache power rail (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “In examples, the first transistor/pass device transistor MP and the second transistor/common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055).
Claims 14 and 20 correspond to claim 6 and are rejected accordingly.
Claims 7-9, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Riccio in view of Gruber and in further view of Garag et al. (US 2023/0093729 A1).
Regarding claim 7, Ramaraju, Riccio and Gruber teach the method of claim 6. However, Ramaraju, Riccio and Gruber do not explicitly teach wherein the shunt current circuit comprises an NFET coupled between the cache power rail and a shunt resistor coupled to ground potential, the NFET receiving the cache activity signal at its gate, and receiving the regulated output cache voltage at its drain and its source coupled to the shunt resistor.
In the analogous art, Garag teaches wherein the shunt current circuit comprises an NFET coupled between the cache power rail and a shunt resistor coupled to ground potential, the NFET receiving the cache activity signal at its gate, and receiving the regulated output cache voltage at its drain and its source coupled to the shunt resistor (“If the output voltage 622 is above the target output voltage, the output of the op amp 613 increases, allowing for increased shunt current to flow through the source of NMOS transistor 616 to the drain of the NMOS transistor 616 to ground 604, decreasing the output voltage 622.” Par 0081 and “wherein an output of the operational amplifier is connected to a gate of a transistor, wherein a source of the transistor is connected to the output voltage of the voltage regulator, wherein a drain of the transistor is connected to a ground.” Par 0103 and “The analog controller will continuously adjust the shunt current through the transistor 616 based on the output voltage 622.” Par 0087) [this shows the NFET (NMOS transistor) controls the shunt current path between the regulated output voltage (cache power rail 622) and ground and its gate is controlled by analog circuitry (which is enabled by memory operation signal); the function of the transistor 616 effectively acts as the controllable resistor in the shunt path to ground].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Riccio, Gruber and Garag before him before the effective filing date of the claimed invention, to have modified Ramaraju, Riccio and Gruber to incorporate the teachings of Garag to incorporate an NFET to generate less heat in the system and allow for faster switching speeds.
Regarding claim 8, Ramaraju, Riccio, Gruber and Garag teach the method of claim 7. Ramaraju further teaches wherein the cache activity turns off the NFET to remove the shunt current from the voltage regulator when the cache is being accessed (“if cache 18 should be accessed…If the answer is YES, the YES path is taken to step 74… At step 74, local regulator 24 is disabled by asserting control signal DISABLE 3.” Par 0032 and “Disable signal DISABLE 1 is asserted as a logic high to make transistor 26 conductive, thus connecting node N3 to VVS” par 0029 and “ Node N2 is at VSS potential so transistors 224 and 226 are substantially non-conductive.” Par 0029 and “transistors 26, 28, 32, 34, 38, and 40 are N-channel transistors” par 0017 and “Transistors 26, 28, 218, and 224 are N-type MOS (metal oxide semiconductor) transistors” par 0026 and paragraph 28, 30) [when the cache access is detected, the PMU asserts disable signal which forces the voltage regulator’s NFET (transistor 26, also corresponding to the shunt current circuit) into a non-conductive state (turning it off) thereby removing the shunt regulation path to restore full power supply].
Claim 12 is covered by claims 7 and 8 and is rejected accordingly.
Regarding claim 9, Ramaraju, Riccio, Gruber and Garag teach the method of claim 7, Garag further teaches further comprises resetting the cache activity signal, by the cache controller, following the cache being accessed, and wherein the cache activity turns on the NFET to provide shunt current from the voltage regulator based on the reset cache activity signal (“In block 1028, the method 1000 checks if the memory operation is complete. If it is not, the method 1000 loops back to block 1012 in FIG. 10 to check whether the input voltage 602 is higher than the next reference voltage. If it is, the method 1000 proceeds to block 1022 in FIG. 10 , in which the controller circuitry 504 disables the voltage regulator 506.” Par 0092 and “The analog controller will continuously adjust the shunt current through the transistor 616 based on the output voltage 622.” Par 0087) [controller 504 checks for memory operation completion (activity signal reset) and manages shunt transistor, regulating shunt current based on output voltage].
Regarding claim 15, Ramaraju, Riccio and Gruber teach the system of claim 14. Gruber further teaches wherein the output field effect transistor (FET) comprises an output PFET (“In examples, the first transistor/pass device transistor MP and the second transistor/common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055) [the output transistor Mp is a PFET].
The remainder of clam 15 corresponds to claim 7 and is rejected accordingly.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju and Riccio in view of Gruber.
Regarding claim 18, Ramaraju and Riccio teach the on-chip voltage regulator of claim 16. However, Ramaraju and Riccio do not explicitly teach wherein the switch comprises a field effect transistor (FET) configured to receive the cache activity signal coupled to its gate, and its source and drain coupled between the cache power rail and the shunt resistor.
In the analogous art, Gruber teaches wherein the switch comprises a field effect transistor (FET) configured to receive the cache activity signal coupled to its gate, and its source and drain coupled between the cache power rail and the shunt resistor (“A first terminal (the source terminal) of the pass device MP is coupled to the supply voltage of the buffered FVF, the second terminal (the drain terminal) is coupled to output node/terminal Vout and to the first terminal (the source terminal) of the common-gate amplifier transistor MC.” par 0047 and “In examples, the first transistor/pass device transistor MP and the second transistor/ common-gate amplifier transistor MC are implemented as a p-channel Metal Oxide Semiconductor Field Effect Transistors (p-MOSFET).” Par 0055).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ramaraju, Riccio and Gruber before him before the effective filing date of the claimed invention, to have modified Ramaraju and Riccio to incorporate the teachings of Gruber to include a FET by adding the feed-forward compensation circuit to increase phase margin of the circuit and thus improve stability of the circuit at higher bandwidths. (Gruber, paragraph 53)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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