Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II (Figs. 3A-3C, claims 1-4, 6-9, and 12) in the reply filed on June 2, 2026, is acknowledged.
Claims 5 and 10-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 2, 2026.
Specification
The disclosure is objected to because of the following informalities: in paragraph [0084], “impudence” should be “impedance”.
Appropriate correction is required.
Claim Objections
Claim 2 is objected to because of the following informalities:
In claim 2, line 2, “impendence” should be “impedance”.
Appropriate correction is required.
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Figs. 46(a) and 46(b) of Hata, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, and 8-9 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Hata, Pub. No. US 2013/0273696, hereafter referred to as Hata.
Regarding claim 1, Hata teaches all of the limitations of the claim in Figs. 46(a) and 46(b), reproduced above with annotations added by the examiner, and in the specification: “A semiconductor device” ([0002]; Figs. 46(a) and 46(b)) “comprising: a first lead comprising a planar stripline” ([0269]; Figs. 46(a) and 46(b), drain terminal DT; note the flat shape of the drain terminal DT); “a second lead comprising a planar stripline” ([0260], Figs. 46(a) and 46(b), source terminal ST; note the flat shape of the source terminal ST); “a first semiconductor die mounted on the first lead” ([0260]; Figs. 46(a) and 46(b), semiconductor chip CHP; note that the semiconductor chip CHP is mounted to the chip placement portion TAB; also see [0259]: “A chip placement portion TAB is formed over the heat sink HS and this chip placement portion TAB is formed integrally with the drain terminal DT.”) “and comprising: a bottom pad disposed on a first side of the first semiconductor die and electrically coupled to the first lead” ([0260]: “A drain electrode (not shown) is formed in the back surface of the semiconductor chip CHP and this drain electrode is electrically coupled with the drain terminal (outer lead) through the chip placement portion TAB.”); “and a first top pad disposed on a second side of the first semiconductor die” ([0260]; Fig. 46(a), source pad SP) “and electrically coupled to the second lead” ([0260]: “…and the source pad SP is electrically coupled with the source terminal (outer lead) ST through a wire W2.”; Figs. 46(a) and 46(b), wire W2), “wherein a shape of the semiconductor device corresponds to a fin” (Figs. 46(a) and 46(b); note that the device has a “fin” shape). The limitation, “wherein the semiconductor device is configured for immersion cooling”, does not result in any structural difference in the claimed device, and thus it carries no patentable weight.
Regarding claim 4, Hata further teaches “The semiconductor device of claim 1, further comprising: a third lead comprising a planar stripline” ([0260]; Fig. 46(a), gate terminal GT; note the flat shape of the gate terminal GT); “wherein the first semiconductor die further comprises a second top pad disposed on the second side of the first semiconductor die” ([0260]; Fig. 46(a), gate pad GP); “wherein the second top pad is electrically coupled to the third lead” ([0260]: “The gate pad GP is electrically coupled with the gate terminal (outer lead) GT through a wire W1”, Fig. 46(a), wire W1); “and wherein the planar stripline of the third lead is co-planar with the planar stripline of the second lead” (Fig. 46(b); note that, as shown in the side view, all three of the source terminal ST, the drain terminal DT, and the gate terminal GT are coplanar).
Regarding claim 6, Hata further teaches “The semiconductor device of claim 1, further comprising an encapsulant disposed over and around the first semiconductor die” ([0261]; Fig. 46(b), sealing body MR; note that the sealing body MR completely surrounds the semiconductor chip CHP).
Regarding claim 8, Hata further teaches “The semiconductor device of claim 6, further comprising the encapsulant disposed around a portion of the first lead and a portion of the second lead” (Fig. 46(b); note that the sealing body MR encloses portions of the source terminal ST, the drain terminal DT, and the gate terminal GT).
Regarding claim 9, Hata further teaches “The semiconductor device of claim 6, wherein the encapsulant is electrically non-conductive” ([0261]: “As illustrated in FIG. 46B, the heat sink HS is so formed that it is exposed from the bottom surface of the sealing body MR and the chip placement portion TAB is placed over the heat sink HS with resin RN in between.”; Fig. 46(b), note that the sealing body MR is made of resin RN, which is an insulating material).
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Fig. 7 of Nuotio, reproduced with annotation added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hata in view of Nuotio, Pub. No. US 2023/0068223, hereafter referred to as Nuotio.
Regarding claim 2, Hata teaches “The semiconductor device of claim 1”, but does not teach “wherein the first and second leads comprise a low impedance or controlled-impendence interconnect between the first semiconductor die and circuitry external to the semiconductor device.”
Nuotio, on the other hand, anticipates “wherein the first and second leads comprise a low impedance or controlled-impendence interconnect between the first semiconductor die and circuitry external to the semiconductor device” by teaching that the leads form low-impedance connections to external busbars (Nuotio [0058]: “An advantage of the exposed large surface area power lead frame pin surfaces 711, 713, 723 is allowing for the formation of a low-impedance connection to external busbars.”; Fig. 7, lead frame pin surfaces 711, 713, and 723).
The teaching of low-impedance connections found in Nuotio can be incorporated into the device of Hata by making the terminals with a low impedance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the terminals of Hata with a low impedance as taught by Nuotio because it would reduce power losses in the terminals and it would be a simple combination of elements of the two disclosures.
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Fig. 1L of Ho, reproduced with annotations added by the examiner.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hata in view of Ho et. al., Pub. No. US 2023/0395553, hereafter referred to as Ho.
Regarding claim 3, Hata anticipates “The semiconductor device of claim 1, wherein the first lead is soldered or brazed to the bottom pad” by teaching that the drain terminal DT is soldered to the drain electrode on the semiconductor chip CHP (Hata [0262]: “The semiconductor chip CHP is placed over the chip placement portion TAB with solder PST2 (not shown in FIG. 46B) in between.”; also see [0259]: “A chip placement portion TAB is formed over the heat sink HS and this chip placement portion TAB is formed integrally with the drain terminal DT.”), but does not teach “and wherein the second lead is soldered or brazed to the first top pad.” Hata does, however, teach that the source terminal ST is electrically connected to the source pad SP through a wire W2 (Hata [0260]; Figs. 46(a) and 46(b); note that the source terminal ST is connected to the source pad SP by the wire W2).
Ho, on the other hand, anticipates “and wherein the second lead is soldered or brazed to the first top pad” by teaching a second lead that is soldered to the semiconductor die (Ho [0040] and [0042]; Fig. 1L, note that the second pin 18 is attached to the die 14 by solder 17).
The attachment of the second pin of Ho to the die via soldering can be incorporated into the device of Hata by attaching the source terminal to the source pad by soldering.
It would have been obvious to one of ordinary skill in the art to solder the source terminal of Hata to the source pad, as taught by Ho, because doing so would establish a more direct and lower-resistance connection between the two elements and it would be a simple combination of the two disclosures.
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Fig. 1 of Poh, reproduced with annotations added by the examiner.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hata in view of Poh et. al., Pub. No. US 2010/0193920, hereafter referred to as Poh.
Regarding claim 7, Hata teaches “The semiconductor device of claim 6”, but does not teach “wherein a thickness of the encapsulant over the first semiconductor die is five microns or less.”
Poh, on the other hand, teaches an encapsulant with a thickness of less than 500 microns over a semiconductor chip (Poh [0023]: “The thickness of the encapsulation material layer along the second face of the first chip island may be arranged to be smaller than for example 500 micrometers.”; Fig. 1, semiconductor chips 14 and 16 and encapsulation material 20), a range which overlaps the claimed range.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the thickness of the encapsulant over semiconductor chip of Hata less than 500 microns because a sufficiently thin encapsulant would allow the dissipation of heat into an external member and current case law holds that, in cases wherein the general conditions of a claim are disclosed in the prior art, discovering optimal or working ranges involves only routine skill in the art (see MPEP 2144.05 II A: “"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”).
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Fig. 7 of Piccioni, reproduced with annotations added by the examiner.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hata in view of Piccioni et. al., Pub. No. US 2025/0323129, hereafter referred to as Piccioni.
Regarding claim 12, Hata teaches “The semiconductor device of claim 1, wherein the first semiconductor die further comprises a second top pad disposed on the second side of the first semiconductor die” (Hata [0260]; Fig. 46(a), gate pad GP); but does not teach “and wherein the second top pad is electrically coupled to the second lead.” Instead, Hata teaches that the second top pad is electrically connected to a third lead (Hata [0260]; Fig. 46(a), gate terminal GT).
Piccioni, on the other hand, teaches a similar semiconductor device (Piccioni [0005-0006]: “The package may also comprise a power transistor or multiple chips, e.g. a transistor and a diode.”; Fig. 7) in which a source connector is bonded to a semiconductor device through multiple pads (Piccioni [0059]; Fig. 7, first load layers 7, source connector 16, and source interconnects 17).
The bonding of a source terminal to multiple load layers taught by Piccioni can be incorporated into the device of Hata by introducing an additional source pad and electrically connecting the source terminal to both of them. The combined device teaches “and wherein the second top pad is electrically coupled to the second lead” (Hata [0260]; Fig. 46(a), source pad SP and source terminal ST; note that there are multiple source pads SP in the combined device, with the source terminal ST connected to all of them).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce a second source pad as taught by Piccioni into the device of Hata because doing so would reduce the resistance in the connection between the source terminal and the source pads and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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