Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-18 in the reply filed on 8/4/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/8/2024 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Claim Objections
Claims 3 and 4 are objected to because of the following informalities:
Claim 3: “a” between “…the…” and “…first circuit carrier” should be deleted.
Claim 4: limitation listed.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-8, 10, 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (US20240088007A1).
Regarding Claim 1:
Baek discloses a method of forming a semiconductor package (Fig. 5), the method comprising:
providing a lead frame (step 530) that comprises a plurality of leads (elements 310a/310b) connected with a peripheral structure (Fig. 6E);
providing a plurality of die pads (Fig. 4 element Db) each having a power switching device mounted thereon (elements 110a/b, paragraph 45);
providing a first circuit carrier (Fig. 3A element 103) with a controller device mounted thereon (element 110c), the controller device being configured to control a switching operation of the power switching devices (paragraph 18);
forming a mechanical connection (Fig. 3A element 311/312) between the first circuit carrier (element 103) and the lead frame (element 550, paragraph 38); and
performing an encapsulation process to form an electrically insulating encapsulant body (element 310, paragraph 41) that encapsulates the power switching devices and the controller device (step 560);
wherein the first circuit carrier is physically supported by the mechanical connection prior to performing the encapsulation process (steps 520 and 560),
wherein forming the mechanical connection comprises an electrical interconnection processing technique (step 550, paragraph 56).
Regarding Claim 4:
Baek discloses a method according to claim 1, wherein the electrical interconnection processing technique comprises (step 550) one or more of:
affixing an attachable metal element to one or both of the first circuit carrier and the lead frame
(paragraphs 56-57); and/or
applying an electrically conductive adhesive to one or both of the first circuit carrier and the lead frame (step 530, paragraph 38).
Regarding Claim 5:
Baek discloses a method according to claim 4, wherein the electrical interconnection processing technique (step 550) comprises affixing the attachable metal element to one or both of the first circuit carrier (Fig. 4 element 103) and the lead frame (element 310b), and wherein the attachable metal element is a bond wire (elements 312d/e, paragraph 56).
Regarding Claim 6:
Baek discloses a method according to claim 4, wherein the electrical interconnection processing technique (step 530) comprises applying the electrically conductive adhesive to one or both of the first circuit carrier (Fig. 3A element 103) and the lead frame (element 310b), and wherein the electrically conductive adhesive is a solder material (element 311, paragraph 38).
Regarding Claim 7:
Baek discloses a method according to claim 4, wherein the lead frame (Fig. 3A elements 310a/310b) comprises a mechanical support post (see annotated fig. attached below), wherein the method comprises arranging the mechanical support post to extend over an outer edge side of the first circuit carrier (step 530), and wherein forming the mechanical connection comprises directly attaching the mechanical support post with the first circuit carrier using the electrical interconnection processing
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461
570
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technique (paragraphs 38, 56, and 62).
Regarding Claim 8:
Baek discloses a method according to claim 7, wherein directly attaching the mechanical support post to an upper side of the first circuit carrier (Figs. 3A and 6E) comprises attaching a bond wire (elements 312) to the upper side of the first circuit carrier and the mechanical support post (step 550, paragraphs 46, 56, and 64).
Regarding Claim 10:
Baek discloses a method according to claim 7, wherein directly attaching the mechanical support post to an upper side of the first circuit carrier (Figs. 3A and 6E) further comprises applying an electrically conductive adhesive (element 311) between the upper side of the first circuit carrier and the mechanical support post (paragraph 38).
Regarding Claim 17:
Baek discloses a method according to claim 1, wherein the plurality of die pads (Fig. 1 elements Db) is provided by a second circuit carrier (element 102, paragraph 16), wherein the method comprises forming a second mechanical connection (Fig. 3A element 312a) between the second circuit carrier and the lead frame (element 310a).
Regarding Claim 18:
Baek discloses a method according to claim 17, wherein forming the mechanical connection between the first circuit carrier and the lead frame comprises attaching the second circuit carrier (step 720, Fig. 1 element 102) to the first circuit carrier (element 103) using the electrical interconnection processing technique (paragraph 28).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20240088007A1) in view of Niu et al. (US20230335474A1).
Regarding Claim 2:
Baek discloses a method according to claim 1, but does not explicitly disclose where the mechanical connection is electrically inactive.
Niu, however, discloses an analogous power module package (Fig. 5A), comprising a first circuit carrier (element 520) that is physically supported by a mechanical connection (elements 517/519) and wherein the mechanical connection is electrically inactive (paragraph 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Niu to explicitly include wherein the mechanical connection is electrically inactive because both are directed to analogous semiconductor power module packages. Doing so improves the performance of the package and the overall manufacturing process (Niu, paragraphs 2 and 26).
Regarding Claim 3:
Baek discloses a method according to claim 1, wherein the first circuit carrier (Fig. 3A element 103) is a printed circuit board (paragraph 16), but does not explicitly disclose where the mechanical connection is connected to an electrically isolated bond pad.
Niu, however, discloses an analogous power module package (Fig. 5A), wherein a mechanical connection (elements 517/519) is affixed to an electrically isolated bond pad (elements 507/509) disposed on an upper side of a circuit carrier (element 520, paragraph 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Niu to explicitly include wherein the mechanical connection is affixed to an electrically isolated bond pad – disposed on an upper side of the first carrier – because both are directed to analogous semiconductor power module packages. Doing so improves the performance of the package and the overall manufacturing process (Niu, paragraphs 2 and 26).
Regarding Claim 15:
Baek discloses a method according to claim 1, but does not explicitly disclose where the plurality of die pads is provided by the lead frame.
Niu, however, discloses an analogous power module package (Fig. 5A), wherein a plurality of die pads (elements 530) is provided by a lead frame (paragraph 24), wherein the lead frame is configured such that each of the die pads are connected with a peripheral structure (paragraphs 24-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Niu to explicitly include wherein the plurality of die pads is provided by the lead frame. Further, wherein the lead frame is configured such that each of the die pads are connected with the peripheral structure because both are directed to analogous semiconductor power module packages. Doing so improves the performance of the package and the overall manufacturing process (Niu, paragraphs 2 and 26).
Regarding Claim 16:
The combination of Baek and Niu disclose a method according to claim 15, wherein Baek further discloses forming the mechanical connection between the first circuit carrier and the lead frame comprises attaching at least some of the die pads (Fig. 4 elements Db) to the first circuit carrier (element 103) using the electrical interconnection processing technique (elements 312, paragraph 56).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20240088007A1) in view of Khanolkar et al. (US20230022572A1).
Regarding Claim 9:
Baek discloses a method according to claim 8, but does not explicitly disclose wherein the step of directly attaching the mechanical support post to the upper side of the first circuit carrier further comprises of soldering the bond wire.
Khanolkar, however, discloses an analogous packaging method (Fig. 7), comprising soldering a bond wire to the upper side of semiconductor dies to mechanical supports (step 714, paragraph 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Khanolkar to explicitly include soldering the bond wires to the upper side of the first circuit carries and the mechanical support post because both are directed to analogous methods for manufacturing semiconductor packages. Doing so improves the overall manufacturing process (Khanolkar, paragraph 44).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20240088007A1) in view of Zohni et al. (US20150115434A1).
Regarding Claim 11:
Baek discloses a method according to claim 7, wherein the mechanical support post extends over the first circuit carrier (Fig. 3A) but does not explicitly disclose where the mechanical support post further comprises a perforation that extends over the first circuit carrier.
Zohni, however, discloses an analogous packaging method (paragraphs 74-80), wherein a support structure (Fig. 2B element 102, paragraph 49) comprises a perforation (element 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Zohni to explicitly include wherein the mechanical support post comprises a perforation that extends over an upper side of the first circuit carrier because both are directed to analogous methods for manufacturing semiconductor packages. Doing so improves the integrity of the semiconductor packages (Zohni, paragraphs 2-5).
Regarding Claim 12:
The combination of Baek and Zohni disclose a method according to claim 11, but Baek does not explicitly disclose where a bond wire is routed through a perforation in the mechanical support post.
Zohni, however, discloses an analogous packaging method (paragraphs 74-80), wherein a bond wire (Fig. 2B element 165) is routed through the perforation (element 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Zohni to explicitly include wherein forming the mechanical connection comprises attaching a bond wire to an upper side of the first circuit and the mechanical support post. Further, wherein the bond wire is routed through the perforation because both are directed to analogous methods for manufacturing semiconductor packages. Doing so improves the integrity of the semiconductor packages (Zohni, paragraphs 2-5).
Regarding Claim 13:
The combination of Baek and Zohni discloses a method according to claim 11, but Baek does not explicitly disclose a vertical wire that is arranged and attached within the perforation of the mechanical support post.
Zohni, however, discloses an analogous packaging method (paragraphs 74-80), comprising forming a vertical wire (Fig. 2B element 148) on an upper side of a first circuit carrier (element 136); arranging the vertical wire within the perforation (element 116); and attaching the vertical wire to the first circuit carrier by an electrically conductive adhesive (element 142, paragraph 55).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Zohni to explicitly include forming a vertical wire on an upper side of the first circuit carrier, arranging the vertical wire within the perforation, and attaching said wire to the mechanical support post by an electrically conductive adhesive because both are directed to analogous methods for manufacturing semiconductor packages. Doing so improves the integrity of the semiconductor packages (Zohni, paragraphs 2-5).
Regarding Claim 14:
The combination of Baek and Zohni discloses a method according to claim 11, wherein Baek discloses forming the mechanical connection comprises providing an electrically conductive adhesive that directly attaches the mechanical support post with the first circuit carrier but does not explicitly disclose wherein the mechanical support post comprises a perforation.
Zohni, however, discloses an analogous packaging method (paragraphs 74-80), wherein a mechanical connection comprises providing an electrically conductive adhesive (Fig. 2B element 159) within the perforation (element 116) that directly attaches the mechanical support post (element 102) with the first circuit carrier (element 153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method described in Baek further in view of Zohni to explicitly include wherein forming the mechanical connection comprises providing an electrically conductive adhesive within the perforation that directly attaches the mechanical support post with the first circuit carrier because both are directed to analogous methods for manufacturing semiconductor packages. Doing so improves the integrity of the semiconductor packages (Zohni, paragraphs 2-5).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 20230245942 A1), Otremba et al. (US 20170179009 A1), Hama et al. (US 20230052108 A1), Lu et al. (US 20170133314 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
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