DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 04/15/2026.
Claim Objections
Claim 18 is objected to because of the following informalities: Claim 18, third line recites “the transformer”, which should be –a transformer-- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim 25 is objected to because of the following informalities: Claim 25, lines 3-4 recites “the transformer”, which should be –a transformer-- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp.
Regarding claim 1, Fahlenkamp discloses (see figures 1-26) a control circuit (figures 1 and 5, part control circuit generated by 60) for controlling switching elements (figure 1, parts 21, 22, 41 and 42) of a switched-mode power supply (figure 1) (paragraph [0035]; FIG. 1 shows an example of a switching converter), the control circuit (figures 1 and 5, part control circuit generated by 60) comprising: a control input (figure 5, part control input at 63; where input S21’/S22’) operative to receive a pulse width modulated control signal (figure 5, part S21’/S22’ from 61) comprising a series of control pulses (figure 3, part S21’/S22’) (paragraph [0054]; This drive circuit 60 has a pulse width modulator 61, which is designed to generate two pulse-width-modulated signals S21', S22' depending on an output voltage signal Sout); a primary output (figure 5, part output at 63; where output S41/S42) operative to control a primary switching element (figure 1, part 41/42) of the switched-mode power supply (figure 1); control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) operative to generate a primary pulse width modulated control signal (figure 5, part S41/S42) based on the received pulse width modulated control signal (figure 5, part S21’/S22’ from 61), the primary pulse width modulated control signal (figure 5, part S41/S42) comprising a series of primary pulses (figures 3 and 5, part S41/S42), the generated primary pulse width modulated control signal (figure 5, part S41/S42) outputted from the primary output (figure 5, part output at 63; where output S41/S42) to control the primary switching element (figure 1, part 41/42); and wherein the primary PWM control signal (figures 3 and 5, part S41/S42) is generated such that the series of primary pulses (figures 3 and 5, part S41/S42) are controlled to occur between the control pulses (figures 3 and 5, part S21’/S22’) (paragraphs [0054]–[0057]; The drive circuit 60 additionally has an adaptation circuit 63, which is designed to generate the primary-side drive signals S21, S22 and also the secondary-side drive signals S41, S42 for the secondary-side freewheeling elements and to temporally coordinate these signals with one another).
Regarding claim 2, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) a secondary output (figure 5, part output at 63; where output S21s/S22s), for controlling a secondary switching element (figure 5, part 21/22) of the switched-mode power supply (figure 1), wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) is further configured to generate, based on the received pulse width modulation control signal (figure 5, part S21’/S22’ from 61), a secondary pulse width modulation control signal (figure 5, part S21s/S22s) at the secondary output (figure 5, part output at 63; where output S21s/S22s), wherein the primary pulse width modulation control signal (figure 5, part S41/S42) and the secondary pulse width modulation control signal (figure 5, part S21s/S22s) are generated such that: i) the primary switching element is controlled to be off (figures 1 and 3, part 41/42; turn-off S41/S42) during a first condition in which the secondary switching element is on (figures 1 and 3, part 21/22; turn-on S21/S22), and ii) the secondary switching element is controlled to be off (figures 1 and 3, part 21/22; turn-off S21/S22) during a second condition in which the primary switching element is on (figures 1 and 3, part 41/42; turn-on S41/S42) (paragraphs [0054]–[0057]).
Regarding claim 20, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) the series of control pulses in the received pulse width modulated control signal (figures 3 and 5, part S21’/S22’ from 61) includes a first control pulse, a second control pulse, and a third control pulse (figure 3, part first, second and third control pulse of S21’/S22’); wherein the series of primary pulses in the generated primary pulse width control signal (figures 3 and 5, part S41/S42) include a first primary pulse and a second primary pulse (figure 3, part first and second primary pulse of S41/S42); wherein the first primary pulse (figure 3, part first primary pulse of S41/S42) resides between the first control pulse (figure 3, part first control pulse of S21’/S22’) and the second control pulse (figure 3, part second control pulse of S21’/S22’; based on the inversion and delay logic); and wherein the second primary pulse (figure 3, part second primary pulse of S41/S42) resides between the second control pulse (figure 3, part second control pulse of S21’/S22’) and the third control pulse (figure 3, part third control pulse of S21’/S22’; based on the inversion and delay logic).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp, in view of Jacobs et al. (US 6,078,509), hereinafter Jacobs.
Regarding claim 3, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) comprises inversion logic (figure 5, part inversion logic at S of 635/636), wherein the primary pulse width modulation control signal (figure 5, part S41/S42). However, Fahlenkamp does not expressly disclose inversion logic, configured to invert the pulse width modulation control signal to generate an inverted PWM control signal, wherein the primary pulse width modulation control signal is generated based on the inverted pulse width modulation control signal.
Jacobs teaches (see figures 1-3) the control logic (figure 2, part 225) comprises inversion logic (figure 2, part inversion logic between d and DELAY), configured to invert (figure 2, part inversion logic between d and DELAY) the pulse width modulation control signal (figure 2, part pulse width modulation control signal d from 220) to generate an inverted PWM control signal (figure 2, part inverted PWM control signal 1-d), wherein the primary pulse width modulation control signal (figure 2, part primary pulse width modulation control signal output from DELAY to S2) is generated based on the inverted pulse width modulation control signal (figure 2, part inverted PWM control signal 1-d) (column 4; lines 17-55).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control logic of Fahlenkamp with the control logic features as taught by Jacobs and obtain the control logic comprises inversion logic, configured to invert the pulse width modulation control signal to generate an inverted PWM control signal, wherein the primary pulse width modulation control signal is generated based on the inverted pulse width modulation control signal, because it provides more effective control in order to obtain more accurate desired output voltage for all output load conditions (column 4; lines 28-37).
Regarding claim 4, Fahlenkamp and Jacobs teach everything claimed as applied above (see claim 3). Further, Fahlenkamp discloses (see figures 1-26) the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) comprises primary delay logic (figure 5, part 633/634), a defined primary delay time (figures 3 and 5, part defined primary delay time of 633/634; Td2), thereby to generate the primary pulses (figures 3 and 5, part S41/S42). However, Fahlenkamp does not expressly disclose the inverted pulse width modulation control signal comprises a series of pulses, each pulse having a leading edge and a trailing edge, and wherein the control logic comprises primary delay logic, configured to delay the leading edge of each pulse in the inverted pulse width modulation control signal by a defined primary delay time, thereby to generate the primary pulses.
Jacobs teaches (see figures 1-3) the inverted pulse width modulation control signal (figure 2, part inverted PWM control signal 1-d) comprises a series of pulses (figure 2, part inverted PWM control signal 1-d), each pulse having a leading edge and a trailing edge (figure 2, part inverted PWM control signal 1-d), and wherein the control logic (figure 2, part 225) comprises primary delay logic (figure 2, part DELAY), configured to delay the leading edge of each pulse in the inverted pulse width modulation control signal (figure 2, part inverted PWM control signal 1-d) by a defined primary delay time (figure 2, part defined primary delay time of DELAY), thereby to generate the primary pulses (figure 2, part primary pulses from DELAY to S2) (column 2; lines 25-35; the delay circuit comprises a signal inverter that generates a signal complementary to the main switch control signal. The turn-on time of the complementary signal (1-d) is then delayed to provide the resulting delay signal. In one embodiment of the present invention, the delay circuit provides a delay of fixed duration. Of course, some applications may benefit from a controllable delay, perhaps based on feedback of the ringing or on load current information).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control logic of Fahlenkamp with the control logic features as taught by Jacobs and obtain the inverted pulse width modulation control signal comprises a series of pulses, each pulse having a leading edge and a trailing edge, and wherein the control logic comprises primary delay logic, configured to delay the leading edge of each pulse in the inverted pulse width modulation control signal by a defined primary delay time, thereby to generate the primary pulses, because it provides more effective control in order to obtain more accurate desired output voltage for all output load conditions (column 4; lines 28-37).
Regarding claim 5, Fahlenkamp and Jacobs teach everything claimed as applied above (see claim 4). Further, Fahlenkamp discloses (see figures 1-26) each control pulse of the pulse width modulation control signal (figure 5, part S21’/S22’ from 61) has a leading edge and a trailing edge (figures 3 and 5, part S21’/S22’ from 61), wherein the secondary pulse width modulation control signal (figure 5, part S21s/S22s) comprises a series of secondary pulses (figures 3 and 5, part S21s/S22s [S21/S22]), each secondary pulse (figures 3 and 5, part S21s/S22s [S21/S22]) corresponding to a respective control pulse (figures 3 and 5, part S21s/S22s [S21/S22]), and wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) comprises secondary delay logic (figure 5, part 631/632), configured to delay the leading edge of each control pulse in the pulse width modulation control signal (figures 3 and 5, part S21’/S22’ from 61) by a defined secondary delay time (figures 3 and 5, part defined secondary delay time of 631/632; Td1), thereby to generate the secondary pulses (figures 3 and 5, part S21s/S22s [S21/S22]) (paragraphs [0054]–[0057]; the adaptation circuit 63 has first and second delay elements 631, 632, to which the pulse-width-modulated output signals S21', S22' of the pulse width modulator 61 are fed and at the outputs of which the primary-side drive signals S21, S22 are available).
Regarding claim 6, Fahlenkamp and Jacobs teach everything claimed as applied above (see claim 5). Further, Fahlenkamp discloses (see figures 1-26) a sensing terminal (figure 5, part upper sensing terminal at 63; wherein the Sdel input) configured to sense an electrical characteristic (figures 5, 6 and 7, part through Sdel), wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) is configured to set one or both of the primary delay time (figures 3 and 5, part primary delay time of 633/634; Td2) and the secondary delay time (figures 3 and 5, part secondary delay time of 631/632; Td1) responsive to the sensed electrical characteristic (figures 5, 6 and 7, part through Sdel) (paragraphs [0055]–[0059]; The delay elements have a settable delay duration with a delay duration dependent on a delay signal Sdel… The delay time of the third and fourth delay elements 633, 634 could also be settable depending on a delay signal Sdel, however, in a manner corresponding to the first and second delay elements 631, 632. The delay signal Sdel which determines the delay durations Td1 is generated by a delay signal generating circuit 65… This delay signal generating circuit 65 illustrated in FIG. 6 is designed to determine a voltage that occurs maximally across one of the freewheeling elements during a drive cycle, and to set the delay signal Sdel depending on the voltage).
Regarding claim 16, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) inversion logic (figure 5, part inversion logic at S of 635/636) operative to invert (figure 5, part inversion logic at S of 635/636); and primary delay logic (figure 5, part 633/634) operative to delay rising edges (figure 5, part 633/634); and produce the generated primary pulse width modulated control signal (figure 5, part S41/S42) outputted from the primary output (figure 5, part output at 63; where output S41/S42) to control the primary switching element (figure 1, part 41/42). However, Fahlenkamp does not expressly disclose inversion logic operative to invert the received pulse width modulated control signal to produce an inverted pulse width modulated signal; and primary delay logic operative to delay rising edges of the inverted pulse width modulated control signal to produce the generated primary pulse width modulated control signal outputted from the primary output to control the primary switching element.
Jacobs teaches (see figures 1-3) inversion logic (figure 2, part inversion logic between d and DELAY) operative to invert (figure 2, part inversion logic between d and DELAY) the received pulse width modulated control signal (figure 2, part pulse width modulation control signal d from 220) to produce an inverted pulse width modulated signal (figure 2, part inverted PWM control signal 1-d); and primary delay logic (figure 2, part DELAY) operative to delay rising edges (figure 2, part DELAY) of the inverted pulse width modulated control signal (figure 2, part inverted PWM control signal 1-d) to produce the generated primary pulse width modulated control signal (figure 2, part primary pulses from DELAY to S2) outputted from the primary output to control the primary switching element (figure 2, part S2) (column 2; lines 25-35; the delay circuit comprises a signal inverter that generates a signal complementary to the main switch control signal. The turn-on time of the complementary signal (1-d) is then delayed to provide the resulting delay signal. In one embodiment of the present invention, the delay circuit provides a delay of fixed duration. Of course, some applications may benefit from a controllable delay, perhaps based on feedback of the ringing or on load current information).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control logic of Fahlenkamp with the control logic features as taught by Jacobs and obtain inversion logic operative to invert the received pulse width modulated control signal to produce an inverted pulse width modulated signal; and primary delay logic operative to delay rising edges of the inverted pulse width modulated control signal to produce the generated primary pulse width modulated control signal outputted from the primary output to control the primary switching element, because it provides more effective control in order to obtain more accurate desired output voltage for all output load conditions (column 4; lines 28-37).
Regarding claim 22, Fahlenkamp discloses everything claimed as applied above (see claim 20). Further, Fahlenkamp discloses (see figures 1-26) first delay logic (figure 5, part 633/634) operative to: i) delay a rising edge (figure 5, part 633/634), and ii) delay a rising edge (figure 5, part 633/634). However, Fahlenkamp does not expressly disclose i) delay a rising edge of the first primary pulse with respect to a falling edge of the first control pulse, and ii) delay a rising edge of the second primary pulse with respect to a falling edge of the second control pulse.
Jacobs teaches (see figures 1-3) first delay logic (figure 2, part DELAY) operative to: i) delay a rising edge (figure 2, part DELAY) of the first primary pulse (figure 2, part first primary pulse at 1-d) with respect to a falling edge of the first control pulse (figure 2, part first control pulse at d; through inversion and delay logic), and ii) delay a rising edge (figure 2, part DELAY) of the second primary pulse (figure 2, part second primary pulse at 1-d) with respect to a falling edge of the second control pulse (figure 2, part second control pulse at d; through inversion and delay logic).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control logic of Fahlenkamp with the control logic features as taught by Jacobs and obtain first delay logic operative to: i) delay a rising edge of the first primary pulse with respect to a falling edge of the first control pulse, and ii) delay a rising edge of the second primary pulse with respect to a falling edge of the second control pulse, because it provides more effective control in order to obtain more accurate desired output voltage for all output load conditions (column 4; lines 28-37).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp, in view of Pervaiz et al. (US 11,575,314), hereinafter Pervaiz.
Regarding claim 7, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) an over-current protection circuit (figures 1 and 5, part control circuit generated by 60) (paragraph [0098];the driver circuits can also realize protection functions… The protection functions may comprise for example a protection of the semiconductor switches against over-temperature, overvoltage or overcurrent), wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) is configured to reduce a pulse width of the primary pulse width modulation control signal (figure 5, part reduce S41/S42). However, Fahlenkamp does not expressly disclose configured to sense a current switched by the primary switching element, wherein the over-current protection circuit is configured to detect an excessive current condition in which the sensed current exceeds a current protection threshold, wherein the control logic is configured to reduce a pulse width of the primary pulse width modulation control signal, responsive to the detection of said excessive current condition.
Pervaiz teaches (see figures 1-10) an over-current protection circuit (figure 5, part 504i), configured to sense a current (figure 5, part ID_s) switched by the primary switching element (figure 5, part S4), wherein the over-current protection circuit (figure 5, part 504i) is configured to detect an excessive current condition (figure 5, part 504i) in which the sensed current (figure 5, part ID_s) exceeds a current protection threshold (figure 5, part OCPref), wherein the control logic (figure 5, part 506) is configured to reduce a pulse width of the primary pulse width modulation control signal (figure 3c, part reduce PWM_2), responsive to the detection of said excessive current condition (figure 5, part OCP from 504i) (column 19; lines 16-28; if comparator 504i determines if a relatively large negative current flows through the current sense resistor RSense (e.g., ID_s×RSense>greater than OCPref), then the resulting OCP signal output by the comparator 504i can be used to shutdown switching of the boost PFC converter).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control circuit of Fahlenkamp with the over-current protection features as taught by Pervaiz and obtain an over-current protection circuit, configured to sense a current switched by the primary switching element, wherein the over-current protection circuit is configured to detect an excessive current condition in which the sensed current exceeds a current protection threshold, wherein the control logic is configured to reduce a pulse width of the primary pulse width modulation control signal, responsive to the detection of said excessive current condition, because it provides more reliable and efficient power converter with more efficient protection circuit (column 31; lines 45-67).
Regarding claim 8, Fahlenkamp and Pervaiz teach everything claimed as applied above (see claim 7). Further, Fahlenkamp discloses (see figures 1-26) the control circuit (figures 1 and 5, part control circuit generated by 60), wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) is configured to reduce a pulse width of at least one of the primary pulse width modulation control signal (figure 5, part reduce S41/S42) and the secondary pulse width modulation control signal (figure 5, part reduce S21s/S22s). However, Fahlenkamp does not expressly disclose an over-current protection terminal, wherein the control circuit is configured to provide an output signal at the over-current protection terminal indicative of the detection of said excessive current condition, wherein the control circuit is configured to receive at the over-current protection terminal an input signal indicative of an excessive current event, wherein the control logic is configured to reduce a pulse width of at least one of the primary pulse width modulation control signal and the secondary pulse width modulation control signal, responsive to said received input signal.
Pervaiz teaches (see figures 1-10) an over-current protection terminal (figure 5, part over-current protection terminal at 7/8), wherein the control circuit (figure 5, part 105) is configured to provide an output signal (figure 5, part output signal from protection circuitry 506h to 7/8) at the over-current protection terminal (figure 5, part over-current protection terminal at 7/8) indicative of the detection of said excessive current condition (figure 5, part protection circuitry 506h) (column 22; lines 29-46; The digital I/O block 508b can be used to communicate with or otherwise program the programmable front-end 506g and/or to communicate protection signals to the boost PFC converter (e.g., via GD_EN, at pin 10) or to other systems (e.g., via the communication interface at pins 7 and 8)), wherein the control circuit (figures 3c and 5, part 105) is configured to receive at the over-current protection terminal an input signal (figure 5, part input signal to over-current protection terminal at 7/8) indicative of an excessive current event (figure 5, part OCP event to protection circuitry 506h), wherein the control logic (figure 5, part 506) is configured to reduce a pulse width of at least one of the primary pulse width modulation control signal (figure 3c, part reduce PWM_2) and the secondary pulse width modulation control signal (figure 3c, part reduce PWM_1) (column 19; lines 16-28; shutdown switching of the boost PFC converter), responsive to said received input signal (figure 5, part input signal to over-current protection terminal at 7/8) (column 22; lines 12-28; The protection circuitry 506h may include standard protection circuitry across various stresses, such as input/output over-voltage protection (OVP), input over-current protection (OCP), thermal shutdown (TSD), under voltage protection (UVP), and under voltage lockout (UVLO). Any number of such protections schemes and circuitry can be used, and the present disclosure is not intended to be limited to any particular schemes or circuitry. As can be seen, the generated protection signals can be used internal to the controller (e.g., using OCP signal as a control input), or external to the controller (e.g., by providing a protection signal to a gate driver or a downstream system via the digital I/O 508b)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control circuit of Fahlenkamp with the over-current protection features as taught by Pervaiz and obtain an over-current protection terminal, wherein the control circuit is configured to provide an output signal at the over-current protection terminal indicative of the detection of said excessive current condition, wherein the control circuit is configured to receive at the over-current protection terminal an input signal indicative of an excessive current event, wherein the control logic is configured to reduce a pulse width of at least one of the primary pulse width modulation control signal and the secondary pulse width modulation control signal, responsive to said received input signal, because it provides more reliable and efficient power converter with more efficient protection circuit (column 31; lines 45-67).
Claims 9-14, 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp, in view of Xiong et al. (US 2022/0131471), hereinafter Xiong.
Regarding claim 9, Fahlenkamp discloses everything claimed as applied above (see claim 2). Further, Fahlenkamp discloses (see figures 1-26) a rectifier (figure 1, parts 41/42) comprising: a controlled switching element (figure 1, parts 41/42), having a control terminal (figure 1, parts control terminal of 41/42); and the control circuit (figures 1 and 5, part control circuit generated by 60). However, Fahlenkamp does not expressly disclose a synchronous rectifier module comprising: a controlled switching element, having a control terminal; and the control circuit, wherein the secondary output of the control circuit is coupled to control the control terminal of the controlled switching element.
Xiong teaches (see figures 1-6) a synchronous rectifier module (figure 1, part synchronous rectifier module generated by 6 and Q1/Q2) comprising: a controlled switching element (figure 1, part Q1/Q2), having a control terminal (figure 1, part control terminal of Q1/Q2); and the control circuit (figure 1, part 6), wherein the secondary output of the control circuit (figure 1, part secondary output of the control circuit 6 that output PWM_4/PWM_3) is coupled to control the control terminal of the controlled switching element (figure 1, part Q1/Q2) (paragraph [0024]; The synchronous rectifier circuit 5 is electrically connected with the secondary winding N2 of the transformer 4. The synchronous rectifier circuit 5 includes at least two synchronous rectifier switches Q1 and Q2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain a synchronous rectifier module comprising: a controlled switching element, having a control terminal; and the control circuit according to claim 2, wherein the secondary output of the control circuit is coupled to control the control terminal of the controlled switching element, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 10, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 9). Further, Fahlenkamp discloses (see figures 1-26) the switched mode power supply (figure 1) comprising: a first rectifier (figure 1, part 42); and a controller (figure 1, part 61) configured to provide a first pulse width modulation control signal (figure 5, part S22’). However, Fahlenkamp does not expressly disclose a first synchronous rectifier module; and a controller configured to provide a first pulse width modulation control signal to the first synchronous rectifier module.
Xiong teaches (see figures 1-6) a switched mode power supply (figure 1) comprising: a first synchronous rectifier module (figure 1, part first synchronous rectifier module generated by 6 and Q1); and a controller (figure 1, part 9) configured to provide a first pulse width modulation control signal (figure 1, part PWM1) to the first synchronous rectifier module (figure 1, part first synchronous rectifier module generated by 6 and Q1; at 7 input).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain the switched mode power supply comprising: a first synchronous rectifier module; and a controller configured to provide a first pulse width modulation control signal to the first synchronous rectifier module, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 11, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 10). Further, Fahlenkamp discloses (see figures 1-26) a second rectifier (figure 1, part 41); wherein the controller (figure 1, part 61) is further configured to provide a second PWM control signal (figure 5, part S21’). However, Fahlenkamp does not expressly disclose a second synchronous rectifier module; wherein the controller is further configured to provide a second PWM control signal to the second synchronous rectifier module.
Xiong teaches (see figures 1-6) a second synchronous rectifier module (figure 1, part second synchronous rectifier module generated by 6 and Q2); wherein the controller (figure 1, part 9) is further configured to provide a second PWM control signal(figure 1, part PWM1) to the second synchronous rectifier module (figure 1, part second synchronous rectifier module generated by 6 and Q2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain a second synchronous rectifier module; wherein the controller is further configured to provide a second PWM control signal to the second synchronous rectifier module, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 12, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 11). Further, Fahlenkamp discloses (see figures 1-26) a first primary switching element (figure 1, part 22); and a second primary switching element (figure 1, part 21), wherein control a control terminal of the first primary switching element (figure 1, part control terminal of 22) and control a control terminal of the second primary switching element (figure 1, part control terminal of 21). However, Fahlenkamp does not expressly disclose the primary pulse width modulation control signal of the first synchronous rectifier module is coupled to control a control terminal of the first primary switching element and the primary pulse width modulation control signal of the second synchronous rectifier module is coupled to control a control terminal of the second primary switching element.
Xiong teaches (see figures 1-6) a first primary switching element (figure 1, part M2); and a second primary switching element (figure 1, part M1), wherein the primary pulse width modulation control signal (figure 1, part primary pulse width modulation control signal PWM_2 output from 6) of the first synchronous rectifier module (figure 1, part first synchronous rectifier module generated by 6 and Q1) is coupled to control a control terminal of the first primary switching element (figure 1, part control terminal of M2) and the primary pulse width modulation control signal (figure 1, part primary pulse width modulation control signal PWM_1 output from 6) of the second synchronous rectifier module (figure 1, part second synchronous rectifier module generated by 6 and Q2) is coupled to control a control terminal of the second primary switching element (figure 1, part control terminal of M1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain a first primary switching element; and a second primary switching element, wherein the primary pulse width modulation control signal of the first synchronous rectifier module is coupled to control a control terminal of the first primary switching element and the primary pulse width modulation control signal of the second synchronous rectifier module is coupled to control a control terminal of the second primary switching element, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 13, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 11). Further, Fahlenkamp discloses (see figures 1-26) a first primary switching element (figure 1, part 22); and a second primary switching element (figure 1, part 21), wherein control a control terminal of the first primary switching element (figure 1, part control terminal of 22) and control a control terminal of the second primary switching element (figure 1, part control terminal of 21). However, Fahlenkamp does not expressly disclose a third synchronous rectifier module; and a fourth synchronous rectifier module, wherein the controller is configured to provide the first pulse width modulation control signal to the fourth synchronous rectifier module and the second pulse width modulation control signal to the third synchronous rectifier module, wherein the primary pulse width modulation control signal of one of the first synchronous rectifier module and the fourth synchronous rectifier module is coupled to control a control terminal of the first primary switching element and the primary pulse width modulation control signal of one of the second synchronous rectifier module and the third synchronous rectifier module is coupled to control a control terminal of the second primary switching element.
Xiong teaches (see figures 1-6) a first primary switching element (figure 4, part M2); a second primary switching element (figure 4, part M1); a third synchronous rectifier module (figure 4, part third synchronous rectifier module generated by 6 and lower Q1); and a fourth synchronous rectifier module (figure 4, part fourth synchronous rectifier module generated by 6 and lower Q2), wherein the controller (figure 4, part 9) is configured to provide the first pulse width modulation control signal (figure 4, part primary pulse width modulation control signal PWM_3b output from 6) to the fourth synchronous rectifier module (figure 4, part fourth synchronous rectifier module generated by 6 and lower Q2) and the second pulse width modulation control signal (figure 4, part second pulse width modulation control signal PWM_4b output from 6) to the third synchronous rectifier module (figure 4, part third synchronous rectifier module generated by 6 and lower Q1), wherein the primary pulse width modulation control signal (figure 4, part primary pulse width modulation control signal PWM_2a output from 6) of one of the first synchronous rectifier module (figure 1, part first synchronous rectifier module generated by 6 and upper Q1) and the fourth synchronous rectifier module (figure 4, part fourth synchronous rectifier module generated by 6 and lower Q2) is coupled to control a control terminal of the first primary switching element (figure 4, part M2) and the primary pulse width modulation control signal (figure 4, part primary pulse width modulation control signal PWM_1a output from 6) of one of the second synchronous rectifier module (figure 4, part second synchronous rectifier module generated by 6 and upper Q2) and the third synchronous rectifier module (figure 4, part third synchronous rectifier module generated by 6 and lower Q1) is coupled to control a control terminal of the second primary switching element (figure 4, part control terminal of M1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain a first primary switching element; a second primary switching element; a third synchronous rectifier module; and a fourth synchronous rectifier module, wherein the controller is configured to provide the first pulse width modulation control signal to the fourth synchronous rectifier module and the second pulse width modulation control signal to the third synchronous rectifier module, wherein the primary pulse width modulation control signal of one of the first synchronous rectifier module and the fourth synchronous rectifier module is coupled to control a control terminal of the first primary switching element and the primary pulse width modulation control signal of one of the second synchronous rectifier module and the third synchronous rectifier module is coupled to control a control terminal of the second primary switching element, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 14, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 12). Further, Fahlenkamp discloses (see figures 1-26) a first transformer (figure 1, part 30), and wherein: the first primary switching element (figure 1, part 22) and the second primary switching element are connected in series (figure 1, part 21) at a switching node (figure 1, part switching node between 22 and 21); the switching node (figure 1, part switching node between 22 and 21) is coupled to a primary winding of the first transformer (figure 1, part 31); the first rectifier (figure 1, part 42) is coupled to a first end of a secondary winding of the first transformer (figure 1, part lower end of 32); the second rectifier (figure 1, part 41) is coupled to a second end of the secondary winding of the first transformer (figure 1, part upper end of 32). However, Fahlenkamp does not expressly disclose the first synchronous rectifier module is coupled to a first end of a secondary winding of the first transformer; the second synchronous rectifier module is coupled to a second end of the secondary winding of the first transformer; and the secondary winding of the first transformer has a center tap, configured to be coupled to a load.
Xiong teaches (see figures 1-6) a first transformer (figure 1, part 4), and wherein: the first primary switching element (figure 1, part M2) and the second primary switching element (figure 1, part M1) are connected in series at a switching node (figure 1, part switching node between M2 and M1); the switching node (figure 1, part switching node between M2 and M1) is coupled to a primary winding of the first transformer (figure 1, part N1); the first synchronous rectifier module (figure 1, part first synchronous rectifier module generated by 6 and Q1) is coupled to a first end of a secondary winding of the first transformer (figure 1, part upper terminal of N2); the second synchronous rectifier module (figure 1, part second synchronous rectifier module generated by 6 and Q2) is coupled to a second end of the secondary winding of the first transformer (figure 1, part lower terminal of N2); and the secondary winding of the first transformer has a center tap (figure 1, part center tap of N2), configured to be coupled to a load (figure 1, part load connected to output at Vout).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the converter of Fahlenkamp with the converter features as taught by Xiong and obtain a first transformer, and wherein: the first primary switching element and the second primary switching element are connected in series at a switching node; the switching node is coupled to a primary winding of the first transformer; the first synchronous rectifier module is coupled to a first end of a secondary winding of the first transformer; the second synchronous rectifier module is coupled to a second end of the secondary winding of the first transformer; and the secondary winding of the first transformer has a center tap, configured to be coupled to a load, because it provides more efficient power conversion with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 21, Fahlenkamp discloses everything claimed as applied above (see claim 20). Further, Fahlenkamp discloses (see figures 1-26) the control of the primary switching element (figure 1, part 41/42) via the first control pulse and the second control pulse (figure 3, part first and second control pulse of S21’/S22’); and wherein a secondary winding of the transformer (figure 1, part 32 of 30) is operative to produce an output voltage (figure 1, part Vout) to power a load (figure 1, part load connected between 13/14), the secondary winding (figure 1, part 32) magnetically coupled to the primary winding of the transformer (figure 1, part 31 of 30). However, Fahlenkamp does not expressly disclose operative to control flow of current through a primary winding of a transformer.
Xiong teaches (see figures 1-6) the control of the primary switching element (figure 1, part M1/M2) via the first control pulse and the second control pulse (figure 1, part first and second control pulse of PWM1) via is operative to control flow of current through a primary winding of a transformer (figure 1, part N1 of 4); and wherein a secondary winding of the transformer (figure 1, part N2 of 4) is operative to produce an output voltage to power a load (figure 1, part Vout), the secondary winding (figure 1, part N2) magnetically coupled to the primary winding of the transformer (figure 1, part N1 of 4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the converter of Fahlenkamp with the converter features as taught by Xiong and obtain the control of the primary switching element via the first control pulse and the second control pulse is operative to control flow of current through a primary winding of a transformer; and wherein a secondary winding of the transformer is operative to produce an output voltage to power a load, the secondary winding magnetically coupled to the primary winding of the transformer, because it provides more efficient power conversion with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Regarding claim 25, Fahlenkamp discloses everything claimed as applied above (see claim 1). Further, Fahlenkamp discloses (see figures 1-26) the control of the primary switching element (figure 1, part 41/42) via the generated primary pulse width modulated control signal (figure 5, part S41/S42); wherein the control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) is further operative to derive a secondary switch control signal (figure 5, part S21s/S22s) from the received pulse width modulated control signal (figure 5, part S21’/S22’ from 61), the secondary switch control signal (figure 5, part S21s/S22s) operative to control a secondary switching element (figures 1 and 5, part 21/22) of the switched mode power supply (figures 1). However, Fahlenkamp does not expressly disclose operative to control flow of current through a primary winding of the transformer to a circuit node coupling multiple capacitors in series; and the secondary switching element disposed in a synchronous rectifier module of the switched mode power supply; and wherein the synchronous rectifier module is operative to control flow of current through a secondary winding of the transformer, the secondary winding magnetically coupled to the primary winding of the transformer.
Xiong teaches (see figures 1-6) the control of the primary switching element (figure 1, part M1/M2) via the generated primary pulse width modulated control signal (figure 1, part PWM_1/PWM_2) is operative to control flow of current through a primary winding of the transformer (figure 1, part N1 of 4) to a circuit node coupling multiple capacitors in series (figure 1, part circuit node coupling multiple capacitors in series at 3); wherein the control logic (figure 1, parts 60-65) is further operative to derive a secondary switch control signal (figure 1, part PWM_3/PWM_4) from the received pulse width modulated control signal (figure 1, part PWM1), the secondary switch control signal (figure 1, part PWM_3/PWM_4) operative to control a secondary switching element (figure 1, part Q1/Q2) of the switched mode power supply (figure 1), the secondary switching element (figure 1, part Q1/Q2) disposed in a synchronous rectifier module (figure 1, part synchronous rectifier module generated by 6 and Q1/Q2) of the switched mode power supply (figure 1); and wherein the synchronous rectifier module (figure 1, part synchronous rectifier module generated by 6 and Q1/Q2) is operative to control flow of current through a secondary winding of the transformer (figure 1, part N2 of 4), the secondary winding (figure 1, part N2) magnetically coupled to the primary winding of the transformer (figure 1, part N1 of 4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the converter of Fahlenkamp with the converter features as taught by Xiong and obtain the control of the primary switching element via the generated primary pulse width modulated control signal is operative to control flow of current through a primary winding of the transformer to a circuit node coupling multiple capacitors in series; wherein the control logic is further operative to derive a secondary switch control signal from the received pulse width modulated control signal, the secondary switch control signal operative to control a secondary switching element of the switched mode power supply, the secondary switching element disposed in a synchronous rectifier module of the switched mode power supply; and wherein the synchronous rectifier module is operative to control flow of current through a secondary winding of the transformer, the secondary winding magnetically coupled to the primary winding of the transformer, because it provides more efficient power conversion with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp, in view of Xiong et al. (US 2022/0131471), hereinafter Xiong, and further in view of Lou et al. (US 2022/0385198), hereinafter Lou.
Regarding claim 15, Fahlenkamp and Xiong teach everything claimed as applied above (see claim 13). Further, Fahlenkamp discloses (see figures 1-26) a first transformer (figure 1, part 30), and wherein: the first primary switching element (figure 1, part 22) and the second primary switching element are connected in series (figure 1, part 21) at a switching node (figure 1, part switching node between 22 and 21); the switching node (figure 1, part switching node between 22 and 21) is coupled to a primary winding of the first transformer (figure 1, part 31); the first rectifier (figure 1, part 42) is coupled to a first end of a secondary winding of the first transformer (figure 1, part lower end of 32); the second rectifier (figure 1, part 41) is coupled to a second end of the secondary winding of the first transformer (figure 1, part upper end of 32). However, Fahlenkamp does not expressly disclose a second transformer, and wherein: a primary winding of the second transformer is in series with the primary winding of the first transformer; the first synchronous rectifier module is coupled to a first end of a secondary winding of the first transformer; the second synchronous rectifier module is coupled to a second end of the secondary winding of the first transformer; and the secondary winding of the first transformer has a center tap, the center tap configured to be coupled to a load, the fourth synchronous rectifier module is coupled to a first end of a secondary winding of the second transformer; the third synchronous rectifier module is coupled to a second end of the secondary winding of the second transformer; and the secondary winding of the second transformer has a center tap, coupled to the center tap of the first transformer.
Xiong teaches (see figures 1-6) a first transformer (figure 4, part upper 4) and a second transformer (figure 4, part lower 4), and wherein: the first primary switching element (figure 4, part M2) and the second primary switching element (figure 4, part M1) are connected in series at a switching node (figure 4, part switching node between M2 and M1); the switching node (figure 4, part switching node between M2 and M1) is coupled to a primary winding of the first transformer (figure 4, part upper N1); the first synchronous rectifier module (figure 4, part upper first synchronous rectifier module generated by 6 and Q1) is coupled to a first end of a secondary winding of the first transformer (figure 4, part upper terminal of upper N2); the second synchronous rectifier module (figure 4, part second synchronous rectifier module generated by 6 and upper Q2) is coupled to a second end of the secondary winding of the first transformer (figure 4, part lower terminal of upper N2); and the secondary winding of the first transformer has a center tap (figure 4, part center tap of upper N2), the center tap configured to be coupled to a load (figure 4, part load connected to output at Vout); the fourth synchronous rectifier module (figure 4, part fourth synchronous rectifier module generated by 6 and lower Q2) is coupled to a first end of a secondary winding of the second transformer (figure 4, part lower end of lower N2); the third synchronous rectifier module (figure 4, part third synchronous rectifier module generated by 6 and lower Q1) is coupled to a second end of the secondary winding of the second transformer figure 4, part upper end of lower N2); and the secondary winding of the second transformer has a center tap (figure 4, part center tap of lower N2), coupled to the center tap of the first transformer (figure 4, part center tap of upper N2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the converter of Fahlenkamp with the converter features as taught by Xiong, because it provides more efficient power conversion with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Lou teaches (see figures 1-7) a first transformer (figure 1, part upper 115) and a second transformer (figure 1, part lower 115), and wherein: the first primary switching element (figure 1, part Q2) and the second primary switching element (figure 1, part Q1) are connected in series at a switching node (figure 1, part switching node between Q2 and Q1); the switching node (figure 1, part switching node between Q2 and Q1) is coupled to a primary winding of the first transformer (figure 1, part 112a/112b); a primary winding of the second transformer (figure 1, part 124a/124b) is in series with the primary winding of the first transformer (figure 1, part 112a/112b).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Fahlenkamp and Xiong with the power converter features as taught by Lou and obtain a first transformer and a second transformer, and wherein: the first primary switching element and the second primary switching element are connected in series at a switching node; the switching node is coupled to a primary winding of the first transformer; a primary winding of the second transformer is in series with the primary winding of the first transformer; the first synchronous rectifier module is coupled to a first end of a secondary winding of the first transformer; the second synchronous rectifier module is coupled to a second end of the secondary winding of the first transformer; and the secondary winding of the first transformer has a center tap, the center tap configured to be coupled to a load, the fourth synchronous rectifier module is coupled to a first end of a secondary winding of the second transformer; the third synchronous rectifier module is coupled to a second end of the secondary winding of the second transformer; and the secondary winding of the second transformer has a center tap, coupled to the center tap of the first transformer, because it improves efficiency of the power conversion and reduce power losses (paragraph [0014]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Fahlenkamp et al. (US 2009/0086512), hereinafter Fahlenkamp, in view of Jacobs et al. (US 6,078,509), hereinafter Jacobs, and further in view of Xiong et al. (US 2022/0131471), hereinafter Xiong.
Regarding claim 17, Fahlenkamp and Jacobs teach everything claimed as applied above (see claim 16). Further, Fahlenkamp discloses (see figures 1-26) secondary delay logic (figure 5, part 631/632) operative to delay rising edges (figure 5, part 631/632) of the received pulse width modulated control signal (figures 3 and 5, part S21’/S22’ from 61) to produce a secondary pulse width modulated control signal (figures 3 and 5, part S21s/S22s [S21/S22]); and apply the secondary pulse width modulated control signal (figures 3 and 5, part S21s/S22s [S21/S22]) to control a switch (figures 3 and 5, part S21s/S22s [S21/S22]). However, Fahlenkamp does not expressly disclose a synchronous rectifier module.
Xiong teaches (see figures 1-6) secondary delay logic (figure 1, part 61) operative to delay rising edges (figure 1, part 61) of the received pulse width modulated control signal (figure 1, part PWM2/PWM3) to produce a secondary pulse width modulated control signal (figure 1, part PWM_3/PWM_4); and apply the secondary pulse width modulated control signal (figure 1, part PWM_3/PWM_4) to control a switch (figure 1, part Q1/Q2) in a synchronous rectifier module (figure 1, part synchronous rectifier module generated by 6 and Q1/Q2) (paragraph [0024]; The synchronous rectifier circuit 5 is electrically connected with the secondary winding N2 of the transformer 4. The synchronous rectifier circuit 5 includes at least two synchronous rectifier switches Q1 and Q2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the rectifier of Fahlenkamp with the synchronous rectifier features as taught by Xiong and obtain secondary delay logic operative to delay rising edges of the received pulse width modulated control signal to produce a secondary pulse width modulated control signal; and apply the secondary pulse width modulated control signal to control a switch in a synchronous rectifier module, because it provides more efficient rectification stage with reduction in the number of signal lines and the wiring area on the system board (paragraph [0002]).
Allowable Subject Matter
Claims 18, 19, 23 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable upon overcoming objections set forth in this action and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination) :
Regarding claim 18, the control of the primary switching element is operative to control flow of first current through a first winding of the transformer;
(Examiner note: the allowable subject matter is in view of the control logic in combination with the primary/secondary side of the transformer operation)
Regarding claim 19, claim 19 is dependent claim of claim 18, therefore, is objected by the same reason presented above;
Regarding claim 23, second delay logic operative to derive a switch control signal from the control pulses in the received pulse width modulated control signal, the switch control signal including a first switch control pulse and a second switch control pulse to control operation of a secondary switching element disposed in a synchronous rectifier module, the synchronous rectifier module coupled to the secondary winding of the transformer;
(Examiner note: the allowable subject matter is in view of the control logic in combination with the primary/secondary side of the transformer operation)
Regarding claim 24, claim 24 is dependent claim of claim 23, therefore, is objected by the same reason presented above;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments filed 04/15/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 1-4 of the Applicant's Response (“Applicants respectfully submit that the claimed invention includes limitations over the cited prior art and that the combination of references does not render the claimed invention as being obvious… In contrast to Fahlenkampf, the claimed invention recites a control circuit for controlling multiple switching elements of a switched-mode power supply, the control circuit comprising: a control input operative to receive a pulse width modulated control signal comprising a series of control pulses; a primary output operative to control a primary switching element of the switched-mode power supply; control logic operative to generate a primary pulse width modulated control signal based on the received pulse width modulated control signal, the primary pulse width modulated control signal comprising a series of primary pulses, the generated primary pulse width modulated control signal outputted from the primary output to control the primary switching element; wherein the primary PWM control signal is generated such that the series of primary pulses are controlled to occur between the control pulses”).
The Examiner respectfully disagrees with Applicant’s arguments, because Fahlenkamp discloses a control circuit (figures 1 and 5, part control circuit generated by 60) for controlling switching elements (figure 1, parts 21, 22, 41 and 42) of a switched-mode power supply (figure 1), the control circuit (figures 1 and 5, part control circuit generated by 60) comprising: a control input (figure 5, part control input at 63; where input S21’/S22’) operative to receive a pulse width modulated control signal (figure 5, part S21’/S22’ from 61) comprising a series of control pulses (figure 3, part S21’/S22’); a primary output (figure 5, part output at 63; where output S41/S42) operative to control a primary switching element (figure 1, part 41/42) of the switched-mode power supply (figure 1); control logic (figure 5, part control logic generated by 631/632, 633/634 and 635/636) operative to generate a primary pulse width modulated control signal (figure 5, part S41/S42) based on the received pulse width modulated control signal (figure 5, part S21’/S22’ from 61), the primary pulse width modulated control signal (figure 5, part S41/S42) comprising a series of primary pulses (figures 3 and 5, part S41/S42), the generated primary pulse width modulated control signal (figure 5, part S41/S42) outputted from the primary output (figure 5, part output at 63; where output S41/S42) to control the primary switching element (figure 1, part 41/42); and wherein the primary PWM control signal (figures 3 and 5, part S41/S42) is generated such that the series of primary pulses (figures 3 and 5, part S41/S42) are controlled to occur between the control pulses (figures 3 and 5, part S21’/S22’) (paragraphs [0054]–[0057]). Therefore, Fahlenkamp meets with the claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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