DETAILED ACTION
This action is responsive to the application filed 9 May 2024 and the Information Disclosure Statement filed 28 Apr 2025. Claims 1-18 are pending. Claims 1, 7 and 13 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28 Apr 2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“PRECHARGING METHOD AND PROGRAMMING METHOD FOR SELECTED AND UNSELECTED SUB-BLOCKS OF 3D MEMORY STRINGS IN A DEVICE”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claim(s) 3, 9, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if the 112(b) rejection below is overcome and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1, 7, and 13 state, “the precharging method comprising: selecting a word line from the top-deck word line group and the bottom-deck word line group to be programmed;” The claim is indefinite because it is unclear whether word lines are selected (one from each deck) or if one word line is selected from only one of the two decks.
Claim(s) 2-6, 8-12, and 14-18 depend on rejected claim(s) 1, 7, and 13 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 4 – 8, 10 – 14, and 16 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang, et al, U.S. Patent Application Publication 2024/0145006 (“Zhang”).
Regarding claim 1, Zhang teaches:
A precharging method for a 3D memory device, which at least comprises a top-deck word line group, a middle dummy word line group, a bottom-deck word line group, and a bottom dummy word line group arranged in sequence, (Zhang, fig 4D, “[0085] FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202. The structure of FIG. 4D includes three drain side select layers SGDO, SGDl and SGD2 (that form select lines); three source side select layers SGSO, SGSl, and SGS2 (that form select lines); dummy word line layers DOL, DOU, DlL, DII, D2L and D2U for connecting to dummy memory cells… [0090] In one set of embodiments, the data word lines are divided into three sets of data word lines… Dummy word lines DOU and DlL are positioned between the first plurality of data word lines ( e.g., WLO-WL89) and the second plurality of data word lines ( e.g., WL90-WL179). The dummy memory cells connected to dummy word lines DOU and DlL are positioned between the first sub-block SBO and the second sub-block SBl.”; a 3D memory structure with at least 3 sub-blocks, with dummy word lines between each of the sub-blocks).
the precharging method comprising: selecting a word line from the top-deck word line group and the bottom-deck word line group to be programmed; (Zhang, fig 4D, 8, “[0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…”; that NAND strings can have precharge voltages applied between programming steps).
determining whether the word line selected is in the top-deck word line group or the bottom-deck word line group; (Zhang, fig 8, “[0131] The target memory cell for programming is indicated by box 810, and resides in Subblock 1.”; that particular memory cells, associated with particular wordlines can be selected and identified with one of the subblocks).
applying a precharge on voltage to the middle dummy word line group so that a precharge voltage reaches a channel at a position corresponding to the middle dummy word line group in response to the (selected) word line being in the top-deck word line group; and (Zhang, fig 4D, 11, “[0135] The NAND string of FIG. 11 is part of a three tier architecture, [0136] To overcome the issue of the NAND channel being at a negative voltage after the previous program-verify, a new pre-charge process is proposed for a three tier architecture… The proposed pre-charging is performed by applying one or more voltages that are appropriate for pre-charging to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells.”; that memory subblocks containing the selected wordline are charged in a specific manner using the dummy lines between the subblocks).
applying a precharge off voltage to the middle dummy word line group so that the precharge voltage does not reach the channel at the position corresponding to the middle dummy word line group in response to the (selected word line being in the bottom-deck word line group. (Zhang, fig 4D, 11, 12, “[0140] In step 1208, the control circuit cuts off channels of memory cells in the second sub-block from channels of memory cells in the first subblock at the end of pre-charge by maintaining the data word lines connected to memory cells in the first sub-block at the one or more overdrive voltages while ramping down voltage on the first dummy word line(s) at end of the pre-charge and while ramping down voltage on the data word lines connected to memory cells in the second sub-block at end of the pre-charge.”; that the cells in the unselected sub-block are treated to a different dummy word line voltage to “cut off channels” between the selected and unselected sub-blocks).
Regarding claim 2, Zhang teaches The precharging method for the 3D memory device according to claim 1, wherein the 3D memory device further comprises a common source line, and the precharge voltage is applied from the common source line. (Zhang, fig 4, 14, “[0077] Below the alternating dielectric layers and word line layers is a source line layer SL. [0147] The signal WL_SSB represents the voltage on word lines in the one or more sub-blocks between the source of pre-charging (e.g., the source line SL) and sub-block that contains the selected word line WLn. [0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…. Additionally, in this example, the pre-charging is performed from the source side (see arrow 804), as the source line 806 is connected to VDDSA (a pre-charge voltage of -2.0-2.5 v)”; multiple NAND strings can have a common source line SL, and that the “precharge voltage” can be introduced via the source lines; that the precharge voltage is a value from -2.0 to + 2.5 V).
Regarding claim 4, Zhang teaches The precharging method for the 3D memory device according to claim 1, further comprising applying the precharge on voltage to the bottom dummy word line group when precharging. (Zhang, fig 12, 14, “[0149] The period of t4-t6 represents the pre-charging (step 604 of FIG. 6, steps 1202-1206 of FIG. 12). … Also at t4, DU is raised to VGP2PCH (step 1336), DL is raised to VGP2PCH (step 1336), and WL_SSB is raised to Vread (step 1332), where Vread is one example of an overdrive voltage.”; a VGP2PCH voltage (precharge on) is applied to dummy word lines between the lower sub-block dummy lines to allow connection to the SL common source line).
Regarding claim 5, Zhang teaches The precharging method for the 3D memory device according to claim 1, wherein the 3D memory device comprises an array comprising a plurality of memory cells, and the plurality of memory cells are single-level cells, multiple-level cells, triple-level cells, or quad-level cells. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Regarding claim 6, Zhang teaches The precharging method for the 3D memory device according to claim 1, wherein the 3D memory device is a 3D NAND memory device. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Regarding claim 7, Zhang teaches:
A precharging method for a 3D memory device, which at least comprises multiple decks of word line groups, a plurality of middle dummy word line groups, and a bottom dummy word line group, wherein the bottom dummy word line group is located below a lowermost deck of word line group of the multiple decks of word line groups, and each of the plurality of middle dummy word line groups is arranged between every two decks of word line groups of the multiple decks of word line groups, (Zhang, fig 4D, “[0085] FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202. The structure of FIG. 4D includes three drain side select layers SGDO, SGDl and SGD2 (that form select lines); three source side select layers SGSO, SGSl, and SGS2 (that form select lines); dummy word line layers DOL, DOU, DlL, DII, D2L and D2U for connecting to dummy memory cells… [0090] In one set of embodiments, the data word lines are divided into three sets of data word lines… Dummy word lines DOU and DlL are positioned between the first plurality of data word lines ( e.g., WLO-WL89) and the second plurality of data word lines ( e.g., WL90-WL179). The dummy memory cells connected to dummy word lines DOU and DlL are positioned between the first sub-block SBO and the second sub-block SBl.”; a 3D memory structure with at least 3 sub-blocks, with dummy word lines between each of the sub-blocks).
the precharging method comprising: selecting a word line from the multiple decks of word line groups to be programmed; (Zhang, fig 4D, 8, “[0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…”; that NAND strings can have precharge voltages applied between programming steps).
determining in which one deck of word line group of the multiple decks of word line groups the word line is located in; (Zhang, fig 8, “[0131] The target memory cell for programming is indicated by box 810, and resides in Subblock 1.”; that particular memory cells, associated with particular wordlines can be selected and identified with one of the subblocks).
applying a precharge on voltage to each middle dummy word line group below the one deck of word line group so that a precharge voltage reaches a channel at a position corresponding to each middle dummy word line group below the one deck of word line group; and (Zhang, fig 4D, 11, “[0135] The NAND string of FIG. 11 is part of a three tier architecture, [0136] To overcome the issue of the NAND channel being at a negative voltage after the previous program-verify, a new pre-charge process is proposed for a three tier architecture… The proposed pre-charging is performed by applying one or more voltages that are appropriate for pre-charging to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells.”; that memory subblocks containing the selected wordline are charged in a specific manner using the dummy lines between the subblocks).
applying a precharge off voltage to each middle dummy word line group above the one deck of word line group so that the precharge voltage does not reach the channel at the position corresponding to each middle dummy word line group above the one deck of word line group. (Zhang, fig 4D, 11, 12, “[0140] In step 1208, the control circuit cuts off channels of memory cells in the second sub-block from channels of memory cells in the first subblock at the end of pre-charge by maintaining the data word lines connected to memory cells in the first sub-block at the one or more overdrive voltages while ramping down voltage on the first dummy word line(s) at end of the pre-charge and while ramping down voltage on the data word lines connected to memory cells in the second sub-block at end of the pre-charge.”; that the cells in the unselected sub-block are treated to a different dummy word line voltage to “cut off channels” between the selected and unselected sub-blocks).
Regarding claim 8, Zhang teaches The precharging method for the 3D memory device according to claim 7, wherein the 3D memory device further comprises a common source line, and the precharge voltage is applied from the common source line. (Zhang, fig 4, 14, “[0077] Below the alternating dielectric layers and word line layers is a source line layer SL. [0147] The signal WL_SSB represents the voltage on word lines in the one or more sub-blocks between the source of pre-charging (e.g., the source line SL) and sub-block that contains the selected word line WLn. [0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…. Additionally, in this example, the pre-charging is performed from the source side (see arrow 804), as the source line 806 is connected to VDDSA (a pre-charge voltage of -2.0-2.5 v)”; multiple NAND strings can have a common source line SL, and that the “precharge voltage” can be introduced via the source lines; that the precharge voltage is a value from -2.0 to + 2.5 V).
Regarding claim 10, Zhang teaches The precharging method for the 3D memory device according to claim 7, further comprising applying the precharge on voltage to the bottom dummy word line group when precharging. (Zhang, fig 12, 14, “[0149] The period of t4-t6 represents the pre-charging (step 604 of FIG. 6, steps 1202-1206 of FIG. 12). … Also at t4, DU is raised to VGP2PCH (step 1336), DL is raised to VGP2PCH (step 1336), and WL_SSB is raised to Vread (step 1332), where Vread is one example of an overdrive voltage.”; a VGP2PCH voltage (precharge on) is applied to dummy word lines between the lower sub-block dummy lines to allow connection to the SL common source line).
Regarding claim 11, Zhang teaches The precharging method for the 3D memory device according to claim 7, wherein the 3D memory device comprises an array comprising a plurality of memory cells, and the plurality of memory cells are single-level cells, multiple-level cells, triple-level cells, or quad-level cells. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Regarding claim 12, Zhang teaches The precharging method for the 3D memory device according to claim 7, wherein the 3D memory device is a 3D NAND memory device. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Regarding claim 13, Zhang teaches:
A programming method for a 3D memory device, which at least comprises a top-deck word line group, a middle dummy word line group, a bottom-deck word line group, and a bottom dummy word line group arranged in sequence, (Zhang, fig 4D, “[0085] FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202. The structure of FIG. 4D includes three drain side select layers SGDO, SGDl and SGD2 (that form select lines); three source side select layers SGSO, SGSl, and SGS2 (that form select lines); dummy word line layers DOL, DOU, DlL, DII, D2L and D2U for connecting to dummy memory cells… [0090] In one set of embodiments, the data word lines are divided into three sets of data word lines… Dummy word lines DOU and DlL are positioned between the first plurality of data word lines ( e.g., WLO-WL89) and the second plurality of data word lines ( e.g., WL90-WL179). The dummy memory cells connected to dummy word lines DOU and DlL are positioned between the first sub-block SBO and the second sub-block SBl.”; a 3D memory structure with at least 3 sub-blocks, with dummy word lines between each of the sub-blocks).
the programming method comprising: selecting a word line from the top-deck word line group and the bottom-deck word line group to be programmed; (Zhang, fig 4D, 8, “[0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…”; that NAND strings can have precharge voltages applied between programming steps).
determining whether the word line selected is in the top-deck word line group or the bottom-deck word line group; (Zhang, fig 8, “[0131] The target memory cell for programming is indicated by box 810, and resides in Subblock 1.”; that particular memory cells, associated with particular wordlines can be selected and identified with one of the subblocks).
applying a precharge on voltage to the middle dummy word line group so that a precharge voltage reaches a channel at a position corresponding to the middle dummy word line group in response to the word line being in the top-deck word line group; (Zhang, fig 4D, 11, “[0135] The NAND string of FIG. 11 is part of a three tier architecture, [0136] To overcome the issue of the NAND channel being at a negative voltage after the previous program-verify, a new pre-charge process is proposed for a three tier architecture… The proposed pre-charging is performed by applying one or more voltages that are appropriate for pre-charging to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells.”; that memory subblocks containing the selected wordline are charged in a specific manner using the dummy lines between the subblocks).
applying a precharge off voltage to the middle dummy word line group so that the precharge voltage does not reach the channel at the position corresponding to the middle dummy word line group in response to the word line being in the bottom-deck word line group; and (Zhang, fig 4D, 11, 12, “[0140] In step 1208, the control circuit cuts off channels of memory cells in the second sub-block from channels of memory cells in the first subblock at the end of pre-charge by maintaining the data word lines connected to memory cells in the first sub-block at the one or more overdrive voltages while ramping down voltage on the first dummy word line(s) at end of the pre-charge and while ramping down voltage on the data word lines connected to memory cells in the second sub-block at end of the pre-charge.”; that the cells in the unselected sub-block are treated to a different dummy word line voltage to “cut off channels” between the selected and unselected sub-blocks).
applying a programming voltage to the word line selected after completing applying the precharge voltage. (Zhang, fig 6, “ [0114] In step 602 of FIG. 6, the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., 12-16V or another suitable level) and”; a memory cell is programmed with a higher voltage after the string is precharged).
Regarding claim 14, Zhang teaches The programming method for the 3D memory device according to claim 13, wherein the 3D memory device further comprises a common source line, and the precharge voltage is applied from the common source line. (Zhang, fig 4, 14, “[0077] Below the alternating dielectric layers and word line layers is a source line layer SL. [0147] The signal WL_SSB represents the voltage on word lines in the one or more sub-blocks between the source of pre-charging (e.g., the source line SL) and sub-block that contains the selected word line WLn. [0131] FIG. 8 depicts a NAND string being pre-charged as part of a process to inhibit the NAND string from programming during a programming process…. Additionally, in this example, the pre-charging is performed from the source side (see arrow 804), as the source line 806 is connected to VDDSA (a pre-charge voltage of -2.0-2.5 v)”; multiple NAND strings can have a common source line SL, and that the “precharge voltage” can be introduced via the source lines; that the precharge voltage is a value from -2.0 to + 2.5 V).
Regarding claim 16, Zhang teaches The programming method for the 3D memory device according to claim 13, further comprising applying the precharge on voltage to the bottom dummy word line group when precharging. (Zhang, fig 12, 14, “[0149] The period of t4-t6 represents the pre-charging (step 604 of FIG. 6, steps 1202-1206 of FIG. 12). … Also at t4, DU is raised to VGP2PCH (step 1336), DL is raised to VGP2PCH (step 1336), and WL_SSB is raised to Vread (step 1332), where Vread is one example of an overdrive voltage.”; a VGP2PCH voltage (precharge on) is applied to dummy word lines between the lower sub-block dummy lines to allow connection to the SL common source line).
Regarding claim 17, Zhang teaches The programming method for the 3D memory device according to claim 13, wherein the 3D memory device comprises an array comprising a plurality of memory cells, and the plurality of memory cells are single-level cells, multiple-level cells, triple-level cells, or quad-level cells. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Regarding claim 18, Zhang teaches The programming method for the 3D memory device according to claim 13, wherein the 3D memory device is a 3D NAND memory device. (Zhang, figs 4, 5, “[0099] Although the example memory of FIGS. 4-41 is a three dimensional memory structure that includes vertical NAND strings with charge-trapping material,… [0101] FIGS. SB-F illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”).”; the methods can be applied to a NAND string of memory, the memory cells can be SLC or MLC).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825