Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (High-performance waveguide coupled Germanium-on-silicon single-photon avalanche diode with independently controllable absorption and multiplication. Nanophotonics. 2023 Feb 14;12(4):705-714; “Wang”), as evidenced by Gao et al. (Si/Ge phototransistor with responsivity >1000A/W on a silicon photonics platform, Opt. Express 32, 2271-2280 (2024); “Gao”), in view of Langstaff et al. (A fully integrated multi-channel detector for electron spectroscopy, Nuclear Instruments and Methods in Physics Research B 238 (2005) 219–223; “Langstaff”), further in view of Schiller et al. (2019/0305764; “Schiller”), and further in view of Liu et al. (Reduced effect of single-photon-detector deadtime using a switchable detector array in an orbital-angular-momentum (OAM) encoded quantum system, 2017 Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, USA, 2017, pp. 1-2; “Liu”).
Regarding claim 1, Wang discloses in figure 1, and related figures and text, for example, Selected Text, embodiments of single photon detectors comprising waveguide couple Ge-Si photon absorbers with three terminals: “By providing two separate voltage drops , the drift and multiplication of carriers can be optimized separately. Benefitting from this structure, two separate voltage drops can be controlled on the absorption and multiplication regions. More specifically, V S1 dynamically manipulates the electric field in the Ge layer, separates photon-generated electron-hole pairs and drives electrons toward charge multiplication.” See below Wang, figures 1 and 2, and related figures and text, for example, Selected Text.
Regarding Wang’s photon/photoelectron structural embodiments, Gao evinces that, “This interplay between the structural elements and carrier dynamics is crucial for the observed improvement in photocurrent. The internal gain of the photo response and the dark current, determined by the base current (photo-generated carriers), can be adjusted by modulating the intensity of the injected light. The geometrical details of the p+-doped regions, particularly their width and separation, have a significant impact on the performance metrics of the phototransistor. See below Gao, figure 1, and related figures and text, for example, Selected Text.
Further regarding claim 1, Wang as evidenced by Gao does not explicitly disclose multi-channel photon/photoelectron detection embodiments.
However, Langstaff discloses, in figure 1, and related figures and text, for example, Selected Text, multi-channel detection embodiments: “The detector chip contains a number of channels, or pixels… Each channel has an anode to collect the electrons as they emerge … …to enable real-time measurements. ...the electron pulse is detected by the collector anodes of the array. … to accumulate the counts as they arrive and circuitry to read out the data sequentially from all channels in the array.” See below Langstaff, figure 1, and related figures and text, for example, Selected Text.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Wang as evidenced by Gao to disclose a plurality of carrier channels; Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; because the resultant multichannel configuration and related method would be ‘reliable and robust and able to out-perform existing single-channel detector systems.” Langstaff, figure 1, and related figures and text, for example, Selected Text.
Further regarding claim 1, Schiller discloses in figures 2 and 3, and related figures and text, for example, Selected Text, programmable embodiments of switch-controlled multi-path delay circuits:
“FIG. 2 illustrates an example delay circuit schematic. Programmable CMOS delay circuit (“delay circuit”) … includes an input node … a low-delay path [including] resistive switches…, a high delay [including] resistive switches… and an output node .... Each resistive switch … includes control lines …When control line … is a high signal and control line… is a low signal, the switch closes (i.e. current passes through the switch). …There is a small period of time when the signal has arrived at the input of buffer … and has not yet been … transmitted … This propagation delay, along with propagation delays of the rest of the low-delay path and buffer … are the minimum configurable delay of delay circuit …”
Based on the specific application … controller …stores information about configurations of resistive switches, including which switches to close to achieve a certain delay…, control signals for certain resistive switches include a primary control signal (i.e. “high” means closed, “low” means open) and an inverted control signal (i.e. “low” means closed, “high” means open). In some other examples, control signals for certain resistive switches include a primary control signal…. controller … calculates, based on the resistance of each resistive switch, which switches should be closed to achieve the proper ratio of effective resistances for the desired delay.
See below Schiller, figures 2 and 3, and related figures and text, for example, Selected Text.
Consequently, in light of Schiller’s disclosure of programmable switch networks, it would have been obvious to one of ordinary skill in the art to modify Wang, as evidenced by Gao, in view of Langstaff to disclose a carrier-modulated waveguide structure comprising: a semiconductor bias unit which includes a first semiconductor layer, a bias intrinsic layer, and a second semiconductor layer, one side of the first semiconductor layer and one side of the second semiconductor layer correspondingly connected to two opposite sides of the bias intrinsic layer; a light absorbing component arranged over a part of the first semiconductor layer, the bias intrinsic layer, and a part of the second semiconductor layer; and a transporting control element having a main body and a plurality of carrier channels each spaced apart from both sides of adjacent carrier channels, one side of the main body disposed on the light absorbing component and another side of the main body extending to form the plurality of the carrier channels coupled to a plurality of light sensors one by one correspondingly; wherein a sum of probabilities of carrier transporting of the carrier channels is 1; Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; because the resulting multi-channel photoelectron (density) counting configurations and methods would facilitate designing, fabricating, and deploying single-photon quantum systems not hindered by single photon detector deadtimes. See below Liu, figures 1-5, and related figures and text, for example, Selected Text (“We explore using a switchable detector array to reduce the deadtime effect in an … encoded quantum system…A key challenge for quantum systems is the “deadtime” of the single photon detector, which is the time needed to recover for registering the next photon after a detector fires. Since a detector does not response to any newly-arriving photon during the deadtime, the incident photon rate of the overall system would be limited by the detector’s deadtime … Since the switchable detector array is able to route an incoming photon to a designed detector, the overall effect of detector deadtime could be reduced.”).
Wang, Figures 1 and 2, and Selected Text
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Abstract: Germanium-on-silicon (Ge-on-Si) single photon avalanche diodes (SPADs) have received wide attention in recent years due to their potential to be integrated with Si photonics. In this work, we propose and demonstrate a high-performance waveguide coupled Ge-on-Si separate absorption- charge-multiplication SPAD with three electric terminals. By providing two separate voltage drops on the light absorption and multiplication regions, the drift and multiplication of carriers can be optimized separately. This indeed improves the freedom of voltage regulation for both areas. .
The three electric terminals SPAD contains two junctions, one is between P-doped Ge and P-doped Si, and the other is between N-doped and P-doped Si. P-doped Si is set as ground, and voltages (i.e., V S1 and V S2) are loaded on the P-doped Ge and N-doped Si, respectively. Benefitting from this structure, two separate voltage drops can be controlled on the absorption and multiplication regions. More specifically, V S1 dynamically manipulates the electric field in the Ge layer, separates photon-generated electron-hole pairs and drives electrons toward charge multiplication, while V S2 is in charge of the electric field in the intrinsic silicon for multiplication. It is worth noting that being different from the conventional SACM structure which has only one bias voltage to simultaneously control the light absorption and charge multiplication regions, the proposed three-terminal SPAD provides two separate voltage drops for independent manipulations, offering a better regulation of the voltage for both areas. Moreover, thanks to the separate controlling, doping profile of the charge layer is greatly released compared to that of the conventional device because of the flexible carrier injection.
Gao, Figure 1 and Selected Text
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Abstract: In this article, we report a Si/Ge waveguide phototransistor with high responsivity and low dark current under low bias voltages, due to an engineered electric field distribution. Here we demonstrate a Si/Ge phototransistor that operates at the conventional optical band centred at 1550 nm, with high responsivity, low dark current and low phase noise. The devices are fabricated using a standard silicon photonics fabrication technology without modification or post processing. The key innovation compared to previous work is the introduction of floating p+-doped regions beneath the photosensitive germanium, allowing the passive manipulation of the electric field, with concomitant suppression of dark current generated at the Ge-Si interface. This interplay between the structural elements and carrier dynamics is crucial for the observed improvement in photocurrent. The internal gain of the photo response and the dark current, determined by the base current (photo-generated carriers), can be adjusted by modulating the intensity of the injected light. The geometrical details of the p+-doped regions, particularly their width and separation, have a significant impact on the performance metrics of the phototransistor, …
Reducing the separation between the p+ regions, while maintaining their individual widths, effectively narrows the high potential barrier regions, as depicted in Fig. 1. This narrowing makes it more challenging for carriers to traverse these barriers directly. Consequently, more carriers are inclined to follow the lower potential barrier path along the Si/Ge interface, which is not within the p+ regions. This shift in carrier path effectively broadens the overall low potential pathway for carrier transportation across the device, enhancing conductivity under both dark and illuminated conditions. This change results in the observed increase in both dark current and photocurrent. Moreover, the expansion of this lower potential pathway predominantly occurs at the Si/Ge interface. This interface is significant due to the excess carriers generated by the Si/Ge lattice mismatch. Therefore, an increase in the interface area not only augments the overall carrier pathway but also intensifies the generation of dark current due to the lattice mismatch-induced excess carriers. The key to optimizing the spacing between p+ regions lie in balancing the trade-offs between dark current and responsivity. The optimal spacing is determined by the specific application’s requirements and its tolerance for dark current.
Langstaff, Figure 1 and Selected Text
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Abstract. In electron spectroscopy, multi-channel detection combined with intense radiation sources provides the optimum experimental configuration. Building on the 5 mm, 192-channel ion detector developed at Aberystwyth, longer arrays have been fabricated for the detection of electrons in a commercial hemispherical analyser. The performance and reliability of a 10 mm, 384-detector array is discussed and the first array-detected photoelectron spectroscopy data for single- crystal diamond are presented. In scanning mode, the detector shows a large improvement compared to single channeltron detection and this improvement allows data to be collected in snapshot mode (1 s per spectrum) to enable real-time measurements.
The detector operation is illustrated schematically in Fig. 1. An electron incident on the MCP is amplified and the electron pulse is detected by the collector anodes of the array.
The detector chip contains a number of channels, or pixels, … a device containing 384 channels …[a] device containing 768 channels with a total active area of 19.2 mm · 3 mm is currently being characterised. Each channel has a metal anode to collect the electrons as they emerge … a charge sensitive amplifier to produce a digital signal in response to the electron pulse, … to accumulate the counts as they arrive and circuitry to read out the data sequentially from all channels in the array.
To enable real-time measurements, data must be recorded with a collection time smaller than the timescale of the process under investigation
Conclusions. A fully integrated 384-channel electron detector has been successfully constructed and incorporated into a hemispherical electron energy analyser for photoelectron spectroscopy. Test results confirm that the detector is reliable and robust and is able to out-perform existing single-channel detector systems.
Schiller, Figures 2 and 3, and Selected Text
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[0029] FIG. 2 illustrates an example delay circuit schematic. Programmable CMOS delay circuit (“delay circuit”) 200 includes an input node 202, a low-delay path including buffer 204 and resistive switches 208, a high delay path including buffers 206 and resistive switch 210, an output buffer 214, and an output node 216. Each resistive switch 208 and 210 includes control lines 218 and 220, When control line 218 is a high signal and control line 220 is a low signal, the switch closes (i.e. current passes through the switch). In some examples, the signal on control line 220 is an inverted signal from control line 218.
[0030] In the example of FIG. 2, buffers 204, 206, and 214 each include a pair of inverters. When a signal is received as the input of a buffer 204, 206, or 214, the signal is inverted by the first inverter and then reinverted to the original signal by the second inverter. Each buffer 204, 206, or 214 induces a propagation delay on the received signal, a time that it takes to invert the signal and reinvert it. In the low-delay path, buffer 204 receives the input signal from input node 202. The input signal received at input node 202 may have deteriorated when input to buffer 204. Buffer 204 may reduce the susceptibility to certain deterioration of the signal, such as noise added to the signal by components of delay circuit 200. In some examples, deterioration of the signal occurs between the signal source and input node 202. Buffer 204 may also amplify the signal or increase the current of the signal as it flows through the low-delay path. Buffer 204 also induces a propagation delay on the signal. There is a small period of time when the signal has arrived at the input of buffer 204 and has not yet been inverted and reinverted and transmitted on the output of buffer 204. This propagation delay, along with propagation delays of the rest of the low-delay path and buffer 214 are the minimum configurable delay of delay circuit 200.
[0031] In the high-delay path, buffers 206a-c are electrically coupled in series with one another. Due to buffers 206a-c being coupled in series, their propagation delays sum together. For example, if each buffer 206 has a propagation delay of 1 us, the total propagation delay across buffers 206a-c (i.e. the time from when the signal is received at the input of buffer 206a to the time when the signal is transmitted from the output of buffer 206c) is 3 us. This propagation delay, along with propagation delays of the rest of the high-delay path and buffer 214 are the maximum configurable delay of delay circuit 200.
[0032] In the example of FIG. 2, resistive switches 208 and 210 are CMOS switches. Resistive switches 208a-j can be configured to adjust the effective resistance of the low-delay path. Resistive switch 210 is configured either to allow current to pass through the high-delay path while providing a fixed effective resistance or to prevent current from passing through the high-delay path when delay circuit 200 is configured for minimum delay. The ratio of effective resistances between the high-delay path and the low-delay path is determined based on the pattern of resistive switches 208a-j that are closed. For example, if resistive switches 208a, 208c, 208f, and 208i are closed to provide an effective resistance of 40, and resistive switch 210 provides an effective resistance of 10, the ratio of low-delay path effective resistance to high-delay path effective resistance is 4:1. In some examples, the larger the ratio of low-delay path effective resistance to high-delay path effective resistance, the more delay is imparted on the signal received at input node 202.
[0033] The example of FIG. 2 illustrates a delay circuit 200 comprising CMOS circuitry, which can be incorporated into an integrated circuit (IC) as a portion of the IC logic. In some examples, a controller (which may be located on the same IC as delay circuit 200) provides control signals to resistive switches 208 and 210 through control lines 218 and 220.
[0034] The following is an example operation of delay circuit 200. A controller configures resistive switches 208 and 210 to induce a delay of 5 us on a signal received at input node 202. Buffers 204, 206, and 214 each induce a delay of 2 us (NOTE: actual delay through a CMOS buffer may be substantially less than 2 us, all example delays used in this disclosure are chosen for mathematical clarity, not for technical accuracy based on a specific transistor technology), and any other propagation delays throughout delay circuit 200 are negligible. The delay through the high-delay path due to buffers 206a-c is 6 us. The delay through the low-delay path due to buffer 204 is 2 us. The delay through output buffer 214 is 2 us. Resultantly, the minimum configurable delay of delay circuit 200 is 4 us and the maximum configurable delay of delay circuit 200 is Bus. Since the desired 5 us delay is nearer to the minimum configurable delay than the maximum configurable delay, delay circuit 200 is configured to have a relatively low effective resistance on the low-delay path and a relatively high effective resistance on the high-delay path. For example, if resistive switch 210 has an effective resistance of 100, resistive switches 208 may have an effective resistance of 20 to achieve a 1:5 ratio of low-delay effective resistance to high-delay effective resistance. In certain example delay circuits 200, a 1:5 ratio of low-delay effective resistance to high-delay effective resistance results in a 5 us delayed sign[0035] FIG. 3 illustrates an example signal delay system. Delay system 300 includes delay circuit 302 and controller 310. Delay circuit 302 includes a low-delay path 304, a high-delay path 306, and an output buffer 308. Controller 310 couples to delay circuit 302 via input signal line 312, high-delay path control lines 314, low-delay path control line 316, and output signal line 318.
[0036] Although the example system of FIG. 3 illustrate controller 310 providing the input signal to delay circuit 302 on input signal line 312 and receiving the output signal from delay circuit 302 on output signal line 318, the input signal may originate from a different source, and the output signal may be transmitted to a different source.
[0037] Based on the specific application of delay system 300, controller 310 uses stored information about arrays of resistive switches included in low-delay path 304 and high-delay path 306, respectively. In some examples, controller 310 stores information about the resistive switches, including each resistive switch's resistance. In such examples, controller 310 determines what ratio of effective resistance of low-delay path 304 to high-delay path 306 is required for a given delay. In such examples, controller 310 calculates, based on the resistance of each resistive switch, which switches should be closed to achieve the proper ratio of effective resistances for the desired delay.
[0038] In some other examples, controller 310 stores information about configurations of resistive switches, including which switches to close to achieve a certain delay. Controller 310 then closes the appropriate resistive switches of high-delay path 306 and low-delay path 304 to achieve the certain delay.
[0039] Controller 310 transmits control signals to resistive switches in high-delay path 306 through high-delay path control lines 314 and to resistive switches in low-delay path 304 through low-delay path control lines 316. In some examples, control signals for certain resistive switches include a primary control signal (i.e. “high” means closed, “low” means open) and an inverted control signal (i.e. “low” means closed, “high” means open). In some other examples, control signals for certain resistive switches include a primary control signal.
Liu, Figures 1-5 and Selected Text
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Abstract: We explore using a switchable detector array to reduce the deadtime effect in an OAM encoded quantum system. For a 4-OAM-state system, the switchable 16-detector array could provide >15X incident photon rate improvement, as compared to a non-switchable 4-detector array.
A key challenge for quantum systems is the “deadtime” of the single photon detector, which is the time needed to recover for registering the next photon after a detector fires. Since a detector does not response to any newly-arriving photon during the deadtime, the incident photon rate of the overall system would be limited by the detector’s deadtime.
Previous reports have shown that a 2-state non-OAM-based system with a switchable 4-detector array might be able to operate at much more than 4 times the incident photon rate of the system with a single detector … Since the switchable detector array is able to route an incoming photon to a designed detector, the overall effect of detector deadtime could be reduced.
Regarding claims 2-7, as dependent upon claim 1, it would have been obvious to one of ordinary skill in the art to modify Wang, as evidenced by Gao, in view of Langstaff, further in view of Schiller, and further in view of Liu, as applied in the rejection of claim 1, to disclose:
2. The carrier-modulated waveguide structure as claimed in claim 1, wherein the first semiconductor layer and the second semiconductor layer are a p-type semiconductor layer and a n-type semiconductor layer respectively. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
3. The carrier-modulated waveguide structure as claimed in claim 1, wherein the light absorbing component is a germanium component. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
4. The carrier-modulated waveguide structure as claimed in claim 1, wherein a material for the transporting control element is selected from a p-type silicon material. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
5. The carrier-modulated waveguide structure as claimed in claim 1, wherein the first semiconductor layer and the second semiconductor layer are respectively provided with a first protrusion arranged opposite to the bias intrinsic layer and a second protrusion disposed opposite to the bias intrinsic layer; the first protrusion and the second protrusion are combined with the bias intrinsic layer to form a stacked platform and the light absorbing component is disposed over the stacked platform; a first semiconductor doped layer and a second semiconductor doped layer are respectively connected to an outer side of the first semiconductor layer and an outer side of the second semiconductor layer. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
6. The carrier-modulated waveguide structure as claimed in claim 1, wherein the light sensor includes: a first electrode; a first semiconductor bias layer disposed on one side of the first electrode and coupled to the first electrode; a sensing intrinsic layer arranged at one side of the first semiconductor bias layer and connected to the first semiconductor bias layer; a second semiconductor bias layer mounted to one side of the sensing intrinsic layer and connected to the sensing intrinsic layer; and a second electrode disposed on one side of the second semiconductor bias layer and coupled to the second semiconductor bias layer; wherein the sensing intrinsic layers of the light sensors are connected to the carrier channels. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
7. The carrier-modulated waveguide structure as claimed in claim 1, wherein the carrier-modulated waveguide structure further includes a gate bias component which is electrically connected to and located over the light absorbing component and providing a gate bias to the light absorbing component. Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
because the resulting configurations and related methods would facilitate designing, fabricating, and deploying single-photon quantum systems not hindered by single photon detector deadtimes. Langstaff, figure 1, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
Claims 8 and 9
Claims 8 and 9, as dependent upon claim 1, are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (High-performance waveguide coupled Germanium-on-silicon single-photon avalanche diode with independently controllable absorption and multiplication. Nanophotonics. 2023 Feb 14;12(4):705-714; “Wang”), as evidenced by Gao et al. (Si/Ge phototransistor with responsivity >1000A/W on a silicon photonics platform, Opt. Express 32, 2271-2280 (2024); “Gao”), in view of Langstaff et al. (A fully integrated multi-channel detector for electron spectroscopy, Nuclear Instruments and Methods in Physics Research B 238 (2005) 219–223; “Langstaff”), further in view of Schiller et al. (2019/0305764; “Schiller”), and further in view of Liu et al. (Reduced effect of single-photon-detector deadtime using a switchable detector array in an orbital-angular-momentum (OAM) encoded quantum system, 2017 Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, USA, 2017, pp. 1-2; “Liu”), as applied in the rejection of claims 1-7, further in view of Tomii et al. (6,339,236; “Tomii”) and further in view of Castelletto et al. (Achieving higher photon counting rates using multiplexed detectors, Quantum Communications and Quantum Imaging IV, edited by Ronald E. Meyers, Yanhua Shih, Keith S. Deacon, Proc. of SPIE Vol. 6305, 63050R, (2006); “Castelletto”).
Regarding claims 8 and 9, as dependent upon claim 1, Tomii discloses at column 1, line 56 – column 2, line 23, and related text and figures, embodiments of ‘improved light responsive semiconductor switch circuits comprising photovoltaic elements that generate an electric power upon absorption of light from a light source.... A shunt transistor is connected in series with a current limiting resistive element across the photovoltaic element to define a shunt path of flowing the current from the photovoltaic element through the current limiting resistive element away from the output switching transistor. Also included in the switch is a latch circuit which is connected to the overcurrent sensor and the shunt transistor. The latch circuit is energized by the photovoltaic element and provides an interruption signal once the overcurrent signal is received and holds the interruption signal after the removal of the overcurrent signal. The interruption signal causes the shunt transistor to become conductive to flow the current from the photovoltaic element through the shunt path, lowering the operating voltage being applied to the control electrode of the output switching transistor below the threshold voltage so as to turn off the output switching transistor for disconnection of the load from the power source.” See below Tomii, Selected Text, and related text and figures.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Wang, as evidenced by Gao, in view of Langstaff, further in view of Schiller, and further in view of Liu, as applied in the rejection of claims 1-7, to disclose:
8. The carrier-modulated waveguide structure as claimed in claim 1, wherein when a first light sensor of the light sensors receives a first incident photon absorbed by the light absorbing component from the transporting control element, the first light sensor drives a first carrier channel of the carrier channels and corresponding to the first light sensor to close and generates a light sensing signal within a first dead period. Tomii, Selected Text, and related text and figures; Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
9. The carrier-modulated waveguide structure as claimed in claim 1, wherein the light sensors provide a plurality of biases to the carrier channels correspondingly and the biases are corresponding to detection probabilities of the light sensors. Tomii, Selected Text, and related text and figures; Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
because the resulting configurations and related methods would facilitate designing, fabricating, and deploying fast multiplexed detection quantum information schemes; See below Castelletto, figure 1, and related figures and text, for example, Selected Text (“We present a multiplexed detection scheme that allows photon counting at higher rates than possible with single detectors. The system uses an array of detectors and an optical switch system to direct incoming photons to detectors known to be live. We model the system for realistic individual detector deadtimes and optical switching times.”); not hindered by single photon detector deadtimes. Langstaff, figure 1, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
Tomii, Selected Text
Tomii, column 1, line 56 – column 2, line 23 (“In view of the above insufficiency in the prior art, the present invention has been achieved to provide an improved light responsive semiconductor switch with shorted load protection which is capable of successfully interrupting a load overcurrent. The semiconductor switch in accordance with the present invention comprises an output switching transistor connected between a pair of output terminals which are adapted for connection to a load circuit composed of a load and a power source energizing the load. The output switching transistor has a control electrode with a threshold voltage at which the output switching transistor conducts to connect the load to the power source. A photovoltaic element is included in the switch to generate an electric power upon absorption of light from a light source. The electric power provides an operating voltage decreasing with an increasing current flowing from the photovoltaic element. An overcurrent sensor is coupled to the load circuit to provide an overcurrent signal when the load circuit sees an overcurrent flowing through the load from the power source. A shunt transistor is connected in series with a current limiting resistive element across the photovoltaic element to define a shunt path of flowing the current from the photovoltaic element through the current limiting resistive element away from the output switching transistor. Also included in the switch is a latch circuit which is connected to the overcurrent sensor and the shunt transistor. The latch circuit is energized by the photovoltaic element and provides an interruption signal once the overcurrent signal is received and holds the interruption signal after the removal of the overcurrent signal. The interruption signal causes the shunt transistor to become conductive to flow the current from the photovoltaic element through the shunt path, lowering the operating voltage being applied to the control electrode of the output switching transistor below the threshold voltage so as to turn off the output switching transistor for disconnection of the load from the power source.”).
Castelletto, Figure 1 and Selected Text
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ABSTRACT. As the quantum information field advances, the need for improved single-photon devices is becoming more critical. Quantum information systems are often limited by detector deadtime to count rates of a few MHz, at best. We present a multiplexed detection scheme that allows photon counting at higher rates than possible with single detectors. The system uses an array of detectors and an optical switch system to direct incoming photons to detectors known to be live. We model the system for realistic individual detector deadtimes and optical switching times. We show that such a system offers more promise than simply reducing the deadtime of an individual detector. We find that a system of N detectors with a given deadtime, can count photons at faster rates than a single detector with a deadtime reduced by 1/N, even if it were practical to make such a large improvement.
4. CONCLUSION. We have shown that a pool of N detectors with a controlled switch system can in principle be operated at much higher incident photon rates than is otherwise possible either with a single detector with much reduced deadtime, or an array of detectors with a passive switch system such as might be implemented with by a tree of beamsplitters. Our modeling included realistic optical switch transition times and showed that switch transitions times are negligible when they are less than 2% of the individual detector deadtimes which means that the scheme should be practical for the case of detectors like InGaAs APDs which often operate with microsecond deadtimes. However for the switching times of 20% or more of the single photon detector deadtime, a detector tree configuration would be more convenient and advantageous.
Claim 10
Claim 10, as dependent upon claim 1, is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (High-performance waveguide coupled Germanium-on-silicon single-photon avalanche diode with independently controllable absorption and multiplication. Nanophotonics. 2023 Feb 14;12(4):705-714; “Wang”), as evidenced by Gao et al. (Si/Ge phototransistor with responsivity >1000A/W on a silicon photonics platform, Opt. Express 32, 2271-2280 (2024); “Gao”), in view of Langstaff et al. (A fully integrated multi-channel detector for electron spectroscopy, Nuclear Instruments and Methods in Physics Research B 238 (2005) 219–223; “Langstaff”), further in view of Schiller et al. (2019/0305764; “Schiller”), and further in view of Liu et al. (Reduced effect of single-photon-detector deadtime using a switchable detector array in an orbital-angular-momentum (OAM) encoded quantum system, 2017 Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, USA, 2017, pp. 1-2; “Liu”), as applied in the rejection of claims 1-7, further in view of Tomii et al. (6,339,236; “Tomii”) and further in view of Castelletto et al. (Achieving higher photon counting rates using multiplexed detectors, Quantum Communications and Quantum Imaging IV, edited by Ronald E. Meyers, Yanhua Shih, Keith S. Deacon, Proc. of SPIE Vol. 6305, 63050R, (2006); “Castelletto”), as applied in the rejection of claims 8 and 9, and further in view of Dolinar et al. (Fundamentals of Free-Space Optical Communication, Keck Institute for Space Studies (KISS) Workshop on Quantum Communication, Sensing and Measurement in Space, Pasadena, CA – June 25, 2012; “Dolinar”).
Regarding claim 10, as dependent upon claim 1, Dolinar discloses in Selected Slides steps characterizing embodiments of quantum communication systems comprising intensity modulated channels and potentially deleterious dark noise, jitter, and dead-time blocking. See below Dolinar, Selected Slides.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Wang, as evidenced by Gao, in view of Langstaff, further in view of Schiller, and further in view of Liu, as applied in the rejection of claims 1-7, further in view of Tomii and further in view of Castelletto, as applied in the rejection of claims 8 and 9, to disclose that when at least one light sensor of the light sensors receives at least one incident photon absorbed by the light absorbing component from the transporting control element, the at least one light sensor drives at least one carrier channel of the carrier channels corresponding to the at least one light sensor to close and generates a quantum strength signal according to the at least one incident photon within a first dead period; the number of the at least one incident photon determines strength of the quantum strength signal; Dolinar, Selected Slides; Tomii, Selected Text, and related text and figures; Wang, figures 1 and 2, and related figures and text, for example, Selected Text; Gao, figure 1, and related figures and text, for example, Selected Text; Langstaff, figure 1, and related figures and text, for example, Selected Text; Schiller, figures 2 and 3, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text; because the resulting configurations and related methods would facilitate designing, fabricating, and deploying fast multiplexed detection quantum information schemes; Castelletto, figure 1, and related figures and text, for example, Selected Text; not hindered by single photon detector deadtimes, for example, as deleteriously induced by jitter and blocking. Dolinar, Selected Slides. Langstaff, figure 1, and related figures and text, for example, Selected Text; Liu, figures 1-5, and related figures and text, for example, Selected Text.
Dolinar, Selected Slides
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Conclusion
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874
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