DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2, 11-14, 16-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez et al. (US 2004/0008086 A1) in view of Sugiura (US 2018/0287576 A1).
Regarding claim 1: Sanchez, fig.5E, discloses an amplifier circuit (operational amplifier 100E; paragraph [0044] line 1) , comprising: a first transistor (2; paragraph [0015], line 5) having a control terminal (Vin +) and first (source) and second (drain) controlled terminals, and a second transistor (3; paragraph [0015] line 5) having a control terminal (Vin-) and first (source) and second (drain) controlled terminals, where the first controlled terminal (source) of the first transistor (2) and the first controlled terminal (source) of the second transistor (3) are connected to one another and to a first reference potential (V+; via current source 14), and the second controlled terminal (drain) of the first transistor (2) and the second controlled terminal (drain) of the second transistor (3) are connected to a second reference potential
(V-; go through conductor 6 and conductor 7, respectively, to load transistors 9 and 8 respectively, which are coupled to V-; paragraph [0005] lines 3-6), wherein the first transistor (2) and the second transistor (3) are of a first conductivity type (P- channel/PMOS; paragraph [0038] lines 4-5); a first circuit (branching including cascode transistor 11 and load transistor 9) having an input side (source of transistor 11; conductor 6) connected to the second controlled terminal (drain) of the first transistor (2), the first circuit (branching including cascode transistor 11 and load transistor 9) having an output side (drain of transistor 11/output conductor 15; paragraph [0038], line 22) configured to provide a first output current (output current at conductor 15); and a second circuit (branching including cascode transistor 10 and load transistor 8) having an input side (source of transistor 10; conductor 7) connected to the second controlled terminal (drain) of the second transistor (3), the second circuit (branching including cascode transistor 10 and load transistor 8) having an output side (drain of transistor 10/current source 13 node) configured to provide a second output current (output at drain of cascode transistor 10; output node coupled to current source circuit 13; paragraph [0039], lines 31-33, [0042], lines 3-5).
However, Sanchez does not disclose a first circuit having an input side connected to the second controlled terminal of the first transistor, the first circuit controlled by a first voltage which depends on a first input voltage which is applied to the control terminal of the first transistor, the first circuit having an output side configured to provide a first output current; and a second circuit having an input side connected to the second controlled terminal of the second transistor, the second circuit controlled by a second voltage which depends on a second input voltage which is applied to a control terminal of the second transistor, the second circuit having an output side configured to provide a second output current; wherein the first circuit and/or the second circuit has a transistor having a control terminal to which the first voltage or the second voltage is applied, wherein the transistor of the first circuit and/or the second circuit has a second conductivity type that is different from the first conductivity type.
Sugiura, Fig. 1, does disclose the first circuit (level-shift 111) controlled by a first voltage (voltage V(191) at output terminal 191) which is applied to the control terminal (gate of transistor 121), (paragraph [0018]) of the first transistor (121), which depends on a first input voltage (the first voltage V(191) being generated from the first input voltage at input terminal 181/INP by Gm amplifier 102; paragraphs [0017]-[0018]), which is applied to the control terminal of the first transistor (gate of input transistor 141) and the second circuit (level-shift circuit 112) controlled by a second voltage (voltage V(192)) at output terminal 192, applied to the gate of transistor 122; paragraph [0019]) which depends on a second input voltage (input voltage at input terminal 182/INN, processed by Gm amplifier 102 to produce the voltage at output terminal 192; paragraphs [0017] and [0019]) which is applied to a control terminal of the second transistor (gate of input transistor 142), wherein the first circuit and/or the second circuit has a transistor (transistor 121 of level-shift circuit 111 and/or transistor 122 of level -shift circuit 112) ) having a control terminal (gate) to which the first voltage or the second voltage is applied (V(191) or V(192)), respectively, wherein the transistor of the first circuit and/or the second circuit has a second conductivity type that is different from the first conductivity type (transistors 121 and 122 are shown in Fig. 1 with their drains coupled toward VDD1 and their sources coupled through current sources 131 and 132 toward VSS1, a configuration that one of ordinary skill in the art would recognize as NMOS, opposite the P-channel conductivity type disclosed for Sanchez transistors 2 and 3).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sanchez by employing the level-shift circuits of Sugiura because Sugiura teaches that the level-shift configuration allows common-mode feedback while preventing gain reduction, suppressing increases in input offset voltage, and maintaining operating speed by avoiding charge/discharge of the gate-source capacitances of the level-shift transistors (Sugiura [0025]-[0026]). Such substitution applies a known amplifier configuration to obtain the predictable advantages taught by Sugiura.
Regarding claim 2: Sanchez, fig. 5E, discloses a first current source (14) configured to provide current to the first controlled terminal of the first transistor (2) and/or the first controlled terminal of the second transistor.
Regarding claim 11: Sanchez, fig. 5E discloses a circuit which provides a total output current which is dependent on the first output current and the second output current (current sources 13, the folded-cascode path through transistor 11, and current source 14 coupled to the output node feeding the output stage (VOUT), paragraph [0039], lines 31-33).
Regarding claim 12: Sanchez, fig.5E, discloses an amplifier circuit (operational amplifier 100E; paragraph [0044] line 1) , comprising: a first transistor (2; paragraph [0015] line 5) having a control terminal (Vin +) and first (source) and second (drain) controlled terminals, and a second transistor (3; paragraph [0015] line 5) having a control terminal (Vin-) and first (source) and second (drain) controlled terminals, where the first controlled terminal (source) of the first transistor (2) and the first controlled terminal (source) of the second transistor (3) are connected to one another and to a first reference potential (V+; via current source 14), and the second controlled terminal (drain) of the first transistor (2) and the second controlled terminal (drain) of the second transistor (3) are connected to a second reference potential
(V-; go through conductor 6 and conductor 7, respectively, to load transistors 9 and 8 respectively, which are coupled to V-; paragraph [0005] lines 3-6), wherein the first transistor (2) and the second transistor (3) are of a first conductivity type (P- channel/PMOS; paragraph [0038] lines 4-5); a third transistor (11) having a control terminal and first and second controlled terminals, the first controlled terminal (source) of the third transistor (11) is connected to the second controlled terminal (drain) of the first transistor (2); the control terminal of the third transistor (11) is set up to receive the second controlled terminal (drain) of the third transistor (11) is configured to provide a first output current (conductor 15); and a fourth transistor (10) having a control terminal and first and second controlled terminals, the first controlled terminal (source) of the fourth transistor (10) is connected to the second controlled terminal (drain) of the second transistor (3); the control terminal of the fourth transistor (10) is set up to receive and the second controlled terminal (drain) of the fourth transistor (10) is configured to provide a second output current (drain current of cascode transistor 10) (paragraph [0039], lines 43-45); and wherein the third transistor (11) and the fourth transistor (10) are of a second conductivity type which is different from the first conductivity type (N-channel, paragraph [0038], lines 19-25).
Sanchez does not disclose the control terminal of the third transistor is set up to receive a voltage which depends on a first input voltage which is applied to the control terminal of the first transistor; the control terminal of the fourth transistor is set up to receive a voltage which depends on
a second input voltage which is applied to the control terminal of the second transistor.
Sugiura, Fig. 1, does disclose a voltage which depends on a first input voltage (V(191), generated based on input voltage INP at input terminal 181), which is applied to the control terminal of the first transistor (2), and a voltage which depends on a second input voltage (V(192), generated based on input voltage INN at input terminal 182), which is applied to the control terminal of the second transistor (3) (paragraphs [0017], lines 12-18; [0018]).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sanchez by employing Sugiura’s level-shift configuration because Sugiura teaches that the level-shift configuration allows the gate-source capacitances of the level-shift transistors to not hinder operation speed, thereby suppressing a reduction in operation speed (Sugiura: paragraph [0026], lines 2-9).
Regarding claims 13 and 14: Sanchez does not disclose a first voltage source connected to the control terminal of the third transistor and set up to provide the voltage to the control terminal of the third transistor, the voltage depending on the first input voltage applied to the control terminal of the first transistor. Sanchez also does not disclose a second voltage source connected to the control terminal of the fourth transistor and set up to provide the voltage to the control terminal of the fourth transistor, the voltage depending on the second input voltage applied to the control terminal of the second transistor.
Sugiura, fig. 1, does disclose a first voltage source (Gm amplifier 102/output terminal 191) connected to the control terminal (gate) of the third transistor (corresponding to the gate of transistor 121; applied in the combination to the gate of Sanchez’s transistor 11) and set up to provide the voltage to the control terminal of the third transistor (11), the voltage (V(191)) depending on the first input voltage (INP at input terminal 181) applied to the control terminal (gate) of the first transistor (Sanchez’s first transistor (2)). Furthermore, Sugiura also discloses a second voltage source (Gm amplifier 102/output terminal 192) connected to the control terminal (gate) of the fourth transistor (122) and set up to provide the voltage to the control terminal of the fourth transistor (corresponding to the gate of transistor 122; applied in the combination to the gate of Sanchez’s transistor 10), the voltage (V(192)) depending on the second input voltage (INN at input terminal 182) applied to the control terminal (gate) of the second transistor (Sanchez’s second transistor 3), (paragraphs [0017], lines 12-18; [0018]- [0019]).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sanchez by employing Sugiura’s level-shift configuration to provide the respective voltages to the control terminals of Sanchez’s cascode transistors 11 and 10, because Sugiura teaches that the level-shift configuration prevents the gate-source capacitances of the level-shift transistors from hindering operation speed, thereby suppressing a reduction in operation speed (Sugiura: paragraph [0026]).
Regarding claim 16: Sanchez, fig. 5E discloses a second current source (N-channel load transistor 9) which is connected between the second controlled terminal (drain) of the first transistor (2) and the second reference potential (V-) (paragraph [0038], lines 15-16).
Regarding claim 17: Sanchez, fig. 5E, discloses a pair of input differential transistors (P-channel input transistors 2 and 3, with Vin+ and Vin- applied to their gates); and at least one pair of folded-cascode transistors having a conductivity type that differs from a conductivity type of the input differential transistors (N-channel cascode transistors 10 and 11); wherein each controlled terminal of a transistor of the pair of input differential transistors is connected to a controlled terminal of an associated transistor of the pair of folded-cascode transistors [0038], lines 15-25); and wherein each control terminal of a transistor of the pair of folded-cascode transistors is set up to receive a voltage which depends on a respective input voltage which is applied to a control terminal of an associated transistor of the pair of input differential transistors.
However, Sanchez does not disclose wherein each control terminal of a transistor of the pair of folded-cascode transistors is set up to receive a voltage which depends on a respective input voltage which is applied to a control terminal of an associated transistor of the pair of input differential transistors.
Sugiura, fig. 1, does disclose that each control terminal of a transistor of the pair of folded-cascode transistors (gates of transistors 121 and 122; corresponding in the combination to the gates of Sanchez’s transistors 11 and 10) is set up to receive a voltage (V(191) and V(192)) which depends on a respective input voltage (INP at input terminal 181 and INN at input terminal 182) which is applied to a control terminal (gate) of an associated transistor of the pair of input differential transistors (paragraphs [0017], lines 12-18; [0018]- [0019]).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sanchez by employing Sugiura’s level-shift configuration to provide respective input-voltage dependent voltages to the control terminals of Sanchez’s folded-cascode transistors 11 and 10, because Sugiura teaches that the level-shift configuration prevents the gate-source capacitances of the level-shift transistors from hindering operation speed, thereby suppressing a reduction in operation speed (Sugiura: paragraph [0026]).
Regarding claim 18: Sanchez, discloses a first current source (tail current source 4) configured to provide current to a first controlled terminal (source) of each transistor in the pair of input differential transistors (P-channel input transistors 2 and 3) (paragraph [0004], lines 3-4).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sanchez et al. (US 2004/0008086 A1) in view of Sugiura (US 2018/0287576 A1) as applied to claim 1 above, and further in view of Sakurai (US 6114907).
Regarding claim 3: Sanchez as modified by Sugiura does not disclose the first current source has a first current source transistor which is connected between the first controlled terminal of the first transistor and the first reference potential, and a control input of the current source transistor is set up to receive a first bias voltage.
Sakurai, Fig. 1; column 1, line 64, column 2, line 32, column 3, lines 10-22) does disclose the first current source (14) has a first current source transistor (bias-controlled transistor used to implement the current source (20A)) which is connected between the first controlled terminal of the first transistor (2) and the first reference potential (V+), and a control input (gate of bias-controlled transistor (20A)) of the current source transistor (bias-controlled transistor used to implement the current source (20A)) is set up to receive a first bias voltage (VBP1).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the Sanchez and Sugiura combination by implementing current source 14 using a bias-controlled current source transistor to maintain the bias-controlled current source transistor in saturation, thereby providing the desired operating condition of the current source transistor (Sakurai, column 1, lines 58-64).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sanchez et al. (US 2004/0008086 A1) in view of Hwang (US 11855596 B2).
Regarding claim 20: Sanchez, fig.5E, discloses an amplifier circuit (operational amplifier 100E; paragraph [0044] line 1) , comprising: a first transistor (2; paragraph [0015] line 5) having a control terminal (Vin +) and first (source) and second (drain) controlled terminals, and a second transistor (3; paragraph [0015] line 5) having a control terminal (Vin-) and first (source) and second (drain) controlled terminals, where the first controlled terminal (source) of the first transistor (2) and the first controlled terminal (source) of the second transistor (3) are connected to one another and to a first reference potential
(V+; via current source 14 ), a first circuit (branching including cascode transistor 11 and load transistor 9) having an input side (source of transistor 11; conductor 6) connected to the second controlled terminal (drain) of the first transistor (2), the first circuit (branching including cascode transistor 11 and load transistor 9) having an output side (drain of transistor 11/output conductor 15; paragraph [0038], line 22) configured to provide a first output current (output current at conductor 15); and a second circuit (branching including cascode transistor 10 and load transistor 8) having an input side (source of transistor 10; conductor 7) connected to the second controlled terminal (drain) of the second transistor (3), the second circuit (branching including cascode transistor 10 and load transistor 8) having an output side (drain of transistor 10/current source 13 node) configured to provide a second output current (output at drain of cascode transistor 10; output node coupled to current source circuit 13; paragraph [0039], lines 31-33, [0042], lines 3-5).
However, Sanchez does not teach the first circuit controlled by a first voltage which depends on a first input voltage which is applied to the control terminal of the first transistor, the second circuit controlled by a second voltage which depends on a second input voltage which is applied to a control terminal of the second transistor; wherein the first voltage is independent of the second voltage.
Hwang, fig. 4, teaches the first circuit controlled by a first voltage which depends on a first input voltage which is applied to the control terminal of the first transistor (first voltage: voltage at boosting node BN applied to the gate/control terminal of TC1.
Hwang teaches gain booster 131 changes BN based on first input signal IN1 and the voltage level of ON1), (column 5, lines 57-67; column 12. Line 63-67), the second circuit controlled by a second voltage which depends on a second input voltage which is applied to a control terminal of the second transistor (second voltage: voltage level of second output node ON2; second input voltage: second input signal IN2 applied to the gate/control terminal of second input transistor T12; Hwang teaches second input unit 120 changes the voltage level of ON2 based on IN2), (column 4, lines 9-14; column 6, lines 1-9), the first voltage is independent of the second voltage, (column 5, lines 57-67; column 6, lines 1-11; column 12. Line 63-67).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the Sanchez to provide respective input-responsive control of the amplifier branches, thereby providing output-signal gain boosting responsive to changes in an input signal, as taught by Hwang (column 3, lines 28-31).
Allowable Subject Matter
Claims 4, 5, 6, 7, 8, 9, 10, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4: none of the references teach a first protective circuit configured such that the voltage difference between the control terminal of the first current source transistor and the second controlled terminal of the first transistor is smaller than a predetermined maximum voltage.
Regarding claims 7, 8: depend therefrom claim 4 and include the same allowable features.
Regarding claim 5: none of the references teach a first bypass connected in parallel with the first transistor and including a first bypass transistor configured to receive a second bias voltage.
Regarding claim 6: none of the references teach a second bypass path connected in parallel with the second transistor and having a third bypass transistor configured to receive a third bias voltage.
Regarding claim 9: none of the references teach the first and/or second transistor configured as a laterally-diffused metal-oxide semiconductor transistor.
Regarding claim 10: none of the references teach an input-voltage-to-reference-potential difference being greater than an applicable operating voltage of the respective first and/or second transistor.
Regarding claim 15: none of the references teach the joint voltage source providing the same voltage to the control terminals of the third and fourth transistors, wherein the voltage depends on both the first and second input voltages.
Regarding claim 19: none of the references teach the first protective circuit configured such that the voltage difference between a control terminal of the first current source and the respective second controlled terminals of the pair of input differential transistors is smaller than a predetermined maximum voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art of record, including:
Yu (CN 120512107 A) discloses a high-voltage operational amplifier including differential input circuitry, current-source/current-mirror circuitry, gain and output stages, and high-voltage protection circuitry configured to protect MOS transistors from excessive voltage conditions.
Willard et al. (US 9882531 B1) discloses a stacked-transistor amplifier architecture for high-voltage/high-power operation and discloses that the transistor stack may be implemented using LDMOS technology.
Grad et al. (US 10892258 B2) discloses a protective circuit for limiting a voltage associated with a transistor to protect it from excessive voltage during an electrostatic discharge.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to /NATASHA Y MARANO/ whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/NATASHA Y MARANO/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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