DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 09/03/2026 has been acknowledged. Claims 1, 4, 11, 13 and 17 have been amended. Claim 5 has been canceled. Claim 22 has been added. No new matter has been added.
This office action considers claims 1-4, 6-19, and 21-22 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 09/03/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. Therefore, the rejection of claims 1-19, and 21 have been withdrawn.
Applicant's arguments with respect to claims 1-4, 6-19, and 21 have been fully considered but are moot in view of the new grounds of rejection.
In response to applicant’s arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The prior art of Buyuktosunoglu et al. (US 20140281378 A1 – hereinafter Buyuktosunoglu) teaches all limitations of claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 3-4, 6-7, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230378135 A1 – hereinafter Lee) in view of Haba (US 20230207437 A1) and Knickerbocker (US 20110042820 A1).
Regarding independent claim 1, Lee teaches:
(Currently Amended) An apparatus (85 – Fig. 24 – [0109] – “stacked
integrated circuit 85” – this is an apparatus), comprising a plurality of core chips ([0002] – “stacked integrated circuit is recently formed by stacking a plurality of chips” – hereinafter ‘Chps’) including a plurality of spiral ([0117] – “In the second area 91_2, through vias 921_1 to 921_4 and front pads 923_1 to 923_4 may be connected, respectively, by using a spiral chain connection method” – Fig. 24 shows this, hereinafter ‘SPR’) through-substrate vias (TSVs) ([0117] – “through vias 921_1 to 921_4 and front pads 923_1 to 923_4” – hereinafter ‘TSV’), wherein
the plurality of core chips are stacked with one another in a face-to-face manner to define a common channel in first (85_1 – Fig. 24 – [0109] – “first chip 85_1”) and second core chips (85_2 – Fig. 24 – [0109] – “second chip 85_2”), which face each other (Fig. 9(c) – [0090] – “As illustrated in (c), a front face to front face bonding structure may be formed by the method of stacking the front side of a wafer on the front side of a wafer so that the front side of the wafer and the front side of the wafer face each other” – hereinafter ‘F2F’), of the plurality of core chips ([0002] – “stacked integrated circuit is recently formed by stacking a plurality of chips” – hereinafter ‘Chps’),
the first core chip (85_1) and the second core chip (85_2) include a first function circuit (731 – [0078] – “first chip output control module 731”) and a second function circuit (735 – [0079] – “second chip output control module 735”) coupled to the first function circuit (731), respectively, and
the first function circuit (731 – [0078] – “first chip output control module 731”) and the second function circuit (735 – [0079] – “second chip output control module 735”) provide the same functions ([0079] – “The second front IDs FID2<1:3> may be set as the same logic bit set as the first front IDs FID1<1:3>” – this describes providing the same logic function) for the common channel in response to a command signal provided by the spiral (SPR) TSVs ([0002] – “The plurality of chips included in the stacked integrated circuit may transmit data to one another in addition to control signals including commands and addresses through respective through vias”).
Lee does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Haba teaches
the plurality of core chips ([0005] – “a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed over the first stacked assembly and including a second plurality of integrated device dies” – hereinafter ‘DIE’) are stacked with one another in a face-to-face manner (TSV – [0009] – “the first and second pluralities of dies are face-to-face) to define a common channel ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – hereinafter ‘COM’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the common channel structure as taught by Haba into Lee.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results [0026] – “Providing electrical communication among a plurality of stacked device dies can be challenging. In particular, it is challenging to convey signals through a thickness of device dies while maintaining very fine pitches. Direct hybrid bonding, as compared with solder bonding, enables very fine pitch electrical connections between vertically adjacent dies, while also significantly reducing the thickness of the die stack, as compared to using thick solder balls between the dies. In conventional memory die stacks, the system comprises a single channel configured to provide read/write signals through the entire die stack. More specifically, in high bandwidth memory (HBM) technologies, one channel exists in a die stack, and every signal is transferred to every die in the die stack. In hybrid memory cube (HMC) technologies, a die stack comprises a plurality of channels, and every signal is transferred to every die in the die stack. Various embodiments disclosed herein connect subsets of dies in the die stack to form a bandwidth channel. For example, a first channel may convey signal to a plurality of dies in a first stacked assembly and a second channel may convey signal to a plurality of dies in a second stacked assembly disposed over the first stacked assembly, such that the second channel bypasses the active circuitry of the plurality of dies in the first stacked assembly. Such a technique could be used for any suitable types of integrated device dies, including memory dies (e.g., dynamic random access memory (DRAM), flash memory with logical NAND-type structure (NAND)) and would beneficially allow for the implementation of multiple channels, wherein each channel may provide a unique signal. For example, interconnects can be disposed through dicing lanes in the plurality of dies such that a high-speed signal can be disposed on a front leading edge of a die stack while other signal inputs/outputs can be disposed on other edges of the die stack. In various embodiments, some dies can have signal pass through vias. In various embodiments, thermocompression or direct hybrid bonding electrically connects vertically adjacent dies. In various embodiments, power and ground can be shared by all channels in the stacked device and in various embodiments, interconnects can be disposed through dummy silicon blocks under the same conditions as would be used with dicing lanes. In various embodiments, a redistribution layer (RDL) may be disposed over a die surface for configurations where interleaved dies are stacked with active front sides facing each other.”
Lee and Haba do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Knickerbocker teaches
coupled ([0068] – “one can have a memory circuit spread across multiple silicon layers, or a clock function circuit spread across multiple silicon layers. For a system function, one can have silicon processor layers and memory and field programmable gate array layers each on different silicon layers that are interconnected” – this describes coupled circuits).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the coupled structure as taught by Knickerbocker into Lee and Haba.
An ordinary artisan would have been motivated to use the known technique of Knickerbocker in the manner set forth above to produce the predictable results to [0005] – “to provide sufficient power and interconnection is to provide a low latency, low inductance path of connection from one chip to another by use of a die stack, where one or more die have through silicon vias (TSV) of thinned silicon die in the die stack, along with silicon-silicon interconnections (SSI), or with one or more die and die stacks on a silicon package again with high interconnection across SSI connections and a silicon package between die and die or die and die stacks or between die stacks, which together can provide electrical links to interconnect die from one level to another within a die stack.”
Regarding claim 3, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 3 depends. Lee further teaches
(Original) The apparatus according to claim 1, wherein the first (731)
and second (735) function circuits provide analog circuits.
Lee and Knickerbocker do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Haba teaches
analog circuits ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the analog circuit structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 4, Lee, as modified by Haba and Knickerbocker, teaches claim 3 from which claim 4 depends. Lee and Knickerbocker do not expressly disclose the limitations of claim 4.
However, in an analogous art, Haba teaches
(Currently Amended) The apparatus according to claim 3, wherein the
analog circuits include power supply circuits ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit) and/or compensation capacitor circuits.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power supply circuit structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 6, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 6 depends. Lee and Knickerbocker do not expressly disclose the limitations of claim 6.
However, in an analogous art, Haba teaches
(Original) The apparatus according to claim 1, wherein each of the core
chips (1a-1h – Fig. 1 – [0027] – “a plurality of integrated device dies 1a-1h (e.g., memory dies, processor dies, etc.) can be stacked on top of one another”) includes one or more memory chips or memory dies ([0027] – “the stacked dies 1a-1h can comprise memory dies”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the core chip structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 7, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 7 depends. Lee and Knickerbocker do not expressly disclose the limitations of claim 7.
However, in an analogous art, Haba teaches
(Original) The apparatus according to claim 1, wherein the core chips are
on an interface chip (2 – Fig. 10 – [0036] – “The stacked dies can be mounted to a carrier 2, such as a logic die or interposer”) coupled to an interposer (20 – Fig. 10 – [0036] – “carrier 2 can be mounted to a substrate 20, such as an interposer or other device die”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the core chip structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 21, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 21 depends. Lee and Knickerbocker do not expressly disclose the limitations of claim 21.
However, in an analogous art, Haba teaches
(Previously Presented) The apparatus according to claim 1, wherein the
apparatus (29 – Fig. 10 – [0040] – “stacked electronic device 29” – this is an apparatus) further comprises a plurality of channels ([0005] – “first plurality of TSVs comprising a first channel, a second plurality of TSVs comprising a second channel” – this is a plurality of channels) including the common channel (COM).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the channel structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba, Knickerbocker, and Kim et al. (US 20160155724 A1 – hereinafter Kim).
Regarding claim 2, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 2 depends. Lee, Haba, and Knickerbocker do not expressly disclose the limitations of claim 2.
However, in an analogous art, Kim teaches
(Original) The apparatus according to claim 1, wherein each of the core
chips (100 and 200 – Fig. 3A – [0098] – “the first semiconductor chip 100 … the second semiconductor chip 200”) includes a semiconductor substrate (111 and 211 – Fig. 2A – [0115] – “the first semiconductor substrate 111 faces the front surface 211a of the second semiconductor substrate 211”) and a plurality of wiring layers (113 and 213 – Fig. 2A – [0090] – “the first circuit layer 113 faces the second circuit layer 213”), and uppermost wiring layers (113 and 213) of the first (100) and second (200) core chips face each other ([0090] – “the first circuit layer 113 faces the second circuit layer 213” – Fig. 2A shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chip structure as taught by Kim into Lee, Haba, and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results of [0003] – “packaging techniques have been devised to meet the demand for high capacity, small thickness and reduced size of semiconductor device and electronic products. One approach is to vertically stack a plurality of semiconductor chips so as to accomplish a chip stack with high density. This technique has merits capable of integrating various kinds semiconductor chips in a smaller area compared to conventional packages with one semiconductor chip.”
Regarding claim 8, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 8 depends. Lee, Haba, and Knickerbocker do not expressly disclose the limitations of claim 8.
However, in an analogous art, Kim teaches
(Original) The apparatus according to claim 1, further includes a plurality of
bumps (219 – Fig. 3A – [0119] – “single blocks 911 may be spaced apart from each other and terminals 219 may be interposed to electrically connect the single blocks 911 each other”) in alignment with the corresponding TSVs (115 – Fig. 3A – [0112] – “via insulating layer 101 may surround the first through-electrode 115”) and connecting the first (100 – Fig. 3A – [0084] – “first semiconductor chip 100 may be a wafer-level chip”) and second core chips (200 – Fig. 3A – [0087] – “the second semiconductor chip 200 may be a wafer-level chip”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chip structure as taught by Kim into Lee, Haba, and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 2.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba, Knickerbocker, and Huang et al. (US 20170250172 A1 – hereinafter Huang).
Regarding claim 9, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 9 depends. Lee further teaches
spiral TSVs (SPR).
Lee, Haba, and Knickerbocker do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Huang teaches
(Original) The apparatus according to claim 1, wherein the first function
circuit ([0041] – “Protection circuits 150 on each semiconductor die 124a-124c” – hereinafter ‘150-1’ that is first function circuit on the first die) and the second function circuit ([0041] – “Protection circuits 150 on each semiconductor die 124a-124c” – hereinafter ‘150-2’ that is first function circuit on the second die) are activated simultaneously responsive to a command signal ([0041] – “Each semiconductor die 124 senses the voltage transient condition simultaneously and activates”) provided by the spiral TSVs.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the function activation structure as taught by Huang into Lee, Haba, and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable results [0005] – “is to produce smaller semiconductor devices. Smaller devices typically consume less power, can be produced more efficiently, and have higher performance. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for increasing the density of devices on printed circuit boards and reducing the size of end products. A smaller die size may be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba, Knickerbocker, and Buyuktosunoglu et al. (US 20140281378 A1 – hereinafter Buyuktosunoglu).
Regarding claim 10, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 10 depends. Lee, Haba, and Knickerbocker do not expressly disclose the limitations of claim 10.
However, in an analogous art, Buyuktosunoglu teaches
(Original) The apparatus according to claim 1, wherein the first core chip
(70A – Fig. 8 – [0073] – “first processor 70A and a second processor 70B vertically stacked”) is in an active state, and the second core chip (70B – Fig. 8 – [0073] – “first processor 70A and a second processor 70B vertically stacked”) is in an inactive state ([0070] – “the first processor chip can be active and the second processor chip can be inactive”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chip state structure as taught by Buyuktosunoglu into Lee, Haba, and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Buyuktosunoglu in the manner set forth above to produce the predictable results of [0005] – “a computer processor system includes a plurality of multi-chip systems. Each multi-chip system includes a plurality of chips that are conjoined together, a local interconnection and input/output wiring layer. One or more multi-chip systems includes a plurality of processor chips that are conjoined together. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. The plurality of multi-chip systems are edge-mounted to the substrate in parallel to each other.”
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba, Knickerbocker, and Otremba (US 20130056877 A1).
Regarding claim 22, Lee, as modified by Haba and Knickerbocker, teaches claim 1 from which claim 22 depends. Lee further teaches
(New) The apparatus according to claim 1, wherein each of the first
function circuit (731) and the second function circuit (735) has half a function required to provide the same functions for the common channel.
Lee and Knickerbocker do not expressly disclose the other limitations of claim 22.
However, in an analogous art, Haba teaches
common channel (COM).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the common channel structure as taught by Haba into Lee and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Lee, Knickerbocker, and Haba do not expressly disclose the other limitations of claim 22.
However, in an analogous art, Otremba teaches
half a function ([0025] – “multi-chip module may be used to house at least part of a circuit, e.g. at least part of a lamp ballast circuit 202, the at least part of the circuit 202 including first chip 204 and second chip 224 electrically connected to each other” – this describes a half a function where the ballast or power is the function and resides half on each chip) required to provide the same functions.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the function structure as taught by Otremba into Lee, Haba, and Knickerbocker.
An ordinary artisan would have been motivated to use the known technique of Otremba in the manner set forth above to produce the predictable results of [0002] – “high-voltage power semiconductors have been arranged in discrete housing modules, e.g. TO220-3, e.g. TO247-3, as shown in illustration 100 of FIG. 1, so as to ensure that high-voltage components are well insulated from each other.”
Claims 11-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba and Kim.
Regarding independent claim 11, Lee teaches:
(Currently Amended) An apparatus (85 – Fig. 24 – [0109] – “stacked
integrated circuit 85” – this is an apparatus), comprising a plurality of core chips ([0002] – “stacked integrated circuit is recently formed by stacking a plurality of chips” – hereinafter ‘Chps’) stacked with one another (Fig. 19(c) – [0090] – “As illustrated in (c), a front face to front face bonding structure may be formed by the method of stacking the front side of a wafer on the front side of a wafer so that the front side of the wafer and the front side of the wafer face each other” – hereinafter ‘F2F’) to provide shared functions ([0079] – “The second front IDs FID2<1:3> may be set as the same logic bit set as the first front IDs FID1<1:3>” – this describes providing a shared logic function) between first (85_1 – Fig. 24 – [0109] – “first chip 85_1”) and second core chips (85_2 – Fig. 24 – [0109] – “second chip 85_2”), each of the core chips including:
a plurality of wiring layers on a semiconductor substrate, uppermost wiring layers of the first and second core chips face each other;
a plurality of channels, the channels of the first and second core chips corresponding with each other to define a common channel; and
a plurality of spiral ([0117] – “In the second area 91_2, through vias 921_1 to 921_4 and front pads 923_1 to 923_4 may be connected, respectively, by using a spiral chain connection method” – Fig. 24 shows this, hereinafter ‘SPR’) through-substrate vias (TSVs) ([0117] – “through vias 921_1 to 921_4 and front pads 923_1 to 923_4” – hereinafter ‘TSV’) configured to provide command signals ([0002] – “The plurality of chips included in the stacked integrated circuit may transmit data to one another in addition to control signals including commands and addresses through respective through vias”) to the channels of the first (85_1) and second (85_1) core chips in a spiral manner (Fig. 24 shows this), wherein
a first function circuit (731 – [0078] – “first chip output control module 731”) of the first core chip (85_1) and a second function circuit (735 – [0079] – “second chip output control module 735”) of the second core chip (85_2) provide the shared functions for the common channel in response to the command signals ([0002] – “The plurality of chips included in the stacked integrated circuit may transmit data to one another in addition to control signals including commands and addresses through respective through vias”) provided by the spiral (SPR) TSVs, the shared functions being the same with each other ([0079] – “The second front IDs FID2<1:3> may be set as the same logic bit set as the first front IDs FID1<1:3>” – this describes providing the same logic function).
Lee does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Haba teaches
a plurality of channels ([0005] – “first plurality of TSVs comprising a first channel, a second plurality of TSVs comprising a second channel”), the channels of the first ([6a – Fig. 10 – [0030] – “dies 6a-6d, 7a-7d within each stack 6, 7”) and second core chips ([6b – Fig. 10 – [0030] – “dies 6a-6d, 7a-7d within each stack 6, 7”) corresponding with each other to define a common channel ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – hereinafter ‘COM’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the common channel structure as taught by Haba into Lee.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Lee and Haba do not expressly disclose the limitations of claim 11.
However, in an analogous art, Kim teaches
each of the core chips (100 and 200 – Fig. 3A – [0098] – “the first semiconductor chip 100 … the second semiconductor chip 200”) including:
a plurality of wiring layers (113 and 213 – Fig. 2A – [0090] – “the first circuit layer 113 faces the second circuit layer 213”) on a semiconductor substrate (111 and 211 – Fig. 2A – [0115] – “the first semiconductor substrate 111 faces the front surface 211a of the second semiconductor substrate 211”), uppermost wiring layers (113 and 213) of the first (100) and second (200) core chips face each other ([0090] – “the first circuit layer 113 faces the second circuit layer 213” – Fig. 2A shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chip structure as taught by Kim into Lee and Haba.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 12, Lee, as modified by Haba and Kim, teaches claim 11 from which claim 12 depends. Lee further teaches
(Original) The apparatus according to claim 11, wherein the first (731)
and second (735) function circuits provide analog circuits.
Lee and Kim do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Haba teaches
analog circuits ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the analog circuit structure as taught by Haba into Lee and Kim.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 13, Lee, as modified by Haba and Kim, teaches claim 12 from which claim 13 depends. Lee and Kim do not expressly disclose the limitations of claim 13.
However, in an analogous art, Haba teaches
(Currently Amended) The apparatus according to claim 12, wherein the
analog circuits provide power supply circuits ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit) and/or compensation capacitor circuits.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power supply circuit structure as taught by Haba into Lee and Kim.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 14, Lee, as modified by Haba and Kim, teaches claim 11 from which claim 14 depends. Lee further teaches
(Original) The apparatus according to claim 11, wherein the first (731)
and second (735) function circuits further provide logic circuits ([0079] – “The second front IDs FID2<1:3> may be set as the same logic bit set as the first front IDs FID1<1:3>” – this describes providing the same logic function).
Regarding claim 15, Lee, as modified by Haba and Kim, teaches claim 11 from which claim 15 depends. Lee and Kim do not expressly disclose the limitations of claim 15.
However, in an analogous art, Haba teaches
(Original) The apparatus according to claim 11, wherein each of the core
chips (1a-1h – Fig. 1 – [0027] – “a plurality of integrated device dies 1a-1h (e.g., memory dies, processor dies, etc.) can be stacked on top of one another”) includes one or more memory chips or memory dies ([0027] – “the stacked dies 1a-1h can comprise memory dies”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power supply circuit structure as taught by Haba into Lee and Kim.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 16, Lee, as modified by Haba and Kim, teaches claim 11 from which claim 16 depends. Lee and Haba do not expressly disclose the limitations of claim 16.
However, in an analogous art, Kim teaches
(Original) The apparatus according to claim 11, further comprising a
plurality of bumps (219 – Fig. 3A – [0119] – “single blocks 911 may be spaced apart from each other and terminals 219 may be interposed to electrically connect the single blocks 911 each other”) in alignment with the corresponding TSVs (115 – Fig. 3A – [0112] – “via insulating layer 101 may surround the first through-electrode 115”) and connecting the first (100 – Fig. 3A – [0084] – “first semiconductor chip 100 may be a wafer-level chip”) and second core chips (200 – Fig. 3A – [0087] – “the second semiconductor chip 200 may be a wafer-level chip”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chip structure as taught by Kim into Lee and Haba.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 19, Lee, as modified by Haba and Kim, teaches claim 17 from which claim 19 depends. Lee and Haba do not expressly disclose the limitations of claim 19.
However, in an analogous art, Kim teaches
(Original) The memory device according to claim 17, wherein
each of the memory dies (100 and 200 – Fig. 3A – [0098] – “the first
semiconductor chip 100 … the second semiconductor chip 200”) include a plurality of wiring layers (113 and 213 – Fig. 2A – [0090] – “the first circuit layer 113 faces the second circuit layer 213”) on a semiconductor substrate (111 and 211 – Fig. 2A – [0115] – “the first semiconductor substrate 111 faces the front surface 211a of the second semiconductor substrate 211”),
uppermost wiring layers (113 and 213) of the first (100) and second (kim (200) memory dies face each other ([0090] – “the first circuit layer 113 faces the second circuit layer 213” – Fig. 2A shows this), and
the first (100) and second (200) memory dies are connected by a plurality of bumps (219 – Fig. 3A – [0119] – “single blocks 911 may be spaced apart from each other and terminals 219 may be interposed to electrically connect the single blocks 911 each other”) in alignment with the TSVs (115 – Fig. 3A – [0112] – “via insulating layer 101 may surround the first through-electrode 115”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the die structure as taught by Kim into Lee and Haba.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results as stated above in claim 2.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Haba.
Regarding independent claim 17, Lee teaches:
(Currently Amended) A memory device, comprising a plurality of memory
dies including a plurality of spiral ([0117] – “In the second area 91_2, through vias 921_1 to 921_4 and front pads 923_1 to 923_4 may be connected, respectively, by using a spiral chain connection method” – Fig. 24 shows this, hereinafter ‘SPR’) through-substrate vias (TSVs) ([0117] – “through vias 921_1 to 921_4 and front pads 923_1 to 923_4” – hereinafter ‘TSV’), wherein
the plurality of memory dies are stacked with one another
the first memory die (85_1 – Fig. 24 – [0109] – “first chip 85_1”) and the second memory die (85_2 – Fig. 24 – [0109] – “second chip 85_2”) include a first analog circuit (731 – [0078] – “first chip output control module 731”) and a second analog circuit (735 – [0079] – “second chip output control module 735”), respectively, and
the first analog circuit (731) and the second analog circuit (735) provide the same functions ([0079] – “The second front IDs FID2<1:3> may be set as the same logic bit set as the first front IDs FID1<1:3>” – this describes providing the same logic function) through the common channel in first in response to command signals provided by the spiral (SPR) TSV ([0002] – “The plurality of chips included in the stacked integrated circuit may transmit data to one another in addition to control signals including commands and addresses through respective through vias”).
Lee does not expressly disclose the other limitations of claim 17.
However, in an analogous art, Haba teaches
A memory device (4 – Fig. 1 – [0027] – “stacked electronic device 4. The stacked electronic device can be used in any suitable type of electronic system, such as high bandwidth memory (HBM), hybrid memory cube (HMC) technologies, or any other suitable stacked system”), comprising a plurality of memory dies (1a-1h – Fig. 1 – [0027] – “a plurality of integrated device dies 1a-1h (e.g., memory dies, processor dies, etc.) can be stacked on top of one another”),
the plurality of memory dies (1a-1h) are stacked with one another (TSV – [0009] – “the first and second pluralities of dies are face-to-face) to define a common channel ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – hereinafter ‘COM’) in first ([6a – Fig. 10 – [0030] – “dies 6a-6d, 7a-7d within each stack 6, 7”) and second core chips ([6b – Fig. 10 – [0030] – “dies 6a-6d, 7a-7d within each stack 6, 7”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the memory device and common channel structure as taught by Haba into Lee.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 18, Lee, as modified by Haba, teaches claim 17 from which claim 18 depends. Lee further teaches
(Original) The memory device according to claim 17, wherein each of
the first (731) and second (735) analog circuits includes a power supply circuit and/or compensation capacitor circuits.
Lee does not expressly disclose the limitations of claim 18.
However, in an analogous art, Haba teaches
analog ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit) circuits includes a power supply circuit ([0040] – “The stacked device 29 of FIG. 10 can utilize common power and/or ground pathways, such that the dies of die stacks 6 and 7 can each access power through power channels 30 and ground channels 45” – the power circuit corresponds to an analog circuit) and/or compensation capacitor circuits.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the analog power supply circuit structure as taught by Haba into Lee and Kim.
An ordinary artisan would have been motivated to use the known technique of Haba in the manner set forth above to produce the predictable results as stated above in claim 1.
Pertinent Art
For the benefits of the Applicant, US 20220238448 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including chip activation structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
