DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the reply filed 08 April 2026.
Claims 1-17 and 19-21 are pending and have been presented for examination.
Claim 18 has been cancelled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5, 6, 10, 11, 14, 15, 19, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHWICK (U.S. Patent Application Publication #2022/0342806) in view of BRANDL (U.S. Patent Application Publication #2018/0019006).
1. FISHWICK discloses An apparatus comprising: a plurality of memory channels to a memory (see [0023]: connection between controller and memory; [0025]: a channel to a memory device comprises the physical connections to the device), the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice (see [0033]: memory controllers are grouped into slices, controllers 12A-12B, 12E-12F form one slice; controllers 12C-12D, 12F12G form another slice), the second slice including multiple memory channels of the plurality of memory channels (see [0033]: a slice has multiple controllers, each controller has a channel to the memory, this would result in a slice with multiple channels; [0078]: a slice can be any size down to a single channel; [0081]: the given memory slice comprises at least one of the plurality of memory channels; the system allows each slice to have one or more channels, when configured with multiple channels FISHWICK would anticipate this limitation); power control circuitry coupled to the plurality of memory channels (see [0072]: power management mechanisms built into the controllers) and configured to adjust, in accordance with a power collapse trigger condition associated with the first slice (see [0063]: monitor system activity), operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice (see [0062]: placing memory controllers in a low power mode; [0066]: one slice can be folded and placed in a lower power state independently of another slice), wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation (see [0062]: transfer to a lower power mode, this indicates one mode has a lower power consumption mode than the other mode); and circuitry coupled to the plurality of memory channels and configured to perform interleaving of memory access operations to the multiple memory channels of the second slice on a per-slice basis that excludes the first slice (see BRANDL below).
BRANDL discloses the following limitations that are not disclosed by FISHWICK: circuitry coupled to the plurality of memory channels (see [0066]-[0067]: memory controller that contains an address decoder to implement chip select interleaving) and configured to perform interleaving of memory access operations to the second slice on a per-slice basis that excludes the first slice (see [0068]: chip select interleaving that interleaves the address space over multiple DIMM ranks on a channel). Interleaving access over multiple ranks on a channel is done using chip select interleaving. This type of interleaving reduces page conflicts and makes more DRAM banks available (see [0068]). The interleaving disclosed by BRANDL would be compatible with the system disclosed by FISHWICK as both systems are accessing DRAM memory (see FISHWICK [0023]; BRANDL [0068]). When one slice in the system of FISHWICK is in a low power state, the other slice that is being accessed would perform the chip select interleaving disclosed by FISHWICK. This access would exclude interleaving on the slice in the low power mode.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to perform interleaving among multiple channels on one slice, as disclosed by BRANDL. One of ordinary skill in the art would have been motivated to make such a modification to reduce page conflicts in a memory channel, as taught by BRANDL. FISHWICK and BRANDL are analogous/in the same field of endeavor as both references are directed to accessing DRAM memory systems.
2. The apparatus of claim 1, wherein the power control circuitry is further configured to: detect a power resume trigger condition associated with the first slice (see FISHWICK [0074]: unfolding when increased memory/bandwidth is needed by running applications); and based on detecting the power resume trigger condition, adjust operation of the first slice from the second mode to the first mode independently of the second slice (see FISHWICK [0077]: for a slice being unfolded the memory controller exits self-refresh mode/low power mode).
5. The apparatus of claim 1, further comprising a power collapse manager that is coupled to the power control circuitry and that is configured to detect the power collapse trigger condition (see FISHWICK [0063]: monitor activity in the system to determine if a slice can be disabled).
6. The apparatus of claim 5, wherein the power collapse manager is further configured to detect the power collapse trigger condition based on one or more of a software workload of a processor that is associated with the first slice, a hardware usage level associated with the first slice, or a vote metric associated with one or more processors including the processor (see FISHWICK [0065]: monitor activity of applications accessing pages in memory).
10. FISHWICK discloses A method comprising: accessing a memory using a plurality of memory channels (see [0023]: connection between controller and memory; [0025]: a channel to a memory device comprises the physical connections to the device), the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice (see [0033]: memory controllers are grouped into slices, controllers 12A-12B, 12E-12F form one slice; controllers 12C-12D, 12F12G form another slice), wherein the second slice includes multiple memory channels of the plurality of memory channels (see [0033]: a slice has multiple controllers, each controller has a channel to the memory, this would result in a slice with multiple channels; [0078]: a slice can be any size down to a single channel; [0081]: the given memory slice comprises at least one of the plurality of memory channels; the system allows each slice to have one or more channels, when configured with multiple channels FISHWICK would anticipate this limitation), and wherein accessing the memory includes performing interleaving of memory access operations to the multiple memory channels of the second slice on a per-slice basis that excludes the first slice (see BRANDL below); and in accordance with a power collapse trigger condition associated with the first slice (see [0063]: monitor system activity), adjusting operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice (see [0062]: placing memory controllers in a low power mode; [0066]: one slice can be folded and placed in a lower power state independently of another slice), wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation (see [0062]: transfer to a lower power mode, this indicates one mode has a lower power consumption mode than the other mode).
BRANDL discloses the following limitations that are not disclosed by FISHWICK: perform interleaving of memory access operations to the second slice on a per-slice basis that excludes the first slice (see [0068]: chip select interleaving that interleaves the address space over multiple DIMM ranks on a channel). Interleaving access over multiple ranks on a channel is done using chip select interleaving. This type of interleaving reduces page conflicts and makes more DRAM banks available (see [0068]). The interleaving disclosed by BRANDL would be compatible with the system disclosed by FISHWICK as both systems are accessing DRAM memory (see FISHWICK [0023]; BRANDL [0068]). When one slice in the system of FISHWICK is in a low power state, the other slice that is being accessed would perform the chip select interleaving disclosed by FISHWICK. This access would exclude interleaving on the slice in the low power mode.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to perform interleaving among multiple channels on one slice, as disclosed by BRANDL. One of ordinary skill in the art would have been motivated to make such a modification to reduce page conflicts in a memory channel, as taught by BRANDL. FISHWICK and BRANDL are analogous/in the same field of endeavor as both references are directed to accessing DRAM memory systems.
11. The method of claim 10, further comprising: detecting a power resume trigger condition associated with the first slice (see FISHWICK [0074]: unfolding when increased memory/bandwidth is needed by running applications); and based on detecting the power resume trigger condition, adjusting operation of the first slice from the second mode to the first mode independently of the second slice (see FISHWICK [0077]: for a slice being unfolded the memory controller exits self-refresh mode/low power mode).
14. The method of claim 10, further comprising detecting the power collapse trigger condition using a power collapse manager (see FISHWICK [0063]: monitor activity in the system to determine if a slice can be disabled).
15. The method of claim 14, wherein the power collapse trigger condition is detected based on one or more of a software workload of a processor that is associated with the first slice, a hardware usage level associated with the first slice, or a vote metric associated with one or more processors including the processor (see FISHWICK [0065]: monitor activity of applications accessing pages in memory).
19. FISHWICK discloses A non-transitory computer-readable medium storing instructions executable by one or more processors to initiate, perform, or control operations (see [0095]: storage media accessible by a computer to provide instructions), the operations comprising: accessing a memory using a plurality of memory channels (see [0023]: connection between controller and memory; [0025]: a channel to a memory device comprises the physical connections to the device), the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice (see [0033]: memory controllers are grouped into slices, controllers 12A-12B, 12E-12F form one slice; controllers 12C-12D, 12F12G form another slice), wherein the second slice includes multiple memory channels of the plurality of memory channels (see [0033]: a slice has multiple controllers, each controller has a channel to the memory, this would result in a slice with multiple channels; [0078]: a slice can be any size down to a single channel; [0081]: the given memory slice comprises at least one of the plurality of memory channels; the system allows each slice to have one or more channels, when configured with multiple channels FISHWICK would anticipate this limitation), and wherein accessing the memory includes performing interleaving of memory access operations to the multiple memory channels of the second slice on a per-slice basis that excludes the first slice (see BRANDL below); and in accordance with a power collapse trigger condition associated with the first slice (see [0063]: monitor system activity), adjusting operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice (see [0062]: placing memory controllers in a low power mode; [0066]: one slice can be folded and placed in a lower power state independently of another slice), wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation (see [0062]: transfer to a lower power mode, this indicates one mode has a lower power consumption mode than the other mode).
BRANDL discloses the following limitations that are not disclosed by FISHWICK: perform interleaving of memory access operations to the second slice on a per-slice basis that excludes the first slice (see [0068]: chip select interleaving that interleaves the address space over multiple DIMM ranks on a channel). Interleaving access over multiple ranks on a channel is done using chip select interleaving. This type of interleaving reduces page conflicts and makes more DRAM banks available (see [0068]). The interleaving disclosed by BRANDL would be compatible with the system disclosed by FISHWICK as both systems are accessing DRAM memory (see FISHWICK [0023]; BRANDL [0068]). When one slice in the system of FISHWICK is in a low power state, the other slice that is being accessed would perform the chip select interleaving disclosed by FISHWICK. This access would exclude interleaving on the slice in the low power mode.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to perform interleaving among multiple channels on one slice, as disclosed by BRANDL. One of ordinary skill in the art would have been motivated to make such a modification to reduce page conflicts in a memory channel, as taught by BRANDL. FISHWICK and BRANDL are analogous/in the same field of endeavor as both references are directed to accessing DRAM memory systems.
20. The non-transitory computer-readable medium of claim 19, wherein the operations further comprise: detecting a power resume trigger condition associated with the first slice (see FISHWICK [0074]: unfolding when increased memory/bandwidth is needed by running applications); and based on detecting the power resume trigger condition, adjusting operation of the first slice from the second mode to the first mode independently of the second slice (see FISHWICK [0077]: for a slice being unfolded the memory controller exits self-refresh mode/low power mode).
21. The apparatus of claim 1, wherein the circuitry is further configured to perform the interleaving of the memory access operations to the second slice on the per-slice basis to enable selective deactivation of the first slice independently of the second slice (see FISHWICK [0062]: placing memory controllers in a low power mode; [0066]: one slice can be folded and placed in a lower power state independently of another slice).
Claim(s) 3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHWICK (U.S. Patent Application Publication #2022/0342806) and BRANDL (U.S. Patent Application Publication #2018/0019006) as applied to claims 1, 2, 5, 6, 10, 11, 14, 15, 19, 20 and 21 above, and further in view of NACHIMUTHU (U.S. Patent Application Publication #2014/0143577).
3. The apparatus of claim 1 (see FISHWICK above), wherein the first slice and the second slice each include a system level cache (SLC) controller, a memory controller coupled to the SLC controller (see NACHIMUTHU below), and a physical interface between the memory controller and the memory (see FISHWICK [0025]: physical connections to the memory device).
NACHIMUTHU discloses the following limitations that are not disclosed by FISHWICK: wherein the first slice and the second slice each include a system level cache (SLC) controller (see [0048]-[0051]: various levels of memory including a memory side cache {system level cache}; [0053]: high speed memory that is part of the system memory address range to be used as a write buffer or scratchpad memory), a memory controller coupled to the SLC controller (see FISHWICK [0022]-[0023]: circuitry is already present for controlling access to the memory, a combination of FISHWICK and NACHIMUTHU would result in this circuitry being coupled to the SLC controller disclosed by NACHIMUTHU). Having a system level cache helps solve the challenges regarding memory power and cost (see [0021]-[0022]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include and SLC controller, as disclosed by NACHIMUTHU. One of ordinary skill in the art would have been motivated to make such a modification to incorporate high speed memory while limiting the increase in memory power and cost, as taught by NACHIMUTHU. FISHWICK and NACHIMUTHU are analogous/in the same field of endeavor as both references are directed to accessing multiple memories.
12. The method of claim 10 (see FISHWICK above), wherein the first slice and the second slice each include a system level cache (SLC) controller, a memory controller coupled to the SLC controller, and a physical interface between the memory controller and the memory (see NACHIMUTHU below).
NACHIMUTHU discloses the following limitations that are not disclosed by FISHWICK: wherein the first slice and the second slice each include a system level cache (SLC) controller (see [0048]-[0051]: various levels of memory including a memory side cache {system level cache}; [0053]: high speed memory that is part of the system memory address range to be used as a write buffer or scratchpad memory), a memory controller coupled to the SLC controller (see FISHWICK [0022]-[0023]: circuitry is already present for controlling access to the memory, a combination of FISHWICK and NACHIMUTHU would result in this circuitry being coupled to the SLC controller disclosed by NACHIMUTHU). Having a system level cache helps solve the challenges regarding memory power and cost (see [0021]-[0022]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include and SLC controller, as disclosed by NACHIMUTHU. One of ordinary skill in the art would have been motivated to make such a modification to incorporate high speed memory while limiting the increase in memory power and cost, as taught by NACHIMUTHU. FISHWICK and NACHIMUTHU are analogous/in the same field of endeavor as both references are directed to accessing multiple memories.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHWICK (U.S. Patent Application Publication #2022/0342806) and BRANDL (U.S. Patent Application Publication #2018/0019006) as applied to claims 1, 2, 5, 6, 10, 11, 14, 15, 19, 20 and 21 above, and further in view of BEKERMAN (U.S. Patent Application Publication #2025/0104742).
4. The apparatus of claim 1 (see FISHWICK above), wherein the plurality of memory channels are coupled to one or more power supply nodes, and wherein the power control circuitry includes, for each slice of the plurality of memory channels, a power gating circuit that is coupled to the one or more power supply nodes and that is configured to selectively disconnect the slice from the one or more power supply nodes (see BEKERMAN below).
BEKERMAN discloses the following limitations that are not disclosed by FISHWICK: wherein the plurality of memory channels are coupled to one or more power supply nodes, and wherein the power control circuitry includes, for each slice of the plurality of memory channels, a power gating circuit that is coupled to the one or more power supply nodes and that is configured to selectively disconnect the slice from the one or more power supply nodes (see [0025]: power management circuitry to allow for power gating; [0033]: maintain power state for a memory resource using power gating operations). BEKERMAN discloses a power gating operation to regulate power supplied to a memory resource. It is implicit that there is a power supply node since the memory is receiving power. FISHWICK already discloses the ability to increase or decrease the power supplied to a memory channel, but FISHWICK does not disclose the specifics of how that is accomplished. BEKERMAN discloses a well-known solution to managing power for a memory resource, which is power gating.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include a power gating circuit, as disclosed by BEKERMAN. One of ordinary skill in the art would have been motivated to make such a modification since a power gating circuit is a well-known solution for managing power to a memory resource, as taught by BEKERMAN. FISHWICK and BEKERMAN are analogous/in the same field of endeavor as both references are directed to management of power for a memory resource.
13. The method of claim 10 (see FISHWICK above), further comprising, for each slice of the plurality of memory channels, selectively disconnecting the slice from one or more power supply nodes using power control circuitry (see BEKERMAN below).
BEKERMAN discloses the following limitations that are not disclosed by FISHWICK: for each slice of the plurality of memory channels, selectively disconnecting the slice from one or more power supply nodes using power control circuitry (see [0025]: power management circuitry to allow for power gating; [0033]: maintain power state for a memory resource using power gating operations). BEKERMAN discloses a power gating operation to regulate power supplied to a memory resource. It is implicit that there is a power supply node since the memory is receiving power. FISHWICK already discloses the ability to increase or decrease the power supplied to a memory channel, but FISHWICK does not disclose the specifics of how that is accomplished. BEKERMAN discloses a well-known solution to managing power for a memory resource, which is power gating.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include a power gating circuit, as disclosed by BEKERMAN. One of ordinary skill in the art would have been motivated to make such a modification since a power gating circuit is a well-known solution for managing power to a memory resource, as taught by BEKERMAN. FISHWICK and BEKERMAN are analogous/in the same field of endeavor as both references are directed to management of power for a memory resource.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHWICK (U.S. Patent Application Publication #2022/0342806) and BRANDL (U.S. Patent Application Publication #2018/0019006) as applied to claims 1, 2, 5, 6, 10, 11, 14, 15, 19, 20 and 21 above, and further in view of YANG (U.S. Patent Application Publication #2023/0041476).
7. The apparatus of claim 1 (see FISHWICK above), wherein the circuitry includes a memory network-on-chip (NoC) coupled to the plurality of memory channels and to the memory, wherein the memory NoC is configured to operate in accordance with a slice-based interleaving scheme (see YANG below).
YANG discloses the following limitations that are not disclosed by FISHWICK: a memory network-on-chip (NoC) coupled to the plurality of memory channels and to the memory (see [0045]: network-on-chip subsystem coupled to a host processor), wherein the memory NoC is configured to operate in accordance with a slice-based interleaving scheme (see BRANDL [0066]-[0068]: a combination of FISHWICK and BRANDL would result in interleaving among the channels in a slice). An NOC brings notable improvements over conventional bus and crossbar architectures (see [0045]). The NOC disclosed by YANG would improve the scalability and communication of the host processor disclosed by FISHWICK.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include an NOC, as disclosed by YANG. One of ordinary skill in the art would have been motivated to make such a modification to improve scalability and communication, as taught by YANG. FISHWICK and YANG are analogous/in the same field of endeavor as both references are directed to communication with memory systems.
16. The method of claim 10 (see FISHWICK above), wherein the memory is accessed via a memory network-on-chip (NoC) and in accordance with a slice-based interleaving scheme (see YANG below).
YANG discloses the following limitations that are not disclosed by FISHWICK: wherein the memory is accessed via a memory network-on-chip (NoC) (see [0045]: network-on-chip subsystem coupled to a host processor) and in accordance with a slice-based interleaving scheme (see BRANDL [0066]-[0068]: a combination of FISHWICK and BRANDL would result in interleaving among the channels in a slice). An NOC brings notable improvements over conventional bus and crossbar architectures (see [0045]). The NOC disclosed by YANG would improve the scalability and communication of the host processor disclosed by FISHWICK.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to include an NOC, as disclosed by YANG. One of ordinary skill in the art would have been motivated to make such a modification to improve scalability and communication, as taught by YANG. FISHWICK and YANG are analogous/in the same field of endeavor as both references are directed to communication with memory systems.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHWICK (U.S. Patent Application Publication #2022/0342806) and BRANDL (U.S. Patent Application Publication #2018/0019006) as applied to claims 1, 2, 5, 6, 10, 11, 14, 15, 19, 20 and 21 above, and further in view of CHEN (U.S. Patent Application Publication #2020/0133903).
9. The apparatus of claim 1 (see FISHWICK above), wherein the memory corresponds to a hybrid memory including a first memory of a first memory type and a second memory of a second memory type different than the first memory type, wherein the first slice is associated with the first memory, and wherein the second slice is associated with the second memory (see CHEN below).
CHEN discloses the following limitations that are not disclosed by FISHWICK: wherein the memory corresponds to a hybrid memory including a first memory of a first memory type and a second memory of a second memory type different than the first memory type (see [0015]: multi-channel interface where each channel can be coupled to a different type of memory; [0020]-[0021]: each channel controller can be configured with a different protocol for interfacing with a particular type of memory), wherein the first slice is associated with the first memory, and wherein the second slice is associated with the second memory (see [0018]-[0019]: each channel is associated with memory). The use of a multi-channel memory configuration that allows for different protocols to be used creates a more flexible memory system through the ability to utilize advanced new media features (see [0003], [0016]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FISHWICK to incorporate a hybrid memory, as disclosed by CHEN. One of ordinary skill in the art would have been motivated to make such a modification to create a flexible memory system that is able to make use of advanced new media features, as taught by CHEN. FISHWICK and CHEN are analogous/in the same field of endeavor as both references are directed to multi-channel memory systems.
Allowable Subject Matter
Claims 8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the state of the art fails to anticipate, or render obvious, “… the slice-based interleaving scheme enables an intra-slice interleaving of the memory access operations within the first slice and disables an inter-slice interleaving of the memory access operations between the first slice and the second slice.”
FISHWICK discloses memory slices with multiple channels and BRANDL discloses interleaving memory accesses using multiple channels. The references, individually or in combination, do not disclose inter-slice interleaving between the first slice and the second slice. Since that type of interleaving is not disclosed, the references would not disclose disabling that type of access.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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