DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 08/31/2026 is acknowledged. Claims 20-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/31/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-5, and 11-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Seo et al. (US 2023/0079392 A1; hereinafter “Seo”).
In regard to claim 1, Seo teaches a semiconductor integrated circuit (IC) device (a resistive random access memory (ReRAM) integrated in a back-end-of-the-line (BEOL) fat wire level as shown in Figs. 18A-18C and Figs. 19A-19C) ( Figs. 18A-18C, Figs. 19A-19C and paragraph 1), comprising:
a bottom wire level (a fat level first interconnect dielectric material layer 12) and a top wire level (a fat level second interconnect dielectric material layer 32) (Fig. 19A-19C and paragraph 66);
a first region (a region containing a fill area contact opening 68A) with a first vertical dimension (D1) between the bottom wire level and the top wire level (the first vertical dimension D1 contains the thickness of the underlying top electrode 26A and all components deposited there under between the fat level second interconnect dielectric material layer 32) (annotated Fig. 18A and Fig. 18B)) (Fig. 18A, Fig. 19A and paragraphs 53, 64-65 and 74); and
a second region (a region containing a combined logic device area contact opening 68B) with a second vertical dimension (D2) between the bottom wire level and the top wire level that is less than the first vertical dimension (as shown in annotated Fig. 18A and Fig. 18B, as D2 is determined by the thickness of the original dielectric material stack 50 and 52, which means the first vertical dimensions D1 that contains the thickness of the underlying top electrode 26A would be greater) (annotated Fig. 18A and Fig. 18B).
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In regard to claim 2, Seo teaches wherein a top surface of the top wire level in the first region is coplanar with a top surface of the top wire level in the second region (as each of the fill area, the logic device area and the ReRAM device area are located laterally adjacent to each other, the coplanar surfaces of the fat level second interconnect dielectric material layer 32 in the fill area, the logic device area and the ReRAM device area will also be coplanar with one another such as fill area second electrically conductive structure 46A and second electrically conductive structure 46B) (paragraph 10).
In regard to claim 3, Seo teaches wherein a bottom surface of the top wire level in the second region is below a bottom surface of the top wire level in the first region (the portion of the bottom surface of the second interconnect dielectric material layer 32 above the fill area ReRAM-containing stack 24A/26A in the aforementioned first region is above the bottom surface of the second interconnect dielectric material layer 32 in the aforementioned second region) (Fig. 18A and Fig. 18B).
In regard to claim 4, Seo teaches further comprising:
a via level that directly connects the bottom wire level to the top wire level (via levels VA1 and VA2 are shown in annotated Figs. 18A and 18B above).
In regard to claim 5, Seo teaches wherein a vertical height of the via level in the first region is greater than a vertical height of the via level in the second region (as shown in annotated Fig. 18A and Fig. 18B, the vertical height of VA1 is greater than VA2 due to the via of the second region VA2 only corresponding to the thickness of the original dielectric material stack 50 and 52).
In regard to claim 11, Seo teaches a semiconductor integrated circuit (IC) device (a resistive random access memory (ReRAM) integrated in a back-end-of-the-line (BEOL) fat wire level as shown in Figs. 18A-18C and Figs. 19A-19C) ( Figs. 18A-18C, Figs. 19A-19C and paragraph 1) comprising:
a first region (a region containing a fill area contact opening 68A) comprising a first bottom wire (a first electrically conductive structure 16A), a first top wire (a fill area second electrically conductive structure 46A), and a first via (a via V1 containing a fill area base electrode 60A and underlying top electrode 26A as shown in annotated Fig. 18A below) directly connected to the first bottom wire and directly connected to the first top wire (Fig. 18A, Fig. 19A and paragraphs 102, 122, and 126);
a second region (a region containing a combined logic device area contact opening 68B) comprising a second bottom wire (logic device area first electrically conductive structure 16B), a second top wire (an upper portion of a logic device area second electrically conductive structure 46B), and a second via (a via V2 containing a lower portion of the logic device area second electrically conductive structure 46B as shown in annotated Fig. 18B below) directly connected to the second bottom wire and directly connected to the second top wire (Fig. 18B, Fig. 19B and paragraphs 120 and 123);
wherein a first vertical dimension (D1) between the first bottom wire and the first top wire is greater than a second vertical dimension (D2) between the second bottom wire and the second top wire (as shown in annotated Fig. 18A and Fig. 18B, D2 is determined by the thickness of the original dielectric material stack 50 and 52, the first vertical dimensions D1 that contains the thickness of the underlying top electrode 26A would be greater) (annotated Fig. 18A and Fig. 18B).
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In regard to claim 12, Seo teaches wherein a top surface of the first top wire is coplanar with a top surface of the second top wire (as each of the fill area, the logic device area and the ReRAM device area are located laterally adjacent to each other the coplanar surfaces of the fat level second interconnect dielectric material layer 32 in the fill area, the logic device area and the ReRAM device area will also be coplanar with one another such as fill area second electrically conductive structure 46A and second electrically conductive structure 46B) (paragraphs 10 and 78-79).
In regard to claim 13, Seo teaches wherein a bottom surface of the second top wire is below a bottom surface of the first top wire (as shown in annotated Fig 18B above, the bottom of the upper portion of the logic device area second electrically conductive structure 46B begins at the top surface of the dielectric material layer 52 as shown in annotated Fig. 18B above, therefore, bottom surface 46B is below the bottom surface of the fill area second electrically conductive structure 46A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7, 14-15, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Seo as applied to claim 5 above, in view of Ponoth et al. (US 2012/0068346 A1; hereinafter “Ponoth”).
In regard to claim 6, Seo doesn’t explicitly teach wherein respective wires, within the top wire level, wrap around respective vias within the via level within the second region.
Ponoth teaches a semiconductor integrated circuit (IC) device (a semiconductor structure as shown in Fig. 4C) (Fig. 4C and paragraph 1), comprising:
wherein respective wires (a second metal layer 420 in the first and second regions R1 and R2) (annotated Fig. 4C and paragraph 35), within a top wire level (dielectric layer 460) (Fig. 4C and paragraph 40), wrap around respective vias (protrusions 221 and 222) within the via level within the second region (as shown in annotated Fig. 4C below the protrusions 221 and 222 are shown inset in the layer 420 in their respective regions)( Fig. 4B, Fig. 4C. and paragraphs 29, 36 and 40).
It would be obvious to one skilled in the art to combine the teachings of Seo with the teachings of Ponoth to have the top wire level, wrap around respective vias within the via level within the second region since this enables formation of a semiconductor interconnect structure that can have higher than conventional aspect ratios (Ponoth paragraph 7).
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In regard to claim 7, Seo teaches wherein adjacent wires within the bottom wire level are horizontally separated by a first dielectric material (each of the fill area, the logic device area and the ReRAM device area are located laterally adjacent to each other therefore, the dielectric material layer 12 functions as a first dielectric material).
In regard to claim 14, Seo doesn’t explicitly teach wherein the second top wire directly contacts a top surface of the second via and directly contacts one or more side surface(s) of the second via.
Ponoth teaches a semiconductor integrated circuit (IC) device (a semiconductor structure as shown in Fig. 4C) (Fig. 4C and paragraph 1),
wherein a second top wire (a layer 420 in the second region R2) directly contacts a top surface of a second via (structure 222) and directly contacts one or more side surface(s) of the second via (in a second region as shown in annotated Fig. 4C, below the structure 222 is shown inset in a layer 420)(Fig. 4B, Fig. 4C. and paragraphs 29, 36 and 40).
It would be obvious to one skilled in the art to combine the teachings of Seo with the teachings of Ponoth to have the second top wire directly contact a top surface of the second via and directly contact one or more side surfaces of the second via since this enables formation of a semiconductor interconnect structure that can have higher than conventional aspect ratios (Ponoth paragraph 7).
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In regard to claim 15, Seo in view of Ponoth teaches wherein the second top wire wraps around the second via (in a second region as shown in annotated Fig. 4C above the structure 222 is shown inset in a layer 420)(Fig. 4B, Fig. 4C. and paragraphs 29, 36 and 40).
In regard to claim 24,Seo teaches a semiconductor integrated circuit (IC) device (a resistive random access memory (ReRAM) integrated in a back-end-of-the-line (BEOL) fat wire level as shown in Figs. 18A-18C and Figs. 19A-19C) ( Figs. 18A-18C, Figs. 19A-19C and paragraph 1) comprising:
a first region (a region containing a fill area contact opening 68A) comprising a first bottom wire (a first electrically conductive structure 16A), a first top wire (a fill area second electrically conductive structure 46A), and a first via (a via V1 containing a fill area base electrode 60A and underlying top electrode 26A as shown in annotated Fig. 18A below) directly connected to a top surface of the first bottom wire and directly connected to a bottom surface of the first top wire (the first via V1 is shown connected to the bottom of fill area second electrically conductive structure 46A and top of first electrically conductive structure 16A in annotated Fig. 18A above) (Fig. 18A, Fig. 19A and paragraphs 102, 122, and 126); and
a second region (a region containing a combined logic device area contact opening 68B) comprising a second bottom wire (logic device area first electrically conductive structure 16B), a second top wire (a logic device area second electrically conductive structure 46B) (Fig. 18B, Fig. 19B and paragraphs 120 and 123); a second via (a via V2 containing a lower portion of the logic device area second electrically conductive structure 46B as shown in annotated Fig. 18A below) directly connected to a top surface of the second bottom wire (the lower portion of the logic device area second electrically conductive structure 46B is shown on the topside of the logic device area first electrically conductive structure 16B in Fig. 18B).
However, Seo doesn’t explicitly teach and the second via directly connected to a top surface of the second bottom wire and inset within the second top wire.
Ponoth teaches a semiconductor integrated circuit (IC) device (a semiconductor structure as shown in Fig. 4C) (Fig. 4C and paragraph 1) comprising:
a second via (structure 222) directly connected to a top surface of a second bottom wire (structure 215) and inset within a second top wire (in a second region as shown in annotated Fig. 4C below the structure 222 is shown inset in a layer 420)(Fig. 4B, Fig. 4C. and paragraphs 29, 36 and 40).
It would be obvious to one skilled in the art to combine the teachings of Seo with the teachings of Ponoth to have the second via directly connected to a top surface of the second bottom wire and inset within the second top wire since this enables formation of a semiconductor interconnect structure that can have higher than conventional aspect ratios (Ponoth paragraph 7).
In regard to claim 25, Seo teaches a semiconductor integrated circuit (IC) device (a resistive random access memory (ReRAM) integrated in a back-end-of-the-line (BEOL) fat wire level as shown in Figs. 18A-18C and Figs. 19A-19C) ( Figs. 18A-18C, Figs. 19A-19C and paragraph 1), comprising:
a bottom wire level (a fat level first interconnect dielectric material layer 12) and a top wire level (a fat level second interconnect dielectric material layer 32) (Fig. 18A-18C and paragraph 66);
a first region (a region containing a fill area contact opening 68A) comprising a first bottom wire (a first electrically conductive structure 16A) within the bottom wire level and a first top wire within the top wire level (Fig. 18A-18C and paragraphs 36 and 120); and
a second region (a region containing a combined logic device area contact opening 68B) comprising a second bottom wire (logic device area first electrically conductive structure 16B) within the bottom wire level (Fig. 18B, paragraphs 37 and 120), a second top wire within the top wire level (a logic device area second electrically conductive structure 46B) (Fig. 18B, Fig. 19B and paragraphs 120 and 123), and a via (a via V2 containing a lower portion of the logic device area second electrically conductive structure 46B as shown in annotated Fig. 18A above) connected to the second bottom wire (the lower portion of the logic device area second electrically conductive structure 46B is shown on the topside of the logic device area first electrically conductive structure 16B in Fig. 18B)
However, Seo doesn’t explicitly teach the via connected to the second bottom wire and inset within the second top wire.
Ponoth teaches a semiconductor integrated circuit (IC) device comprising:
a via (structure 222) connected to a second bottom wire (structure 215) and inset within a second top wire (in a second region as shown in annotated Fig. 4C below the structure 222 is shown inset in a layer 420)(Fig. 4B, Fig. 4C. and paragraphs 29, 36 and 40).
It would be obvious to one skilled in the art to combine the teachings of Seo with the teachings of Ponoth to have the via connected to the second bottom wire and inset within the second top wire since this enables formation of a semiconductor interconnect structure that can have higher than conventional aspect ratios (Ponoth paragraph 7).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Ponton as applied to claim 7 above, and further in view of Chen et al. (US 2021/0384074 A1; hereinafter “Chen”)
In regard to claim 8, Seo teaches wherein adjacent wires within the top wire level are horizontally separated by a separation block comprising an etch stop layer that is directly upon the via level.
Chen teaches a semiconductor integrated circuit (IC) device (a semiconductor structure 200) (Fig. 19A and paragraph 43), wherein adjacent wires (second metal features 238) within top wire level are horizontally separated by a separation block comprising an etch stop layer that is directly upon the via level (the separation block formed of a second ESL 226 and a second ILD layer 228 are shown on the via level (via) and separating the second metal features 238 in annotated Fig 19A below) (annotated Fig. 19A and paragraphs 39 and 44).
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It would have been obvious to one skilled in the art at the time to combine the teachings of Seo in view of Ponoth with the teachings of Chen to have adjacent wires within the top wire level are horizontally separated by a separation block comprising an etch stop layer that is directly upon the via level since this layout is well known amongst those skilled in the art to allow for separation of conductive components and prevents unwanted shorts within the device.
In regard to claim 9, Seo in view of Ponoth and Chen teach teaches herein the separation block further comprises a second dielectric material (the second ILD layer 228) directly upon the etch stop layer (the second ILD layer 228B is shown on the second ESL 226) (Fig. 18A).
In regard to claim 10, Seo teaches wherein the second dielectric material is different relative to the first dielectric material (the fat level second interconnect dielectric material layer 32 can be compositionally the same as, or compositionally different from, the fat level first interconnect dielectric material layer 12) (paragraph 66).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Ponoth as applied to claim 6 above, in view of Juengling (US 2019/0067193 A1)
In regard to claim 16, Seo in view of Ponoth doesn’t explicitly teach wherein the first region further comprises one or more additional first top wires with respective bottom surface(s) that are coplanar with a bottom surface of the first top wire.
Juengling teaches a semiconductor integrated circuit (IC) device,
wherein a first region (a first region as shown in annotated Fig. 4 below) further comprises one or more additional first top wires (one of a plurality of conductive structures 12) with respective bottom surface(s) that are coplanar with a bottom surface of a first top wire (as shown in annotated Fig. 4 the plurality of conductive structures 12 have bottom surfaces coplanar with one another) (annotated Fig. 4 and paragraph 25).
It would have been obvious to one skilled in the art to combine the teachings of Seo in view of Ponoth with the teachings of Juengling to have the first region further comprise one or more additional first top wires with respective bottom surface(s) that are coplanar with a bottom surface of the first top wire since this is well known in the art to enhance the functionality of the device by adding more connections within the device.
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In regard to claim 17, Seo in view of Ponoth and Juengling teaches wherein a second region (a second region as shown in annotated Fig. 4 above) further comprises one or more additional second top wires (one of a plurality of conductive structures 12) with respective bottom surface(s) that are coplanar with a bottom surface of the second top wire (as shown in annotated Fig. 4, the plurality of conductive structures 12 have bottom surfaces coplanar with one another) (annotated Fig. 4 and paragraph 25).
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Ponton and Juengling as applied to claim 17 above, and further in view of Chen et al. (US 2021/0384074 A1; hereinafter “Chen”).
In regard to claim 18, Seo in view of Ponton and Juengling don’t explicitly teach Seo in view of Ponton and Juengling wherein a first isolation block separates the first top wire from one or more additional first top wires, the first isolation block comprising a first etch stop layer and a first dielectric material upon the first etch stop layer and wherein a second isolation block separates the second top wire from one or more additional second top wires, the second isolation block comprising a second etch stop layer and a second dielectric material upon the second etch stop layer.
Chen teaches a semiconductor integrated circuit (IC) device (a semiconductor structure 200) (Fig. 19A and paragraph 43),
wherein a first isolation block (a second ILD layer 228 and a second ESL 226 in the annotated first region) separates a first top wire (a second metal feature 238 over interface 240) from one or more additional first top wires (the second ILD layer 228 and the second ESL 226 in the annotated first region is shown separating the second metal feature 238 over interface 240 and the second metal feature 238 not over interface 240) (annotated Fig. 19A, paragraphs 37 and 44), the first isolation block comprising a first etch stop layer (the second ESL 226) and a first dielectric material (the second ILD layer 228) upon the first etch stop layer and wherein a second isolation block (a second ILD layer 228 and a second ESL 226 in the annotated second region) separates the second top wire from one or more additional second top wires (the second ILD layer 228 and the second ESL 226 in the annotated second region is shown separating the second metal feature 238 over interface 240 and the second metal feature 238 not over interface 240) (annotated Fig. 19A, paragraphs 37 and 44), the second isolation block comprising a second etch stop layer (the second ESL 226 in the second region as shown in annotated Fig. 19A) and a second dielectric material (the second ILD layer 228 in the second region as shown in annotated Fig. 19A) upon the second etch stop layer (annotated Fig. 19A, paragraphs 37 and 44).
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It would’ve been obvious to combine the teachings of Seo in view of Ponoth and Juengling with the teachings of Chen to have a first isolation block separate the first top wire from one or more additional first top wires, the first isolation block comprise a first etch stop layer and a first dielectric material upon the first etch stop layer and wherein a second isolation block separate the second top wire from one or more additional second top wires, where the second isolation block comprises a second etch stop layer and a second dielectric material upon the second etch stop layer, since this layout is well known amongst those skilled in the art to allow for separation of conductive components and prevents unwanted shorts within the device.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Ponton, Juengling and Chen as applied to claim 18 above, and further in view of Seo as taught in 10A-10C
In regard to claim 19, Seo as taught in Fig. 19A-19C, in view of Ponton, Juengling and Chen don’t explicitly teach wherein the second etch stop layer is below the first etch stop layer..
Seo as taught in Fig. 10A-10C teaches, a semiconductor integrated circuit (IC) device, wherein a second etch stop layer (a dielectric encapsulation layer 30L) is below a first etch stop layer (as shown in Figs. 10B and 10C the second etch stop layer which corresponds to the dielectric encapsulation layer 30L is lower than the first etch stop layer which corresponds to the dielectric encapsulation structure 31A) (annotated Fig. 10B, annotated Fig. 10C and paragraphs 63 and 65).
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It would have been obvious for one skilled in the art to combine the teachings of Seo in view of Ponton, Juengling and Chen with the teachings of Seo as shown in Figs. 10A-10C to have the second etch stop layer below the first etch stop layer since it is well known amongst those in the arts to form etch stop layers in order protect components in the device during manufacture. Further it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anderson et al. (US 2006/0057835 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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